UefiCpuPkg PiSmmCpuDxeSmm: Fixed #double fault on #page fault for IA32

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmFuncsArch.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
index 6844c3fc499d810bb041a38ae04084f934f090e7..6a5d453242ff43b362451aaa2a94a51066bc225e 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
@@ -1,7 +1,7 @@
 /** @file\r
   SMM CPU misc functions for x64 arch specific.\r
   \r
-Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -14,6 +14,30 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
+EFI_PHYSICAL_ADDRESS                mGdtBuffer;\r
+UINTN                               mGdtBufferSize;\r
+\r
+/**\r
+  Initialize IDT for SMM Stack Guard.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InitializeIDTSmmStackGuard (\r
+  VOID\r
+  )\r
+{\r
+  IA32_IDT_GATE_DESCRIPTOR  *IdtGate;\r
+\r
+  //\r
+  // If SMM Stack Guard feature is enabled, set the IST field of\r
+  // the interrupt gate for Page Fault Exception to be 1\r
+  //\r
+  IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r
+  IdtGate += EXCEPT_IA32_PAGE_FAULT;\r
+  IdtGate->Bits.Reserved_0 = 1;\r
+}\r
+\r
 /**\r
   Initialize Gdt for all processors.\r
   \r
@@ -41,8 +65,10 @@ InitGdt (
   // on each SMI entry.\r
   //\r
   GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned\r
-  GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));\r
+  mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
+  GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r
   ASSERT (GdtTssTables != NULL);\r
+  mGdtBuffer = (UINTN)GdtTssTables;\r
   GdtTableStepSize = GdtTssTableSize;\r
 \r
   for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r
@@ -103,24 +129,24 @@ GetProtectedModeCS (
 /**\r
   Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r
 \r
-  @param[in] ApHltLoopCode    The 32-bit address of the safe hlt-loop function.\r
-  @param[in] TopOfStack       A pointer to the new stack to use for the ApHltLoopCode.\r
-  @param[in] NumberToFinish   Semaphore of APs finish count.\r
+  @param[in] ApHltLoopCode          The address of the safe hlt-loop function.\r
+  @param[in] TopOfStack             A pointer to the new stack to use for the ApHltLoopCode.\r
+  @param[in] NumberToFinishAddress  Address of Semaphore of APs finish count.\r
 \r
 **/\r
 VOID\r
 TransferApToSafeState (\r
-  IN UINT32             ApHltLoopCode,\r
-  IN UINT32             TopOfStack,\r
-  IN UINT32             *NumberToFinish\r
+  IN UINTN  ApHltLoopCode,\r
+  IN UINTN  TopOfStack,\r
+  IN UINTN  NumberToFinishAddress\r
   )\r
 {\r
   AsmDisablePaging64 (\r
     GetProtectedModeCS (),\r
-    (UINT32) (UINTN) ApHltLoopCode,\r
-    (UINT32) (UINTN) NumberToFinish,\r
+    (UINT32)ApHltLoopCode,\r
+    (UINT32)NumberToFinishAddress,\r
     0,\r
-    TopOfStack\r
+    (UINT32)TopOfStack\r
     );\r
   //\r
   // It should never reach here\r
@@ -128,4 +154,3 @@ TransferApToSafeState (
   ASSERT (FALSE);\r
 }\r
 \r
-\r