UefiCpuPkg: Add PiSmmCpuDxeSmm module X64 files

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmInit.asm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm
new file mode 100644 (file)
index 0000000..9182f02
--- /dev/null
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm
@@ -0,0 +1,132 @@
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   SmmInit.Asm\r
+;\r
+; Abstract:\r
+;\r
+;   Functions for relocating SMBASE's for all processors\r
+;\r
+;-------------------------------------------------------------------------------\r
+\r
+EXTERNDEF   SmmInitHandler:PROC\r
+EXTERNDEF   gSmmCr0:DWORD\r
+EXTERNDEF   gSmmCr3:DWORD\r
+EXTERNDEF   gSmmCr4:DWORD\r
+EXTERNDEF   gSmmJmpAddr:QWORD\r
+EXTERNDEF   gcSmmInitTemplate:BYTE\r
+EXTERNDEF   gcSmmInitSize:WORD\r
+EXTERNDEF   mRebasedFlag:PTR BYTE\r
+EXTERNDEF   mSmmRelocationOriginalAddress:QWORD\r
+EXTERNDEF   mRebasedFlagAddr32:DWORD\r
+EXTERNDEF   mSmmRelocationOriginalAddressPtr32:DWORD\r
+EXTERNDEF   gSmmInitStack:QWORD\r
+EXTERNDEF   gcSmiInitGdtr:FWORD\r
+\r
+    .code\r
+\r
+gcSmiInitGdtr   LABEL   FWORD\r
+            DW      0\r
+            DQ      0\r
+\r
+SmmStartup  PROC\r
+    DB      66h, 0b8h                   ; mov eax, imm32\r
+gSmmCr3     DD      ?\r
+    mov     cr3, rax\r
+    DB      66h, 2eh\r
+    lgdt    fword ptr [ebp + (offset gcSmiInitGdtr - SmmStartup)]\r
+    DB      66h, 0b8h                   ; mov eax, imm32\r
+gSmmCr4     DD      ?\r
+    or      ah,  2                      ; enable XMM registers access\r
+    mov     cr4, rax\r
+    DB      66h\r
+    mov     ecx, 0c0000080h             ; IA32_EFER MSR\r
+    rdmsr\r
+    or      ah, 1                       ; set LME bit\r
+    wrmsr\r
+    DB      66h, 0b8h                   ; mov eax, imm32\r
+gSmmCr0     DD      ?\r
+    mov     cr0, rax                    ; enable protected mode & paging\r
+    DB      66h, 0eah                   ; far jmp to long mode\r
+gSmmJmpAddr DQ      @LongMode\r
+@LongMode:                              ; long-mode starts here\r
+    DB      48h, 0bch                   ; mov rsp, imm64\r
+gSmmInitStack   DQ      ?\r
+    and     sp, 0fff0h                  ; make sure RSP is 16-byte aligned\r
+    ;\r
+    ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save\r
+    ; them before calling C-function.\r
+    ;\r
+    sub     rsp, 60h\r
+    movdqa  [rsp], xmm0\r
+    movdqa  [rsp + 10h], xmm1\r
+    movdqa  [rsp + 20h], xmm2\r
+    movdqa  [rsp + 30h], xmm3\r
+    movdqa  [rsp + 40h], xmm4\r
+    movdqa  [rsp + 50h], xmm5\r
+\r
+    add     rsp, -20h\r
+    call    SmmInitHandler\r
+    add     rsp, 20h\r
+\r
+    ;\r
+    ; Restore XMM0~5 after calling C-function.\r
+    ;\r
+    movdqa  xmm0, [rsp]\r
+    movdqa  xmm1, [rsp + 10h]\r
+    movdqa  xmm2, [rsp + 20h]\r
+    movdqa  xmm3, [rsp + 30h]\r
+    movdqa  xmm4, [rsp + 40h]\r
+    movdqa  xmm5, [rsp + 50h]\r
+\r
+    rsm\r
+SmmStartup  ENDP\r
+\r
+gcSmmInitTemplate   LABEL   BYTE\r
+\r
+_SmmInitTemplate    PROC\r
+    DB      66h, 2eh, 8bh, 2eh          ; mov ebp, cs:[@F]\r
+    DW      @L1 - _SmmInitTemplate + 8000h\r
+    DB      66h, 81h, 0edh, 00h, 00h, 03h, 00  ; sub ebp, 30000h\r
+    jmp     bp                          ; jmp ebp actually\r
+@L1:\r
+    DQ      SmmStartup\r
+_SmmInitTemplate    ENDP\r
+\r
+gcSmmInitSize   DW  $ - gcSmmInitTemplate\r
+\r
+SmmRelocationSemaphoreComplete PROC\r
+    push    rax\r
+    mov     rax, mRebasedFlag\r
+    mov     byte ptr [rax], 1\r
+    pop     rax\r
+    jmp     [mSmmRelocationOriginalAddress]\r
+SmmRelocationSemaphoreComplete ENDP\r
+\r
+;\r
+; Semaphore code running in 32-bit mode\r
+;\r
+SmmRelocationSemaphoreComplete32 PROC\r
+    ;\r
+    ; mov byte ptr [], 1\r
+    ;\r
+    db      0c6h, 05h\r
+mRebasedFlagAddr32    dd      0\r
+    db      1\r
+    ;\r
+    ; jmp dword ptr []\r
+    ;\r
+    db      0ffh, 25h\r
+mSmmRelocationOriginalAddressPtr32    dd      0\r
+SmmRelocationSemaphoreComplete32 ENDP\r
+\r
+    END\r