UefiCpuPkg/PiSmmCpuDxeSmm: eliminate "gSmmJmpAddr" and related DBs

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index b147e72180191afae903c082f5a50b59822e41d1..2460e1eb2dee91d2e0388ffe32044d7ebad0b471 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -22,10 +22,9 @@ extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)\r
 extern ASM_PFX(mSmmRelocationOriginalAddress)\r
 \r
-global ASM_PFX(gSmmCr3)\r
-global ASM_PFX(gSmmCr4)\r
-global ASM_PFX(gSmmCr0)\r
-global ASM_PFX(gSmmJmpAddr)\r
+global ASM_PFX(gPatchSmmCr3)\r
+global ASM_PFX(gPatchSmmCr4)\r
+global ASM_PFX(gPatchSmmCr0)\r
 global ASM_PFX(gSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r
 global ASM_PFX(gcSmmInitSize)\r
@@ -33,6 +32,8 @@ global ASM_PFX(gcSmmInitTemplate)
 global ASM_PFX(mRebasedFlagAddr32)\r
 global ASM_PFX(mSmmRelocationOriginalAddressPtr32)\r
 \r
+%define LONG_MODE_CS 0x38\r
+\r
     DEFAULT REL\r
     SECTION .text\r
 \r
@@ -41,36 +42,35 @@ ASM_PFX(gcSmiInitGdtr):
             DQ      0\r
 \r
 global ASM_PFX(SmmStartup)\r
+\r
+BITS 16\r
 ASM_PFX(SmmStartup):\r
-    DB      0x66\r
     mov     eax, 0x80000001             ; read capability\r
     cpuid\r
-    DB      0x66\r
     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.\r
-    DB      0x66, 0xb8                   ; mov eax, imm32\r
-ASM_PFX(gSmmCr3): DD 0\r
-    mov     cr3, rax\r
-    DB      0x66, 0x2e\r
-    lgdt    [ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
-    DB      0x66, 0xb8                   ; mov eax, imm32\r
-ASM_PFX(gSmmCr4): DD 0\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr3):\r
+    mov     cr3, eax\r
+o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr4):\r
     or      ah,  2                      ; enable XMM registers access\r
-    mov     cr4, rax\r
-    DB      0x66\r
+    mov     cr4, eax\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
     rdmsr\r
     or      ah, BIT0                    ; set LME bit\r
-    DB      0x66\r
     test    ebx, BIT20                  ; check NXE capability\r
     jz      .1\r
     or      ah, BIT3                    ; set NXE bit\r
 .1:\r
     wrmsr\r
-    DB      0x66, 0xb8                   ; mov eax, imm32\r
-ASM_PFX(gSmmCr0): DD 0\r
-    mov     cr0, rax                    ; enable protected mode & paging\r
-    DB      0x66, 0xea                   ; far jmp to long mode\r
-ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr0):\r
+    mov     cr0, eax                    ; enable protected mode & paging\r
+    jmp     LONG_MODE_CS : dword 0      ; offset will be patched to @LongMode\r
+@PatchLongModeOffset:\r
+\r
+BITS 64\r
 @LongMode:                              ; long-mode starts here\r
     DB      0x48, 0xbc                   ; mov rsp, imm64\r
 ASM_PFX(gSmmInitStack): DQ 0\r
@@ -142,8 +142,8 @@ ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
 ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
     lea    rax, [@LongMode]\r
-    lea    rcx, [ASM_PFX(gSmmJmpAddr)]\r
-    mov    qword [rcx], rax\r
+    lea    rcx, [@PatchLongModeOffset - 6]\r
+    mov    dword [rcx], eax\r
 \r
     lea    rax, [ASM_PFX(SmmStartup)]\r
     lea    rcx, [@L1]\r