UefiCpuPkg/PiSmmCpuDxeSmm: Enable NXE if it's supported

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 2701689c3de4afa75fbac1a107a557bc974d7339..b147e72180191afae903c082f5a50b59822e41d1 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -42,6 +42,11 @@ ASM_PFX(gcSmiInitGdtr):
 \r
 global ASM_PFX(SmmStartup)\r
 ASM_PFX(SmmStartup):\r
+    DB      0x66\r
+    mov     eax, 0x80000001             ; read capability\r
+    cpuid\r
+    DB      0x66\r
+    mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.\r
     DB      0x66, 0xb8                   ; mov eax, imm32\r
 ASM_PFX(gSmmCr3): DD 0\r
     mov     cr3, rax\r
@@ -54,7 +59,12 @@ ASM_PFX(gSmmCr4): DD 0
     DB      0x66\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
     rdmsr\r
-    or      ah, 1                       ; set LME bit\r
+    or      ah, BIT0                    ; set LME bit\r
+    DB      0x66\r
+    test    ebx, BIT20                  ; check NXE capability\r
+    jz      .1\r
+    or      ah, BIT3                    ; set NXE bit\r
+.1:\r
     wrmsr\r
     DB      0x66, 0xb8                   ; mov eax, imm32\r
 ASM_PFX(gSmmCr0): DD 0\r