Revert "UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports"

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmProfileArch.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
index 63bae5a9137cbbff9cf2617b1f5825429a6eb141..e7c78d36fc5fa8f0d345a9eab7695a8eea620baa 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
@@ -1,7 +1,7 @@
 /** @file\r
 X64 processor specific functions to enable SMM profile.\r
 \r
-Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
@@ -147,14 +147,9 @@ RestorePageTableAbove4G (
   BOOLEAN       Existed;\r
   UINTN         Index;\r
   UINTN         PFIndex;\r
-  IA32_CR4      Cr4;\r
-  BOOLEAN       Enable5LevelPaging;\r
 \r
   ASSERT ((PageTable != NULL) && (IsValidPFAddress != NULL));\r
 \r
-  Cr4.UintN = AsmReadCr4 ();\r
-  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
-\r
   //\r
   // If page fault address is 4GB above.\r
   //\r
@@ -166,48 +161,38 @@ RestorePageTableAbove4G (
   //\r
   Existed = FALSE;\r
   PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);\r
-  PTIndex = 0;\r
-  if (Enable5LevelPaging) {\r
-    PTIndex = BitFieldRead64 (PFAddress, 48, 56);\r
-  }\r
-  if ((!Enable5LevelPaging) || ((PageTable[PTIndex] & IA32_PG_P) != 0)) {\r
-    // PML5E\r
-    if (Enable5LevelPaging) {\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-    }\r
-    PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
+  PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
+  if ((PageTable[PTIndex] & IA32_PG_P) != 0) {\r
+    // PML4E\r
+    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+    PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
     if ((PageTable[PTIndex] & IA32_PG_P) != 0) {\r
-      // PML4E\r
+      // PDPTE\r
       PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-      PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
-      if ((PageTable[PTIndex] & IA32_PG_P) != 0) {\r
-        // PDPTE\r
-        PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-        PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
-        // PD\r
-        if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {\r
+      PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
+      // PD\r
+      if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {\r
+        //\r
+        // 2MB page\r
+        //\r
+        Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+        if ((Address & ~((1ull << 21) - 1)) == ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) {\r
+          Existed = TRUE;\r
+        }\r
+      } else {\r
+        //\r
+        // 4KB page\r
+        //\r
+        PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);\r
+        if (PageTable != 0) {\r
           //\r
-          // 2MB page\r
+          // When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.\r
           //\r
+          PTIndex = BitFieldRead64 (PFAddress, 12, 20);\r
           Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-          if ((Address & ~((1ull << 21) - 1)) == ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) {\r
+          if ((Address & ~((1ull << 12) - 1)) == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {\r
             Existed = TRUE;\r
           }\r
-        } else {\r
-          //\r
-          // 4KB page\r
-          //\r
-          PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);\r
-          if (PageTable != 0) {\r
-            //\r
-            // When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.\r
-            //\r
-            PTIndex = BitFieldRead64 (PFAddress, 12, 20);\r
-            Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-            if ((Address & ~((1ull << 12) - 1)) == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {\r
-              Existed = TRUE;\r
-            }\r
-          }\r
         }\r
       }\r
     }\r
@@ -236,11 +221,6 @@ RestorePageTableAbove4G (
     //\r
     PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);\r
     PFAddress = AsmReadCr2 ();\r
-    // PML5E\r
-    if (Enable5LevelPaging) {\r
-      PTIndex = BitFieldRead64 (PFAddress, 48, 56);\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-    }\r
     // PML4E\r
     PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r