UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmProfileArch.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
index c4ec12debb1c444555564dde20b63ab077afa54b..37da5fb78dbc38575e44d2bebed5b27f814c3b62 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
@@ -1,7 +1,9 @@
 /** @file\r
 X64 processor specific functions to enable SMM profile.\r
 \r
-Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -45,13 +47,14 @@ InitSmmS3Cr3 (
   //\r
   // Generate PAE page table for the first 4GB memory space\r
   //\r
-  Pages = Gen4GPageTable (1);\r
+  Pages = Gen4GPageTable (FALSE);\r
 \r
   //\r
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
-  PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));\r
-  *PTEntry = Pages + IA32_PG_P;\r
+  PTEntry = (UINT64*)AllocatePageTableMemory (1);\r
+  ASSERT (PTEntry != NULL);\r
+  *PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
 \r
   //\r
@@ -78,7 +81,7 @@ InitPagesForPFHandler (
   //\r
   Address = NULL;\r
   Address = AllocatePages (MAX_PF_PAGE_COUNT);\r
-  ASSERT_EFI_ERROR (Address != NULL);\r
+  ASSERT (Address != NULL);\r
 \r
   mPFPageBuffer =  (UINT64)(UINTN) Address;\r
   mPFPageIndex = 0;\r
@@ -110,14 +113,14 @@ AcquirePage (
   //\r
   // Cut the previous uplink if it exists and wasn't overwritten\r
   //\r
-  if ((mPFPageUplink[mPFPageIndex] != NULL) && ((*mPFPageUplink[mPFPageIndex] & PHYSICAL_ADDRESS_MASK) == Address)) {\r
+  if ((mPFPageUplink[mPFPageIndex] != NULL) && ((*mPFPageUplink[mPFPageIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK) == Address)) {\r
     *mPFPageUplink[mPFPageIndex] = 0;\r
   }\r
 \r
   //\r
   // Link & Record the current uplink\r
   //\r
-  *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+  *Uplink = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
   mPFPageUplink[mPFPageIndex] = Uplink;\r
 \r
   mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;\r
@@ -167,33 +170,33 @@ RestorePageTableAbove4G (
   PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
   if ((PageTable[PTIndex] & IA32_PG_P) != 0) {\r
     // PML4E\r
-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
     if ((PageTable[PTIndex] & IA32_PG_P) != 0) {\r
       // PDPTE\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
       PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
       // PD\r
       if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {\r
         //\r
         // 2MB page\r
         //\r
-        Address = (UINT64)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
-        if ((Address & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)) == ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) {\r
+        Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+        if ((Address & ~((1ull << 21) - 1)) == ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) {\r
           Existed = TRUE;\r
         }\r
       } else {\r
         //\r
         // 4KB page\r
         //\r
-        PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+        PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);\r
         if (PageTable != 0) {\r
           //\r
           // When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.\r
           //\r
           PTIndex = BitFieldRead64 (PFAddress, 12, 20);\r
-          Address = (UINT64)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
-          if ((Address & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1)) == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {\r
+          Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+          if ((Address & ~((1ull << 12) - 1)) == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {\r
             Existed = TRUE;\r
           }\r
         }\r
@@ -226,13 +229,13 @@ RestorePageTableAbove4G (
     PFAddress = AsmReadCr2 ();\r
     // PML4E\r
     PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     // PDPTE\r
     PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     // PD\r
     PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
-    Address = PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK;\r
+    Address = PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK;\r
     //\r
     // Check if 2MB-page entry need be changed to 4KB-page entry.\r
     //\r
@@ -240,11 +243,11 @@ RestorePageTableAbove4G (
       AcquirePage (&PageTable[PTIndex]);\r
 \r
       // PTE\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
       for (Index = 0; Index < 512; Index++) {\r
-        PageTable[Index] = Address | IA32_PG_RW | IA32_PG_P;\r
+        PageTable[Index] = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
         if (!IsAddressValid (Address, &Nx)) {\r
-          PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+          PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
         }\r
         if (Nx && mXdSupported) {\r
           PageTable[Index] = PageTable[Index] | IA32_PG_NX;\r
@@ -262,7 +265,7 @@ RestorePageTableAbove4G (
         //\r
         // Patch to remove present flag and rw flag.\r
         //\r
-        PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+        PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
       }\r
       //\r
       // Set XD bit to 1\r
@@ -289,7 +292,7 @@ RestorePageTableAbove4G (
   //\r
   // Add present flag or clear XD flag to make page fault handler succeed.\r
   //\r
-  PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+  PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);\r
   if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
     //\r
     // If page fault is caused by instruction fetch, clear XD bit in the entry.\r