UefiCpuPkg VTF0 X64: Build page tables in NASM code

[mirror_edk2.git] / UefiCpuPkg / ResetVector / Vtf0 / X64 / PageTables.asm

diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
new file mode 100644 (file)
index 0000000..3d703c7
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
@@ -0,0 +1,78 @@
+;------------------------------------------------------------------------------\r
+; @file\r
+; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)\r
+;\r
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS    64\r
+\r
+%define ALIGN_TOP_TO_4K_FOR_PAGING\r
+\r
+%define PAGE_PRESENT            0x01\r
+%define PAGE_READ_WRITE         0x02\r
+%define PAGE_USER_SUPERVISOR    0x04\r
+%define PAGE_WRITE_THROUGH      0x08\r
+%define PAGE_CACHE_DISABLE     0x010\r
+%define PAGE_ACCESSED          0x020\r
+%define PAGE_DIRTY             0x040\r
+%define PAGE_PAT               0x080\r
+%define PAGE_GLOBAL           0x0100\r
+%define PAGE_2M_MBO            0x080\r
+%define PAGE_2M_PAT          0x01000\r
+\r
+%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \\r
+                          PAGE_ACCESSED + \\r
+                          PAGE_DIRTY + \\r
+                          PAGE_READ_WRITE + \\r
+                          PAGE_PRESENT)\r
+\r
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r
+                       PAGE_READ_WRITE + \\r
+                       PAGE_PRESENT)\r
+\r
+%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)\r
+%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))\r
+\r
+%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \\r
+                     PAGE_PDP_ATTR)\r
+%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)\r
+\r
+TopLevelPageDirectory:\r
+\r
+    ;\r
+    ; Top level Page Directory Pointers (1 * 512GB entry)\r
+    ;\r
+    DQ      PDP(0x1000)\r
+\r
+\r
+    ;\r
+    ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r
+    ;\r
+    TIMES 0x1000-PGTBLS_OFFSET($) DB 0\r
+\r
+    DQ      PDP(0x2000)\r
+    DQ      PDP(0x3000)\r
+    DQ      PDP(0x4000)\r
+    DQ      PDP(0x5000)\r
+\r
+    ;\r
+    ; Page Table Entries (2048 * 2MB entries => 4GB)\r
+    ;\r
+    TIMES 0x2000-PGTBLS_OFFSET($) DB 0\r
+\r
+%assign i 0\r
+%rep    0x800\r
+    DQ      PTE_2MB(i)\r
+    %assign i i+1\r
+%endrep\r
+\r
+EndOfPageTables:\r