/** @file\r
C functions in SEC\r
\r
- Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "SecMain.h"\r
\r
-EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = {\r
+EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = {\r
SecTemporaryRamDone\r
};\r
\r
EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformationPpi = { SecPlatformInformation };\r
\r
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {\r
+EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {\r
+ {\r
+ //\r
+ // SecPerformance PPI notify descriptor.\r
+ //\r
+ EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
+ &gPeiSecPerformancePpiGuid,\r
+ (VOID *)(UINTN)SecPerformancePpiCallBack\r
+ },\r
{\r
EFI_PEI_PPI_DESCRIPTOR_PPI,\r
&gEfiTemporaryRamDonePpiGuid,\r
}\r
};\r
\r
+/**\r
+ Migrates the Global Descriptor Table (GDT) to permanent memory.\r
+\r
+ @retval EFI_SUCCESS The GDT was migrated successfully.\r
+ @retval EFI_OUT_OF_RESOURCES The GDT could not be migrated due to lack of available memory.\r
+\r
+**/\r
+EFI_STATUS\r
+MigrateGdt (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN GdtBufferSize;\r
+ IA32_DESCRIPTOR Gdtr;\r
+ VOID *GdtBuffer;\r
+\r
+ AsmReadGdtr ((IA32_DESCRIPTOR *)&Gdtr);\r
+ GdtBufferSize = sizeof (IA32_SEGMENT_DESCRIPTOR) -1 + Gdtr.Limit + 1;\r
+\r
+ Status = PeiServicesAllocatePool (\r
+ GdtBufferSize,\r
+ &GdtBuffer\r
+ );\r
+ ASSERT (GdtBuffer != NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ GdtBuffer = ALIGN_POINTER (GdtBuffer, sizeof (IA32_SEGMENT_DESCRIPTOR));\r
+ CopyMem (GdtBuffer, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
+ Gdtr.Base = (UINTN)GdtBuffer;\r
+ AsmWriteGdtr (&Gdtr);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
//\r
// These are IDT entries pointing to 10:FFFFFFE4h.\r
//\r
VOID\r
NORETURN\r
EFIAPI\r
-SecStartupPhase2(\r
- IN VOID *Context\r
+SecStartupPhase2 (\r
+ IN VOID *Context\r
);\r
\r
+/**\r
+ Entry point of the notification callback function itself within the PEIM.\r
+ It is to get SEC performance data and build HOB to convey the SEC performance\r
+ data to DXE phase.\r
+\r
+ @param PeiServices Indirect reference to the PEI Services Table.\r
+ @param NotifyDescriptor Address of the notification descriptor data structure.\r
+ @param Ppi Address of the PPI that was installed.\r
+\r
+ @return Status of the notification.\r
+ The status code returned from this function is ignored.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecPerformancePpiCallBack (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
+ IN VOID *Ppi\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ PEI_SEC_PERFORMANCE_PPI *SecPerf;\r
+ FIRMWARE_SEC_PERFORMANCE Performance;\r
+\r
+ SecPerf = (PEI_SEC_PERFORMANCE_PPI *)Ppi;\r
+ Status = SecPerf->GetPerformance ((CONST EFI_PEI_SERVICES **)PeiServices, SecPerf, &Performance);\r
+ if (!EFI_ERROR (Status)) {\r
+ BuildGuidDataHob (\r
+ &gEfiFirmwarePerformanceGuid,\r
+ &Performance,\r
+ sizeof (FIRMWARE_SEC_PERFORMANCE)\r
+ );\r
+ DEBUG ((DEBUG_INFO, "FPDT: SEC Performance Hob ResetEnd = %ld\n", Performance.ResetEnd));\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
/**\r
\r
Entry point to the C language phase of SEC. After the SEC assembly\r
@param BootFirmwareVolume Base address of the Boot Firmware Volume.\r
**/\r
VOID\r
+NORETURN\r
EFIAPI\r
SecStartup (\r
- IN UINT32 SizeOfRam,\r
- IN UINT32 TempRamBase,\r
- IN VOID *BootFirmwareVolume\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume\r
)\r
{\r
- EFI_SEC_PEI_HAND_OFF SecCoreData;\r
- IA32_DESCRIPTOR IdtDescriptor;\r
- SEC_IDT_TABLE IdtTableInStack;\r
- UINT32 Index;\r
- UINT32 PeiStackSize;\r
- EFI_STATUS Status;\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ IA32_DESCRIPTOR IdtDescriptor;\r
+ SEC_IDT_TABLE IdtTableInStack;\r
+ UINT32 Index;\r
+ UINT32 PeiStackSize;\r
+ EFI_STATUS Status;\r
\r
//\r
// Report Status Code to indicate entering SEC core\r
EFI_SOFTWARE_SEC | EFI_SW_SEC_PC_ENTRY_POINT\r
);\r
\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a() TempRAM Base: 0x%x, TempRAM Size: 0x%x, BootFirmwareVolume 0x%x\n",\r
+ __FUNCTION__,\r
+ TempRamBase,\r
+ SizeOfRam,\r
+ BootFirmwareVolume\r
+ ));\r
+\r
PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);\r
if (PeiStackSize == 0) {\r
PeiStackSize = (SizeOfRam >> 1);\r
// |-------------------|----> TempRamBase\r
\r
IdtTableInStack.PeiService = 0;\r
- for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {\r
- CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));\r
+ for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index++) {\r
+ ZeroMem ((VOID *)&IdtTableInStack.IdtTable[Index], sizeof (IA32_IDT_GATE_DESCRIPTOR));\r
+ CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&mIdtEntryTemplate, sizeof (UINT64));\r
}\r
\r
- IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;\r
+ IdtDescriptor.Base = (UINTN)&IdtTableInStack.IdtTable;\r
IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);\r
\r
AsmWriteIdtr (&IdtDescriptor);\r
//\r
// Update the base address and length of Pei temporary memory\r
//\r
- SecCoreData.DataSize = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.DataSize = (UINT16)sizeof (EFI_SEC_PEI_HAND_OFF);\r
SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;\r
- SecCoreData.BootFirmwareVolumeSize = (UINTN)(0x100000000ULL - (UINTN) BootFirmwareVolume);\r
- SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;\r
+ SecCoreData.BootFirmwareVolumeSize = (UINTN)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength;\r
+ SecCoreData.TemporaryRamBase = (VOID *)(UINTN)TempRamBase;\r
SecCoreData.TemporaryRamSize = SizeOfRam;\r
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
SecCoreData.PeiTemporaryRamSize = SizeOfRam - PeiStackSize;\r
- SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
+ SecCoreData.StackBase = (VOID *)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
SecCoreData.StackSize = PeiStackSize;\r
\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a() BFV Base: 0x%x, BFV Size: 0x%x, TempRAM Base: 0x%x, TempRAM Size: 0x%x, PeiTempRamBase: 0x%x, PeiTempRamSize: 0x%x, StackBase: 0x%x, StackSize: 0x%x\n",\r
+ __FUNCTION__,\r
+ SecCoreData.BootFirmwareVolumeBase,\r
+ SecCoreData.BootFirmwareVolumeSize,\r
+ SecCoreData.TemporaryRamBase,\r
+ SecCoreData.TemporaryRamSize,\r
+ SecCoreData.PeiTemporaryRamBase,\r
+ SecCoreData.PeiTemporaryRamSize,\r
+ SecCoreData.StackBase,\r
+ SecCoreData.StackSize\r
+ ));\r
+\r
//\r
// Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.\r
//\r
InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);\r
+\r
+ //\r
+ // Should not come here.\r
+ //\r
+ UNREACHABLE ();\r
}\r
\r
/**\r
VOID\r
NORETURN\r
EFIAPI\r
-SecStartupPhase2(\r
- IN VOID *Context\r
+SecStartupPhase2 (\r
+ IN VOID *Context\r
)\r
{\r
- EFI_SEC_PEI_HAND_OFF *SecCoreData;\r
- EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
- UINT32 Index;\r
- EFI_PEI_PPI_DESCRIPTOR *AllSecPpiList;\r
- EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;\r
+ EFI_SEC_PEI_HAND_OFF *SecCoreData;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ UINT32 Index;\r
+ EFI_PEI_PPI_DESCRIPTOR *AllSecPpiList;\r
+ EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;\r
+\r
+ PeiCoreEntryPoint = NULL;\r
+ SecCoreData = (EFI_SEC_PEI_HAND_OFF *)Context;\r
\r
- SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context;\r
- AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *) SecCoreData->PeiTemporaryRamBase;\r
+ //\r
+ // Perform platform specific initialization before entering PeiCore.\r
+ //\r
+ PpiList = SecPlatformMain (SecCoreData);\r
//\r
// Find Pei Core entry point. It will report SEC and Pei Core debug information if remote debug\r
// is enabled.\r
//\r
- FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);\r
- if (PeiCoreEntryPoint == NULL)\r
- {\r
- CpuDeadLoop ();\r
+ if (PpiList != NULL) {\r
+ Index = 0;\r
+ do {\r
+ if (CompareGuid (PpiList[Index].Guid, &gEfiPeiCoreFvLocationPpiGuid) &&\r
+ (((EFI_PEI_CORE_FV_LOCATION_PPI *)PpiList[Index].Ppi)->PeiCoreFvLocation != 0)\r
+ )\r
+ {\r
+ //\r
+ // In this case, SecCore is in BFV but PeiCore is in another FV reported by PPI.\r
+ //\r
+ FindAndReportEntryPoints (\r
+ (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase,\r
+ (EFI_FIRMWARE_VOLUME_HEADER *)((EFI_PEI_CORE_FV_LOCATION_PPI *)PpiList[Index].Ppi)->PeiCoreFvLocation,\r
+ &PeiCoreEntryPoint\r
+ );\r
+ if (PeiCoreEntryPoint != NULL) {\r
+ break;\r
+ } else {\r
+ //\r
+ // Invalid PeiCore FV provided by platform\r
+ //\r
+ CpuDeadLoop ();\r
+ }\r
+ }\r
+ } while ((PpiList[Index++].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
}\r
\r
//\r
- // Perform platform specific initialization before entering PeiCore.\r
+ // If EFI_PEI_CORE_FV_LOCATION_PPI not found, try to locate PeiCore from BFV.\r
//\r
- PpiList = SecPlatformMain (SecCoreData);\r
+ if (PeiCoreEntryPoint == NULL) {\r
+ //\r
+ // Both SecCore and PeiCore are in BFV.\r
+ //\r
+ FindAndReportEntryPoints (\r
+ (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase,\r
+ (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase,\r
+ &PeiCoreEntryPoint\r
+ );\r
+ if (PeiCoreEntryPoint == NULL) {\r
+ CpuDeadLoop ();\r
+ }\r
+ }\r
+\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a() PeiCoreEntryPoint: 0x%x\n",\r
+ __FUNCTION__,\r
+ PeiCoreEntryPoint\r
+ ));\r
+\r
if (PpiList != NULL) {\r
+ AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *)SecCoreData->PeiTemporaryRamBase;\r
+\r
//\r
// Remove the terminal flag from the terminal PPI\r
//\r
CopyMem (AllSecPpiList, mPeiSecPlatformInformationPpi, sizeof (mPeiSecPlatformInformationPpi));\r
- Index = sizeof (mPeiSecPlatformInformationPpi) / sizeof (EFI_PEI_PPI_DESCRIPTOR) - 1;\r
+ Index = sizeof (mPeiSecPlatformInformationPpi) / sizeof (EFI_PEI_PPI_DESCRIPTOR) - 1;\r
AllSecPpiList[Index].Flags = AllSecPpiList[Index].Flags & (~EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
\r
//\r
//\r
// Add the terminal PPI\r
//\r
- CopyMem (&AllSecPpiList[Index ++], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+ CopyMem (&AllSecPpiList[Index++], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
\r
//\r
// Set PpiList to the total PPI\r
// Adjust PEI TEMP RAM Range.\r
//\r
ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
- SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+ SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR);\r
//\r
// Adjust the Base and Size to be 8-byte aligned as HOB which has 8byte aligned requirement\r
// will be built based on them in PEI phase.\r
//\r
- SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
- SecCoreData->PeiTemporaryRamSize &= ~0x07;\r
+ SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
+ SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a() PeiTemporaryRamBase: 0x%x, PeiTemporaryRamSize: 0x%x\n",\r
+ __FUNCTION__,\r
+ SecCoreData->PeiTemporaryRamBase,\r
+ SecCoreData->PeiTemporaryRamSize\r
+ ));\r
} else {\r
//\r
// No addition PPI, PpiList directly point to the common PPI list.\r
"%a() Stack Base: 0x%p, Stack Size: 0x%x\n",\r
__FUNCTION__,\r
SecCoreData->StackBase,\r
- (UINT32) SecCoreData->StackSize\r
+ (UINT32)SecCoreData->StackSize\r
));\r
\r
//\r
// Transfer the control to the PEI core\r
//\r
ASSERT (PeiCoreEntryPoint != NULL);\r
- (*PeiCoreEntryPoint) (SecCoreData, PpiList);\r
+ (*PeiCoreEntryPoint)(SecCoreData, PpiList);\r
\r
//\r
// Should not come here.\r
VOID\r
)\r
{\r
- BOOLEAN State;\r
+ EFI_STATUS Status;\r
+ EFI_STATUS Status2;\r
+ UINTN Index;\r
+ BOOLEAN State;\r
+ EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor;\r
+ REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi;\r
\r
//\r
// Republish Sec Platform Information(2) PPI\r
//\r
RepublishSecPlatformInformationPpi ();\r
\r
+ //\r
+ // Re-install SEC PPIs using a PEIM produced service if published\r
+ //\r
+ for (Index = 0, Status = EFI_SUCCESS; Status == EFI_SUCCESS; Index++) {\r
+ Status = PeiServicesLocatePpi (\r
+ &gRepublishSecPpiPpiGuid,\r
+ Index,\r
+ &PeiPpiDescriptor,\r
+ (VOID **)&RepublishSecPpiPpi\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_INFO, "Calling RepublishSecPpi instance %d.\n", Index));\r
+ Status2 = RepublishSecPpiPpi->RepublishSecPpis ();\r
+ ASSERT_EFI_ERROR (Status2);\r
+ }\r
+ }\r
+\r
//\r
// Migrate DebugAgentContext.\r
//\r
//\r
// Disable interrupts and save current interrupt state\r
//\r
- State = SaveAndDisableInterrupts();\r
+ State = SaveAndDisableInterrupts ();\r
+\r
+ //\r
+ // Migrate GDT before NEM near down\r
+ //\r
+ if (PcdGetBool (PcdMigrateTemporaryRamFirmwareVolumes)) {\r
+ Status = MigrateGdt ();\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
\r
//\r
// Disable Temporary RAM after Stack and Heap have been migrated at this point.\r
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