# 0x80000001 | Invalid value provided.\r
#\r
\r
+[Ppis]\r
+ gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r
+\r
[PcdsFeatureFlag]\r
## Indicates if SMM Profile will be enabled.\r
# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
- # It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).\r
+ # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.\r
+ # In IA32 build, the page table memory is not marked as read-only when it is enabled.\r
# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
# TRUE - SMM Profile will be enabled.<BR>\r
# FALSE - SMM Profile will be disabled.<BR>\r
# @Prompt If CPU features will be initialized during S3 resume.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
\r
+ ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r
+ # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r
+ # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r
+ # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r
+ # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r
+ # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
## Specifies max supported number of Logical Processors.\r
# @Prompt Configure max supported number of Logical Processors\r
# @Prompt The specified AP target C-state for Mwait.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
\r
- ## Indicates if SMM uses static page table.\r
- # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\r
- # This flag only impacts X64 build, because SMM always builds static page table for IA32.\r
- # It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
- # It could not be enabled also at the same time with heap guard feature for SMM\r
- # (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\r
- # TRUE - SMM uses static page table for all memory.<BR>\r
- # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
- # @Prompt Use static page table for all memory in SMM.\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r
-\r
## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
# @Prompt AP synchronization timeout value in SMM.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
# @Prompt Current boot is a power-on reset.\r
gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
\r
+[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r
+ ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
+ # MMIO access is always allowed regardless of the value of this PCD.\r
+ # Loose of such restriction is only required by RAS components in X64 platforms.\r
+ # The PCD value is considered as constantly TRUE in IA32 platforms.\r
+ # When the PCD value is TRUE, page table is initialized to cover all memory spaces\r
+ # and the memory occupied by page table is protected by page table itself as read-only.\r
+ # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
+ # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM\r
+ # (PcdHeapGuardPropertyMask in MdeModulePkg).\r
+ # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)\r
+ # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.\r
+ # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r
+ # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r
+ # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r
+\r
[PcdsDynamic, PcdsDynamicEx]\r
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
# @Prompt The pointer to a CPU S3 data buffer.\r