UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 762badf5d2396f938438c6cbcdf3d4c3d7ba1339..2115aa4387a2cced9a8194673175c8382ea67746 100644 (file)
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -1,7 +1,7 @@
 ## @file  UefiCpuPkg.dec\r
 # This Package provides UEFI compatible CPU modules and libraries.\r
 #\r
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.<BR>\r
 #\r
 # SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
@@ -53,6 +53,18 @@
   ##\r
   MpInitLib|Include/Library/MpInitLib.h\r
 \r
+  ##  @libraryclass  Provides function to support CcExit processing.\r
+  CcExitLib|Include/Library/CcExitLib.h\r
+\r
+  ##  @libraryclass  Provides function to get CPU cache information.\r
+  CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h\r
+\r
+  ##  @libraryclass  Provides function for loading microcode.\r
+  MicrocodeLib|Include/Library/MicrocodeLib.h\r
+\r
+  ##  @libraryclass  Provides function for manipulating x86 paging structures.\r
+  CpuPageTableLib|Include/Library/CpuPageTableLib.h\r
+\r
 [Guids]\r
   gUefiCpuPkgTokenSpaceGuid      = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
   gMsegSmramGuid                 = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
@@ -66,13 +78,24 @@
   ## Include/Guid/MicrocodePatchHob.h\r
   gEdkiiMicrocodePatchHobGuid    = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}\r
 \r
+  ## Include/Guid/SmmBaseHob.h\r
+  gSmmBaseHobGuid      = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }}\r
+\r
 [Protocols]\r
   ## Include/Protocol/SmmCpuService.h\r
-  gEfiSmmCpuServiceProtocolGuid  = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
+  gEfiSmmCpuServiceProtocolGuid   = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
+  gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}\r
 \r
   ## Include/Protocol/SmMonitorInit.h\r
   gEfiSmMonitorInitProtocolGuid  = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r
 \r
+[Protocols.RISCV64]\r
+  #\r
+  # Protocols defined for RISC-V systems\r
+  #\r
+  ## Include/Protocol/RiscVBootProtocol.h\r
+  gRiscVEfiBootProtocolGuid  = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}\r
+\r
 #\r
 # [Error.gUefiCpuPkgTokenSpaceGuid]\r
 #   0x80000001 | Invalid value provided.\r
@@ -84,6 +107,9 @@
   ## Include/Ppi/ShadowMicrocode.h\r
   gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}\r
 \r
+  ## Include/Ppi/RepublishSecPpi.h\r
+  gRepublishSecPpiPpiGuid   = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}\r
+\r
 [PcdsFeatureFlag]\r
   ## Indicates if SMM Profile will be enabled.\r
   #  If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
@@ -142,6 +168,18 @@
   # @Prompt Lock SMM Feature Control MSR.\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
 \r
+  ## Indicates if SMRR will be enabled.<BR><BR>\r
+  #   TRUE  - SMRR will be enabled.<BR>\r
+  #   FALSE - SMRR will not be enabled.<BR>\r
+  # @Prompt Enable SMRR.\r
+  gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|TRUE|BOOLEAN|0x3213210D\r
+\r
+  ## Indicates if SmmFeatureControl will be enabled.<BR><BR>\r
+  #   TRUE  - SmmFeatureControl will be enabled.<BR>\r
+  #   FALSE - SmmFeatureControl will not be enabled.<BR>\r
+  # @Prompt Support SmmFeatureControl.\r
+  gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|TRUE|BOOLEAN|0x32132110\r
+\r
 [PcdsFixedAtBuild]\r
   ## List of exception vectors which need switching stack.\r
   #  This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
@@ -158,6 +196,14 @@
   # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002\r
 \r
+  ## Area of memory where the SEV-ES work area block lives.\r
+  # @Prompt Configure the SEV-ES work area base\r
+  gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005\r
+\r
+  ## Size of teh area of memory where the SEV-ES work area block lives.\r
+  # @Prompt Configure the SEV-ES work area base\r
+  gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006\r
+\r
 [PcdsFixedAtBuild, PcdsPatchableInModule]\r
   ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
   # @Prompt Configure base address of CPU Local APIC\r
@@ -370,5 +416,16 @@
   # @ValidRange  0x80000001 | 0 - 1\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
 \r
+  ## This dynamic PCD indicates whether SEV-ES is enabled\r
+  #   TRUE  - SEV-ES is enabled\r
+  #   FALSE - SEV-ES is not enabled\r
+  # @Prompt SEV-ES Status\r
+  gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016\r
+\r
+  ## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR\r
+  #  features VMGEXIT defined in the version 2 of GHCB spec.\r
+  # @Prompt GHCB Hypervisor Features\r
+  gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018\r
+\r
 [UserExtensions.TianoCore."ExtraFiles"]\r
   UefiCpuPkgExtra.uni\r