ArmPkg: only attempt buildin MmCommunicationDxe for AArch64

[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 12f4413ea5b01ec4441f4c8fa893ec2fa58b1ab0..762badf5d2396f938438c6cbcdf3d4c3d7ba1339 100644 (file)
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -1,7 +1,7 @@
 ## @file  UefiCpuPkg.dec\r
 # This Package provides UEFI compatible CPU modules and libraries.\r
 #\r
-# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>\r
 #\r
 # SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
@@ -63,6 +63,9 @@
   ## Include/Guid/CpuFeaturesInitDone.h\r
   gEdkiiCpuFeaturesInitDoneGuid  = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
 \r
+  ## Include/Guid/MicrocodePatchHob.h\r
+  gEdkiiMicrocodePatchHobGuid    = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}\r
+\r
 [Protocols]\r
   ## Include/Protocol/SmmCpuService.h\r
   gEfiSmmCpuServiceProtocolGuid  = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
@@ -78,6 +81,9 @@
 [Ppis]\r
   gEdkiiPeiMpServices2PpiGuid =    { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r
 \r
+  ## Include/Ppi/ShadowMicrocode.h\r
+  gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}\r
+\r
 [PcdsFeatureFlag]\r
   ## Indicates if SMM Profile will be enabled.\r
   #  If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
@@ -148,6 +154,10 @@
   # @Prompt Specify size of good stack of exception which need switching stack.\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
 \r
+  ## Count of pre allocated SMM MP tokens per chunk.\r
+  # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002\r
+\r
 [PcdsFixedAtBuild, PcdsPatchableInModule]\r
   ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
   # @Prompt Configure base address of CPU Local APIC\r
@@ -220,6 +230,12 @@
   # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r
 \r
+  ## Specifies the periodic interval value in microseconds for the status check\r
+  #  of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking\r
+  #  mode in DXE phase.\r
+  # @Prompt Periodic interval value in microseconds for AP status check in DXE.\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E\r
+\r
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
   ## Specifies max supported number of Logical Processors.\r
   # @Prompt Configure max supported number of Logical Processors\r