UefiCpuPkg/PiSmmCpu: Restrict access per PcdCpuSmmRestrictedMemoryAccess

[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 14ddaa8633c62cf587a332f9278b59637054d9aa..83acd3361282ccfaf7703b02f890b57179218cd9 100644 (file)
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -211,6 +211,14 @@
   # @Prompt If CPU features will be initialized during S3 resume.\r
   gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
 \r
+  ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r
+  # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r
+  #   Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r
+  #   6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r
+  #   Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r
+  # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r
+\r
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
   ## Specifies max supported number of Logical Processors.\r
   # @Prompt Configure max supported number of Logical Processors\r
@@ -270,6 +278,18 @@
   # @Prompt Current boot is a power-on reset.\r
   gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
 \r
+[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r
+  ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
+  #  MMIO access is always allowed regardless of the value of this PCD.\r
+  #  Loose of such restriction is only required by RAS components in X64 platforms.\r
+  #  The PCD value is considered as constantly TRUE in IA32 platforms.\r
+  #  When the PCD value is TRUE, page table is initialized to cover all memory spaces\r
+  #  and the memory occupied by page table is protected by page table itself as read-only.\r
+  #   TRUE  - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r
+  #   FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r
+  # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r
+\r
 [PcdsDynamic, PcdsDynamicEx]\r
   ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
   # @Prompt The pointer to a CPU S3 data buffer.\r