//\r
// This Package provides UEFI compatible CPU modules and libraries.\r
//\r
-// Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>\r
//\r
-// This program and the accompanying materials are licensed and made available under\r
-// the terms and conditions of the BSD License which accompanies this distribution.\r
-// The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
//\r
// **/\r
\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApInitTimeOutInMicroSeconds_HELP #language en-US "Specifies timeout value in microseconds for the BSP to detect all APs for the first time."\r
\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuBootLogicalProcessorNumber_PROMPT #language en-US "Number of Logical Processors available after platform reset."\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuBootLogicalProcessorNumber_HELP #language en-US "Specifies the number of Logical Processors that are available in the preboot environment after platform reset, including BSP and APs."\r
+\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuMicrocodePatchAddress_PROMPT #language en-US "Microcode Region base address."\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuMicrocodePatchAddress_HELP #language en-US "Specifies the base address of the first microcode Patch in the microcode Region."\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmProfileEnable_PROMPT #language en-US "Enable SMM Profile"\r
\r
-#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmProfileEnable_HELP #language en-US "Indicates if SMM Profile will be enabled. If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged. This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\n"\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmProfileEnable_HELP #language en-US "Indicates if SMM Profile will be enabled.\n"\r
+ "If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\n"\r
+ "It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).\n"\r
+ "This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\n"\r
"TRUE - SMM Profile will be enabled.<BR>\n"\r
"FALSE - SMM Profile will be disabled.<BR>"\r
\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmStackSize_HELP #language en-US "Specifies stack size in bytes for each processor in SMM."\r
\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmShadowStackSize_PROMPT #language en-US "Processor shadow stack size in SMM."\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmShadowStackSize_HELP #language en-US "Specifies shadow stack size in bytes for each processor in SMM."\r
+\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmApSyncTimeout_PROMPT #language en-US "AP synchronization timeout value in SMM"\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmApSyncTimeout_HELP #language en-US "Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM."\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmStaticPageTable_PROMPT #language en-US "Use static page table for all memory in SMM."\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmStaticPageTable_HELP #language en-US "Indicates if SMM uses static page table.\n"\r
- "If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.<BR><BR>\n"\r
- "This flag only impacts X64 build, because SMM alway builds static page table for IA32.\n"\r
+ "If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\n"\r
+ "This flag only impacts X64 build, because SMM always builds static page table for IA32.\n"\r
+ "It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\n"\r
+ "It could not be enabled also at the same time with heap guard feature for SMM\n"\r
+ "(PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\n"\r
"TRUE - SMM uses static page table for all memory.<BR>\n"\r
"FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>"\r
\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdIsPowerOnReset_HELP #language en-US "Indicates if the current boot is a power-on reset."\r
\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmRestrictedMemoryAccess_PROMPT #language en-US "Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock."\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmRestrictedMemoryAccess_HELP #language en-US "Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR><BR>\n"\r
+ "MMIO access is always allowed regardless of the value of this PCD.<BR>\n"\r
+ "Loose of such restriction is only required by RAS components in X64 platforms.<BR>\n"\r
+ "The PCD value is considered as constantly TRUE in IA32 platforms.<BR>\n"\r
+ "When the PCD value is TRUE, page table is initialized to cover all memory spaces<BR>\n"\r
+ "and the memory occupied by page table is protected by page table itself as read-only.<BR>\n"\r
+ "In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).<BR>\n"\r
+ "In X64 build, it could not be enabled also at the same time with heap guard feature for SMM<BR>\n"\r
+ "(PcdHeapGuardPropertyMask in MdeModulePkg).<BR>\n"\r
+ "In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)<BR>\n"\r
+ "or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.<BR>\n"\r
+ "TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\n"\r
+ "FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>"\r
+\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesCapability_PROMPT #language en-US "Processor feature capabilities."\r
\r
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesCapability_HELP #language en-US "Indicates processor feature capabilities, each bit corresponding to a specific feature."\r
"Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\n"\r
"This PCD is ignored if CPU processor trace is disabled.<BR><BR>\n"\r
"Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\n"\r
- "0 - Single Range output scheme.<BR>\n"\r\r
- "1 - ToPA(Table of physical address) scheme.<BR>\n"\r
\ No newline at end of file
+ "0 - Single Range output scheme.<BR>\n"\r
+ "1 - ToPA(Table of physical address) scheme.<BR>\n"\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuStackSwitchExceptionList_PROMPT #language en-US "Specify exception vectors which need switching stack."\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuStackSwitchExceptionList_HELP #language en-US "List of exception vectors which need switching stack.\n"\r
+ "This PCD will only take into effect if PcdCpuStackGuard is enabled.n"\r
+ "By default exception #DD(8), #PF(14) are supported.n"\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuKnownGoodStackSize_PROMPT #language en-US "Specify size of good stack of exception which need switching stack."\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuKnownGoodStackSize_HELP #language en-US "Size of good stack for an exception.\n"\r
+ "This PCD will only take into effect if PcdCpuStackGuard is enabled.\n"\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuCoreCrystalClockFrequency_PROMPT #language en-US "Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency."\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuCoreCrystalClockFrequency_HELP #language en-US "Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.<BR><BR>\n"\r
+ "TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.<BR><BR>\n"\r
+ "This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX.<BR><BR>\n"\r
+ "Default value is 24000000 for 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family.<BR>\n"\r
+ "25000000 - Intel Xeon Processor Scalable Family with CPUID signature 06_55H(25MHz).<BR>\n"\r
+ "24000000 - 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family(24MHz).<BR>\n"\r
+ "19200000 - Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH(19.2MHz).<BR>\n"\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmMpTokenCountPerChunk_PROMPT #language en-US "Specify the count of pre allocated SMM MP tokens per chunk.\n"\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmMpTokenCountPerChunk_HELP #language en-US "This value used to specify the count of pre allocated SMM MP tokens per chunk.\n"\r
+\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApStatusCheckIntervalInMicroSeconds_PROMPT #language en-US "Periodic interval value in microseconds for AP status check in DXE.\n"\r
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApStatusCheckIntervalInMicroSeconds_HELP #language en-US "Periodic interval value in microseconds for the status check of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking mode in DXE phase.\n"\r
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