UefiPayloadPkg: UefiPayload retrieve PCI root bridge from Guid Hob

[mirror_edk2.git] / UefiPayloadPkg / Library / PciHostBridgeLib / PciHostBridgeSupport.c

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index fffbf04cad3fc746e1b9e2d9e1ad7cef23ad3a81..b0268f05069ce6b0bf3d39cccf185d6f00f2a739 100644 (file)
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -1,7 +1,7 @@
 /** @file\r
   Scan the entire PCI bus for root bridges to support coreboot UEFI payload.\r
 \r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -582,3 +582,74 @@ ScanForRootBridges (
 \r
   return RootBridges;\r
 }\r
+\r
+/**\r
+  Scan for all root bridges from Universal Payload PciRootBridgeInfoHob\r
+\r
+  @param[in]  PciRootBridgeInfo    Pointer of Universal Payload PCI Root Bridge Info Hob\r
+  @param[out] NumberOfRootBridges  Number of root bridges detected\r
+\r
+  @retval     Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r
+\r
+**/\r
+PCI_ROOT_BRIDGE *\r
+RetrieveRootBridgeInfoFromHob (\r
+  IN  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES  *PciRootBridgeInfo,\r
+  OUT UINTN                               *NumberOfRootBridges\r
+)\r
+{\r
+  PCI_ROOT_BRIDGE                *PciRootBridges;\r
+  UINTN                          Size;\r
+  UINT8                          Index;\r
+\r
+  ASSERT (PciRootBridgeInfo != NULL);\r
+  ASSERT (NumberOfRootBridges != NULL);\r
+  if (PciRootBridgeInfo == NULL) {\r
+    return NULL;\r
+  }\r
+  if (PciRootBridgeInfo->Count == 0) {\r
+    return NULL;\r
+  }\r
+  Size = PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);\r
+  PciRootBridges = (PCI_ROOT_BRIDGE *) AllocatePool (Size);\r
+  ASSERT (PciRootBridges != NULL);\r
+  if (PciRootBridges == NULL) {\r
+    return NULL;\r
+  }\r
+  ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE));\r
+\r
+  //\r
+  // Create all root bridges with PciRootBridgeInfoHob\r
+  //\r
+  for (Index = 0; Index < PciRootBridgeInfo->Count; Index++) {\r
+    PciRootBridges[Index].Segment               = PciRootBridgeInfo->RootBridge[Index].Segment;\r
+    PciRootBridges[Index].Supports              = PciRootBridgeInfo->RootBridge[Index].Supports;\r
+    PciRootBridges[Index].Attributes            = PciRootBridgeInfo->RootBridge[Index].Attributes;\r
+    PciRootBridges[Index].DmaAbove4G            = PciRootBridgeInfo->RootBridge[Index].DmaAbove4G;\r
+    PciRootBridges[Index].NoExtendedConfigSpace = PciRootBridgeInfo->RootBridge[Index].NoExtendedConfigSpace;\r
+    PciRootBridges[Index].ResourceAssigned      = PciRootBridgeInfo->ResourceAssigned;\r
+    PciRootBridges[Index].AllocationAttributes  = PciRootBridgeInfo->RootBridge[Index].AllocationAttributes;\r
+    PciRootBridges[Index].DevicePath            = CreateRootBridgeDevicePath(PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridge[Index].UID);\r
+    CopyMem(&PciRootBridges[Index].Bus,         &PciRootBridgeInfo->RootBridge[Index].Bus,         sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].Io,          &PciRootBridgeInfo->RootBridge[Index].Io,          sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].Mem,         &PciRootBridgeInfo->RootBridge[Index].Mem,         sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].MemAbove4G,  &PciRootBridgeInfo->RootBridge[Index].MemAbove4G,  sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].PMem,        &PciRootBridgeInfo->RootBridge[Index].PMem,        sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+    CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBridge[Index].PMemAbove4G, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));\r
+  }\r
+\r
+  *NumberOfRootBridges = PciRootBridgeInfo->Count;\r
+\r
+  //\r
+  // Now, this library only supports RootBridge that ResourceAssigned is True\r
+  //\r
+  if (PciRootBridgeInfo->ResourceAssigned) {\r
+    PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);\r
+  } else {\r
+    DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned is FALSE\n"));\r
+    PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE);\r
+    return NULL;\r
+  }\r
+\r
+  return PciRootBridges;\r
+}\r