+#define R_PCH_SPI_PR1 0x78 // Protected Region 1 Register\r
+#define B_PCH_SPI_PR1_WPE BIT31 // Write Protection Enable\r
+#define B_PCH_SPI_PR1_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]\r
+#define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable\r
+#define B_PCH_SPI_PR1_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]\r
+\r