]> git.proxmox.com Git - mirror_edk2.git/commit - MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
MdeModulePkg XhciDxe: Use common buffer for AsyncInterruptTransfer
authorStar Zeng <star.zeng@intel.com>
Thu, 25 Oct 2018 08:20:27 +0000 (16:20 +0800)
committerStar Zeng <star.zeng@intel.com>
Sun, 28 Oct 2018 13:20:08 +0000 (21:20 +0800)
commit777920997152a2e68f664241f6080b64ff21edd6
tree98b3da38fcdc859230b9485368a320cd51604bdd
parent4f792685e476dfd1e777033492207335ea804c9f
MdeModulePkg XhciDxe: Use common buffer for AsyncInterruptTransfer

V3:
Call XhcFreeUrb after XhcCreateTransferTrb fails in XhcCreateTrb.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1274

In current code, XhcMonitorAsyncRequests (timer handler) will do
unmap and map operations for AsyncIntTransfers to "Flush data from
PCI controller specific address to mapped system memory address".
XhcMonitorAsyncRequests
  XhcFlushAsyncIntMap
    PciIo->Unmap
      IoMmu->SetAttribute
    PciIo->Map
      IoMmu->SetAttribute

This may impact the boot performance.

Since the data buffer for XhcMonitorAsyncRequests is internal
buffer, we can allocate common buffer by PciIo->AllocateBuffer
and map the buffer with EfiPciIoOperationBusMasterCommonBuffer,
then the unmap and map operations can be removed.

///
/// Provides both read and write access to system memory by
/// both the processor and a bus master. The buffer is coherent
/// from both the processor's and the bus master's point of view.
///
EfiPciIoOperationBusMasterCommonBuffer,

Test done:
USB KB works normally.
USB disk read/write works normally.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h