UefiCpuPkg/MtrrLib: Fix a bug that may wrongly set memory <1MB to UC
authorRuiyu Ni <ruiyu.ni@intel.com>
Mon, 21 Jan 2019 15:16:22 +0000 (23:16 +0800)
committerRay Ni <ray.ni@intel.com>
Tue, 19 Feb 2019 09:14:34 +0000 (17:14 +0800)
commit13a47cf9251b11d07e25027dc13d3f4a0f5c17ed
tree79989274ad2c4765c9b7aab97556ad362fcf89b9
parenta083afa3fe9e6b7c93d41f775bf443fd2ac6cea8
UefiCpuPkg/MtrrLib: Fix a bug that may wrongly set memory <1MB to UC

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1481

Today's MtrrLib contains a bug, for example:
 when the original cache setting is WB for [0xF_0000, 0xF_8000) and,
 a new request to set [0xF_0000, 0xF_4000) to WP,
 the cache setting for [0xF_4000, 0xF_8000) is reset to UC.

The reason is when MtrrLibSetBelow1MBMemoryAttribute() is called the
WorkingFixedSettings doesn't contain the actual MSR value stored in
hardware, but when writing the fixed MTRRs, the code logic assumes
WorkingFixedSettings contains the actual MSR value.

The new fix is to change MtrrLibSetBelow1MBMemoryAttribute() to
calculate the correct ClearMasks[] and OrMasks[], and use them
directly when writing the fixed MTRRs.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
UefiCpuPkg/Library/MtrrLib/MtrrLib.c