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(parent: 13a0471) | patch
CpuPageTableLib: Split the page entry when LA is aligned but PA is not
authorRay Ni <ray.ni@intel.com>
Thu, 14 Jul 2022 12:08:29 +0000 (20:08 +0800)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Tue, 9 Aug 2022 07:08:05 +0000 (07:08 +0000)
commit9cb8974f06c6cc2545a66e696a58911122dec9fd
tree02e9da1e6de12737b5cd0862c31c716aa4cb90eatree
parent13a0471bfdcc1c7b18e182ca554d2ce98116e500commit | diff
CpuPageTableLib: Split the page entry when LA is aligned but PA is not

When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.

The patch fixes the bug.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c diff | blob | blame | history
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