]> git.proxmox.com Git - mirror_qemu.git/blame - dma-helpers.c
migration/postcopy: postpone setting PostcopyState to END
[mirror_qemu.git] / dma-helpers.c
CommitLineData
244ab90e
AL
1/*
2 * DMA helper functions
3 *
4 * Copyright (c) 2009 Red Hat
5 *
6 * This work is licensed under the terms of the GNU General Public License
7 * (GNU GPL), version 2 or later.
8 */
9
d38ea87a 10#include "qemu/osdep.h"
4be74634 11#include "sysemu/block-backend.h"
9c17d615 12#include "sysemu/dma.h"
0ab8ed18 13#include "trace-root.h"
1de7afc9 14#include "qemu/thread.h"
6a1751b7 15#include "qemu/main-loop.h"
244ab90e 16
e5332e63
DG
17/* #define DEBUG_IOMMU */
18
df32fd1c 19int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
d86a77f8 20{
df32fd1c 21 dma_barrier(as, DMA_DIRECTION_FROM_DEVICE);
24addbc7 22
d86a77f8
DG
23#define FILLBUF_SIZE 512
24 uint8_t fillbuf[FILLBUF_SIZE];
25 int l;
24addbc7 26 bool error = false;
d86a77f8
DG
27
28 memset(fillbuf, c, FILLBUF_SIZE);
29 while (len > 0) {
30 l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
5c9eb028
PM
31 error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
32 fillbuf, l, true);
bc9b78de
BH
33 len -= l;
34 addr += l;
d86a77f8 35 }
e5332e63 36
24addbc7 37 return error;
d86a77f8
DG
38}
39
f487b677
PB
40void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
41 AddressSpace *as)
244ab90e 42{
7267c094 43 qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
244ab90e
AL
44 qsg->nsg = 0;
45 qsg->nalloc = alloc_hint;
46 qsg->size = 0;
df32fd1c 47 qsg->as = as;
f487b677
PB
48 qsg->dev = dev;
49 object_ref(OBJECT(dev));
244ab90e
AL
50}
51
d3231181 52void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
244ab90e
AL
53{
54 if (qsg->nsg == qsg->nalloc) {
55 qsg->nalloc = 2 * qsg->nalloc + 1;
7267c094 56 qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
244ab90e
AL
57 }
58 qsg->sg[qsg->nsg].base = base;
59 qsg->sg[qsg->nsg].len = len;
60 qsg->size += len;
61 ++qsg->nsg;
62}
63
64void qemu_sglist_destroy(QEMUSGList *qsg)
65{
f487b677 66 object_unref(OBJECT(qsg->dev));
7267c094 67 g_free(qsg->sg);
ea8d82a1 68 memset(qsg, 0, sizeof(*qsg));
244ab90e
AL
69}
70
59a703eb 71typedef struct {
7c84b1b8 72 BlockAIOCB common;
8a8e63eb 73 AioContext *ctx;
7c84b1b8 74 BlockAIOCB *acb;
59a703eb 75 QEMUSGList *sg;
99868af3 76 uint32_t align;
d4f510eb 77 uint64_t offset;
43cf8ae6 78 DMADirection dir;
59a703eb 79 int sg_cur_index;
d3231181 80 dma_addr_t sg_cur_byte;
59a703eb
AL
81 QEMUIOVector iov;
82 QEMUBH *bh;
cb144ccb 83 DMAIOFunc *io_func;
8a8e63eb 84 void *io_func_opaque;
37b7842c 85} DMAAIOCB;
59a703eb 86
4be74634 87static void dma_blk_cb(void *opaque, int ret);
59a703eb
AL
88
89static void reschedule_dma(void *opaque)
90{
37b7842c 91 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
59a703eb 92
539343c0 93 assert(!dbs->acb && dbs->bh);
59a703eb
AL
94 qemu_bh_delete(dbs->bh);
95 dbs->bh = NULL;
4be74634 96 dma_blk_cb(dbs, 0);
59a703eb
AL
97}
98
4be74634 99static void dma_blk_unmap(DMAAIOCB *dbs)
59a703eb 100{
59a703eb
AL
101 int i;
102
59a703eb 103 for (i = 0; i < dbs->iov.niov; ++i) {
df32fd1c 104 dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base,
c65bcef3
DG
105 dbs->iov.iov[i].iov_len, dbs->dir,
106 dbs->iov.iov[i].iov_len);
59a703eb 107 }
c3adb5b9
PB
108 qemu_iovec_reset(&dbs->iov);
109}
110
111static void dma_complete(DMAAIOCB *dbs, int ret)
112{
c57c4658
KW
113 trace_dma_complete(dbs, ret, dbs->common.cb);
114
539343c0 115 assert(!dbs->acb && !dbs->bh);
4be74634 116 dma_blk_unmap(dbs);
c3adb5b9
PB
117 if (dbs->common.cb) {
118 dbs->common.cb(dbs->common.opaque, ret);
119 }
120 qemu_iovec_destroy(&dbs->iov);
8007429a 121 qemu_aio_unref(dbs);
7403b14e
AL
122}
123
4be74634 124static void dma_blk_cb(void *opaque, int ret)
7403b14e
AL
125{
126 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
c65bcef3 127 dma_addr_t cur_addr, cur_len;
7403b14e
AL
128 void *mem;
129
4be74634 130 trace_dma_blk_cb(dbs, ret);
c57c4658 131
7403b14e 132 dbs->acb = NULL;
d4f510eb 133 dbs->offset += dbs->iov.size;
59a703eb
AL
134
135 if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
c3adb5b9 136 dma_complete(dbs, ret);
59a703eb
AL
137 return;
138 }
4be74634 139 dma_blk_unmap(dbs);
59a703eb
AL
140
141 while (dbs->sg_cur_index < dbs->sg->nsg) {
142 cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
143 cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
df32fd1c 144 mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir);
59a703eb
AL
145 if (!mem)
146 break;
147 qemu_iovec_add(&dbs->iov, mem, cur_len);
148 dbs->sg_cur_byte += cur_len;
149 if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
150 dbs->sg_cur_byte = 0;
151 ++dbs->sg_cur_index;
152 }
153 }
154
155 if (dbs->iov.size == 0) {
c57c4658 156 trace_dma_map_wait(dbs);
8a8e63eb 157 dbs->bh = aio_bh_new(dbs->ctx, reschedule_dma, dbs);
e95205e1 158 cpu_register_map_client(dbs->bh);
59a703eb
AL
159 return;
160 }
161
99868af3
MCA
162 if (!QEMU_IS_ALIGNED(dbs->iov.size, dbs->align)) {
163 qemu_iovec_discard_back(&dbs->iov,
164 QEMU_ALIGN_DOWN(dbs->iov.size, dbs->align));
58f423fb
KW
165 }
166
1919631e 167 aio_context_acquire(dbs->ctx);
8a8e63eb
PB
168 dbs->acb = dbs->io_func(dbs->offset, &dbs->iov,
169 dma_blk_cb, dbs, dbs->io_func_opaque);
1919631e 170 aio_context_release(dbs->ctx);
6bee44ea 171 assert(dbs->acb);
59a703eb
AL
172}
173
7c84b1b8 174static void dma_aio_cancel(BlockAIOCB *acb)
c16b5a2c
CH
175{
176 DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
177
c57c4658
KW
178 trace_dma_aio_cancel(dbs);
179
539343c0 180 assert(!(dbs->acb && dbs->bh));
c16b5a2c 181 if (dbs->acb) {
539343c0 182 /* This will invoke dma_blk_cb. */
4be74634 183 blk_aio_cancel_async(dbs->acb);
539343c0 184 return;
c16b5a2c 185 }
539343c0 186
e95205e1
FZ
187 if (dbs->bh) {
188 cpu_unregister_map_client(dbs->bh);
189 qemu_bh_delete(dbs->bh);
190 dbs->bh = NULL;
191 }
539343c0
PB
192 if (dbs->common.cb) {
193 dbs->common.cb(dbs->common.opaque, -ECANCELED);
194 }
c16b5a2c
CH
195}
196
5fa78b2a
SH
197static AioContext *dma_get_aio_context(BlockAIOCB *acb)
198{
199 DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
200
201 return dbs->ctx;
202}
9bb9da46 203
d7331bed 204static const AIOCBInfo dma_aiocb_info = {
c16b5a2c 205 .aiocb_size = sizeof(DMAAIOCB),
9bb9da46 206 .cancel_async = dma_aio_cancel,
5fa78b2a 207 .get_aio_context = dma_get_aio_context,
c16b5a2c
CH
208};
209
8a8e63eb 210BlockAIOCB *dma_blk_io(AioContext *ctx,
99868af3 211 QEMUSGList *sg, uint64_t offset, uint32_t align,
8a8e63eb
PB
212 DMAIOFunc *io_func, void *io_func_opaque,
213 BlockCompletionFunc *cb,
43cf8ae6 214 void *opaque, DMADirection dir)
59a703eb 215{
8a8e63eb 216 DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, NULL, cb, opaque);
59a703eb 217
8a8e63eb 218 trace_dma_blk_io(dbs, io_func_opaque, offset, (dir == DMA_DIRECTION_TO_DEVICE));
c57c4658 219
37b7842c 220 dbs->acb = NULL;
59a703eb 221 dbs->sg = sg;
8a8e63eb 222 dbs->ctx = ctx;
cbe0ed62 223 dbs->offset = offset;
99868af3 224 dbs->align = align;
59a703eb
AL
225 dbs->sg_cur_index = 0;
226 dbs->sg_cur_byte = 0;
43cf8ae6 227 dbs->dir = dir;
cb144ccb 228 dbs->io_func = io_func;
8a8e63eb 229 dbs->io_func_opaque = io_func_opaque;
59a703eb
AL
230 dbs->bh = NULL;
231 qemu_iovec_init(&dbs->iov, sg->nsg);
4be74634 232 dma_blk_cb(dbs, 0);
37b7842c 233 return &dbs->common;
59a703eb
AL
234}
235
236
8a8e63eb
PB
237static
238BlockAIOCB *dma_blk_read_io_func(int64_t offset, QEMUIOVector *iov,
239 BlockCompletionFunc *cb, void *cb_opaque,
240 void *opaque)
241{
242 BlockBackend *blk = opaque;
243 return blk_aio_preadv(blk, offset, iov, 0, cb, cb_opaque);
244}
245
4be74634 246BlockAIOCB *dma_blk_read(BlockBackend *blk,
99868af3 247 QEMUSGList *sg, uint64_t offset, uint32_t align,
4be74634 248 void (*cb)(void *opaque, int ret), void *opaque)
59a703eb 249{
99868af3
MCA
250 return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
251 dma_blk_read_io_func, blk, cb, opaque,
4be74634 252 DMA_DIRECTION_FROM_DEVICE);
59a703eb
AL
253}
254
8a8e63eb
PB
255static
256BlockAIOCB *dma_blk_write_io_func(int64_t offset, QEMUIOVector *iov,
257 BlockCompletionFunc *cb, void *cb_opaque,
258 void *opaque)
259{
260 BlockBackend *blk = opaque;
261 return blk_aio_pwritev(blk, offset, iov, 0, cb, cb_opaque);
262}
263
4be74634 264BlockAIOCB *dma_blk_write(BlockBackend *blk,
99868af3 265 QEMUSGList *sg, uint64_t offset, uint32_t align,
4be74634 266 void (*cb)(void *opaque, int ret), void *opaque)
59a703eb 267{
99868af3
MCA
268 return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
269 dma_blk_write_io_func, blk, cb, opaque,
4be74634 270 DMA_DIRECTION_TO_DEVICE);
59a703eb 271}
8171ee35
PB
272
273
c65bcef3
DG
274static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg,
275 DMADirection dir)
8171ee35
PB
276{
277 uint64_t resid;
278 int sg_cur_index;
279
280 resid = sg->size;
281 sg_cur_index = 0;
282 len = MIN(len, resid);
283 while (len > 0) {
284 ScatterGatherEntry entry = sg->sg[sg_cur_index++];
285 int32_t xfer = MIN(len, entry.len);
df32fd1c 286 dma_memory_rw(sg->as, entry.base, ptr, xfer, dir);
8171ee35
PB
287 ptr += xfer;
288 len -= xfer;
289 resid -= xfer;
290 }
291
292 return resid;
293}
294
295uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg)
296{
c65bcef3 297 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
8171ee35
PB
298}
299
300uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg)
301{
c65bcef3 302 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
8171ee35 303}
84a69356 304
4be74634 305void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
84a69356
PB
306 QEMUSGList *sg, enum BlockAcctType type)
307{
4be74634 308 block_acct_start(blk_get_stats(blk), cookie, sg->size, type);
84a69356 309}