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Declare function before use, reduces compiler warning noise.
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b4608c04
FB
1/*
2 * gdb server stub
5fafdf24 3 *
3475187d 4 * Copyright (c) 2003-2005 Fabrice Bellard
b4608c04
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
978efd6a 20#include "config.h"
1fddef4b
FB
21#ifdef CONFIG_USER_ONLY
22#include <stdlib.h>
23#include <stdio.h>
24#include <stdarg.h>
25#include <string.h>
26#include <errno.h>
27#include <unistd.h>
978efd6a 28#include <fcntl.h>
1fddef4b
FB
29
30#include "qemu.h"
31#else
67b915a5 32#include "vl.h"
1fddef4b 33#endif
67b915a5 34
8f447cc7
FB
35#include "qemu_socket.h"
36#ifdef _WIN32
37/* XXX: these constants may be independent of the host ones even for Unix */
38#ifndef SIGTRAP
39#define SIGTRAP 5
40#endif
41#ifndef SIGINT
42#define SIGINT 2
43#endif
44#else
b4608c04 45#include <signal.h>
8f447cc7 46#endif
b4608c04 47
4abe615b 48//#define DEBUG_GDB
b4608c04 49
858693c6
FB
50enum RSState {
51 RS_IDLE,
52 RS_GETLINE,
53 RS_CHKSUM1,
54 RS_CHKSUM2,
a2d1ebaf 55 RS_SYSCALL,
858693c6 56};
858693c6 57typedef struct GDBState {
6a00d601 58 CPUState *env; /* current CPU */
41625033 59 enum RSState state; /* parsing state */
858693c6
FB
60 char line_buf[4096];
61 int line_buf_index;
62 int line_csum;
4046d913
PB
63 char last_packet[4100];
64 int last_packet_len;
41625033 65#ifdef CONFIG_USER_ONLY
4046d913 66 int fd;
41625033 67 int running_state;
4046d913
PB
68#else
69 CharDriverState *chr;
41625033 70#endif
858693c6 71} GDBState;
b4608c04 72
1fddef4b 73#ifdef CONFIG_USER_ONLY
4046d913
PB
74/* XXX: This is not thread safe. Do we care? */
75static int gdbserver_fd = -1;
76
1fddef4b
FB
77/* XXX: remove this hack. */
78static GDBState gdbserver_state;
1fddef4b 79
858693c6 80static int get_char(GDBState *s)
b4608c04
FB
81{
82 uint8_t ch;
83 int ret;
84
85 for(;;) {
8f447cc7 86 ret = recv(s->fd, &ch, 1, 0);
b4608c04
FB
87 if (ret < 0) {
88 if (errno != EINTR && errno != EAGAIN)
89 return -1;
90 } else if (ret == 0) {
91 return -1;
92 } else {
93 break;
94 }
95 }
96 return ch;
97}
4046d913 98#endif
b4608c04 99
a2d1ebaf
PB
100/* GDB stub state for use by semihosting syscalls. */
101static GDBState *gdb_syscall_state;
102static gdb_syscall_complete_cb gdb_current_syscall_cb;
103
104enum {
105 GDB_SYS_UNKNOWN,
106 GDB_SYS_ENABLED,
107 GDB_SYS_DISABLED,
108} gdb_syscall_mode;
109
110/* If gdb is connected when the first semihosting syscall occurs then use
111 remote gdb syscalls. Otherwise use native file IO. */
112int use_gdb_syscalls(void)
113{
114 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
115 gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
116 : GDB_SYS_DISABLED);
117 }
118 return gdb_syscall_mode == GDB_SYS_ENABLED;
119}
120
858693c6 121static void put_buffer(GDBState *s, const uint8_t *buf, int len)
b4608c04 122{
4046d913 123#ifdef CONFIG_USER_ONLY
b4608c04
FB
124 int ret;
125
126 while (len > 0) {
8f447cc7 127 ret = send(s->fd, buf, len, 0);
b4608c04
FB
128 if (ret < 0) {
129 if (errno != EINTR && errno != EAGAIN)
130 return;
131 } else {
132 buf += ret;
133 len -= ret;
134 }
135 }
4046d913
PB
136#else
137 qemu_chr_write(s->chr, buf, len);
138#endif
b4608c04
FB
139}
140
141static inline int fromhex(int v)
142{
143 if (v >= '0' && v <= '9')
144 return v - '0';
145 else if (v >= 'A' && v <= 'F')
146 return v - 'A' + 10;
147 else if (v >= 'a' && v <= 'f')
148 return v - 'a' + 10;
149 else
150 return 0;
151}
152
153static inline int tohex(int v)
154{
155 if (v < 10)
156 return v + '0';
157 else
158 return v - 10 + 'a';
159}
160
161static void memtohex(char *buf, const uint8_t *mem, int len)
162{
163 int i, c;
164 char *q;
165 q = buf;
166 for(i = 0; i < len; i++) {
167 c = mem[i];
168 *q++ = tohex(c >> 4);
169 *q++ = tohex(c & 0xf);
170 }
171 *q = '\0';
172}
173
174static void hextomem(uint8_t *mem, const char *buf, int len)
175{
176 int i;
177
178 for(i = 0; i < len; i++) {
179 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
180 buf += 2;
181 }
182}
183
b4608c04 184/* return -1 if error, 0 if OK */
858693c6 185static int put_packet(GDBState *s, char *buf)
b4608c04 186{
4046d913
PB
187 int len, csum, i;
188 char *p;
b4608c04
FB
189
190#ifdef DEBUG_GDB
191 printf("reply='%s'\n", buf);
192#endif
193
194 for(;;) {
4046d913
PB
195 p = s->last_packet;
196 *(p++) = '$';
b4608c04 197 len = strlen(buf);
4046d913
PB
198 memcpy(p, buf, len);
199 p += len;
b4608c04
FB
200 csum = 0;
201 for(i = 0; i < len; i++) {
202 csum += buf[i];
203 }
4046d913
PB
204 *(p++) = '#';
205 *(p++) = tohex((csum >> 4) & 0xf);
206 *(p++) = tohex((csum) & 0xf);
b4608c04 207
4046d913
PB
208 s->last_packet_len = p - s->last_packet;
209 put_buffer(s, s->last_packet, s->last_packet_len);
b4608c04 210
4046d913
PB
211#ifdef CONFIG_USER_ONLY
212 i = get_char(s);
213 if (i < 0)
b4608c04 214 return -1;
4046d913 215 if (i == '+')
b4608c04 216 break;
4046d913
PB
217#else
218 break;
219#endif
b4608c04
FB
220 }
221 return 0;
222}
223
6da41eaf
FB
224#if defined(TARGET_I386)
225
6da41eaf
FB
226static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
227{
e95c8d51 228 uint32_t *registers = (uint32_t *)mem_buf;
6da41eaf
FB
229 int i, fpus;
230
231 for(i = 0; i < 8; i++) {
e95c8d51 232 registers[i] = env->regs[i];
6da41eaf 233 }
e95c8d51
FB
234 registers[8] = env->eip;
235 registers[9] = env->eflags;
236 registers[10] = env->segs[R_CS].selector;
237 registers[11] = env->segs[R_SS].selector;
238 registers[12] = env->segs[R_DS].selector;
239 registers[13] = env->segs[R_ES].selector;
240 registers[14] = env->segs[R_FS].selector;
241 registers[15] = env->segs[R_GS].selector;
6da41eaf
FB
242 /* XXX: convert floats */
243 for(i = 0; i < 8; i++) {
244 memcpy(mem_buf + 16 * 4 + i * 10, &env->fpregs[i], 10);
245 }
e95c8d51 246 registers[36] = env->fpuc;
6da41eaf 247 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
e95c8d51
FB
248 registers[37] = fpus;
249 registers[38] = 0; /* XXX: convert tags */
250 registers[39] = 0; /* fiseg */
251 registers[40] = 0; /* fioff */
252 registers[41] = 0; /* foseg */
253 registers[42] = 0; /* fooff */
254 registers[43] = 0; /* fop */
3b46e624 255
e95c8d51
FB
256 for(i = 0; i < 16; i++)
257 tswapls(&registers[i]);
258 for(i = 36; i < 44; i++)
259 tswapls(&registers[i]);
6da41eaf
FB
260 return 44 * 4;
261}
262
263static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
264{
265 uint32_t *registers = (uint32_t *)mem_buf;
266 int i;
267
268 for(i = 0; i < 8; i++) {
269 env->regs[i] = tswapl(registers[i]);
270 }
e95c8d51
FB
271 env->eip = tswapl(registers[8]);
272 env->eflags = tswapl(registers[9]);
6da41eaf
FB
273#if defined(CONFIG_USER_ONLY)
274#define LOAD_SEG(index, sreg)\
275 if (tswapl(registers[index]) != env->segs[sreg].selector)\
276 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
277 LOAD_SEG(10, R_CS);
278 LOAD_SEG(11, R_SS);
279 LOAD_SEG(12, R_DS);
280 LOAD_SEG(13, R_ES);
281 LOAD_SEG(14, R_FS);
282 LOAD_SEG(15, R_GS);
283#endif
284}
285
9e62fd7f 286#elif defined (TARGET_PPC)
9e62fd7f
FB
287static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
288{
a541f297 289 uint32_t *registers = (uint32_t *)mem_buf, tmp;
9e62fd7f
FB
290 int i;
291
292 /* fill in gprs */
a541f297 293 for(i = 0; i < 32; i++) {
e95c8d51 294 registers[i] = tswapl(env->gpr[i]);
9e62fd7f
FB
295 }
296 /* fill in fprs */
297 for (i = 0; i < 32; i++) {
e95c8d51
FB
298 registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
299 registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
9e62fd7f
FB
300 }
301 /* nip, msr, ccr, lnk, ctr, xer, mq */
e95c8d51 302 registers[96] = tswapl(env->nip);
0411a972 303 registers[97] = tswapl(env->msr);
9e62fd7f
FB
304 tmp = 0;
305 for (i = 0; i < 8; i++)
a541f297 306 tmp |= env->crf[i] << (32 - ((i + 1) * 4));
e95c8d51
FB
307 registers[98] = tswapl(tmp);
308 registers[99] = tswapl(env->lr);
309 registers[100] = tswapl(env->ctr);
76a66253 310 registers[101] = tswapl(ppc_load_xer(env));
e95c8d51 311 registers[102] = 0;
a541f297
FB
312
313 return 103 * 4;
9e62fd7f
FB
314}
315
316static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
317{
318 uint32_t *registers = (uint32_t *)mem_buf;
319 int i;
320
321 /* fill in gprs */
322 for (i = 0; i < 32; i++) {
e95c8d51 323 env->gpr[i] = tswapl(registers[i]);
9e62fd7f
FB
324 }
325 /* fill in fprs */
326 for (i = 0; i < 32; i++) {
e95c8d51
FB
327 *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
328 *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
9e62fd7f
FB
329 }
330 /* nip, msr, ccr, lnk, ctr, xer, mq */
e95c8d51 331 env->nip = tswapl(registers[96]);
0411a972 332 ppc_store_msr(env, tswapl(registers[97]));
e95c8d51 333 registers[98] = tswapl(registers[98]);
9e62fd7f 334 for (i = 0; i < 8; i++)
a541f297 335 env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
e95c8d51
FB
336 env->lr = tswapl(registers[99]);
337 env->ctr = tswapl(registers[100]);
76a66253 338 ppc_store_xer(env, tswapl(registers[101]));
e95c8d51
FB
339}
340#elif defined (TARGET_SPARC)
341static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
342{
3475187d 343 target_ulong *registers = (target_ulong *)mem_buf;
e95c8d51
FB
344 int i;
345
346 /* fill in g0..g7 */
48b2c193 347 for(i = 0; i < 8; i++) {
e95c8d51
FB
348 registers[i] = tswapl(env->gregs[i]);
349 }
350 /* fill in register window */
351 for(i = 0; i < 24; i++) {
352 registers[i + 8] = tswapl(env->regwptr[i]);
353 }
9d9754a3 354#ifndef TARGET_SPARC64
e95c8d51
FB
355 /* fill in fprs */
356 for (i = 0; i < 32; i++) {
357 registers[i + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
358 }
359 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
360 registers[64] = tswapl(env->y);
3475187d
FB
361 {
362 target_ulong tmp;
363
364 tmp = GET_PSR(env);
365 registers[65] = tswapl(tmp);
366 }
e95c8d51
FB
367 registers[66] = tswapl(env->wim);
368 registers[67] = tswapl(env->tbr);
369 registers[68] = tswapl(env->pc);
370 registers[69] = tswapl(env->npc);
371 registers[70] = tswapl(env->fsr);
372 registers[71] = 0; /* csr */
373 registers[72] = 0;
3475187d
FB
374 return 73 * sizeof(target_ulong);
375#else
9d9754a3
FB
376 /* fill in fprs */
377 for (i = 0; i < 64; i += 2) {
378 uint64_t tmp;
379
8979596d
BS
380 tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
381 tmp |= *(uint32_t *)&env->fpr[i + 1];
382 registers[i / 2 + 32] = tswap64(tmp);
3475187d 383 }
9d9754a3
FB
384 registers[64] = tswapl(env->pc);
385 registers[65] = tswapl(env->npc);
17d996e1
BS
386 registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
387 ((env->asi & 0xff) << 24) |
388 ((env->pstate & 0xfff) << 8) |
389 GET_CWP64(env));
9d9754a3
FB
390 registers[67] = tswapl(env->fsr);
391 registers[68] = tswapl(env->fprs);
392 registers[69] = tswapl(env->y);
393 return 70 * sizeof(target_ulong);
3475187d 394#endif
e95c8d51
FB
395}
396
397static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
398{
3475187d 399 target_ulong *registers = (target_ulong *)mem_buf;
e95c8d51
FB
400 int i;
401
402 /* fill in g0..g7 */
403 for(i = 0; i < 7; i++) {
404 env->gregs[i] = tswapl(registers[i]);
405 }
406 /* fill in register window */
407 for(i = 0; i < 24; i++) {
3475187d 408 env->regwptr[i] = tswapl(registers[i + 8]);
e95c8d51 409 }
9d9754a3 410#ifndef TARGET_SPARC64
e95c8d51
FB
411 /* fill in fprs */
412 for (i = 0; i < 32; i++) {
413 *((uint32_t *)&env->fpr[i]) = tswapl(registers[i + 32]);
414 }
415 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
416 env->y = tswapl(registers[64]);
e80cfcfc 417 PUT_PSR(env, tswapl(registers[65]));
e95c8d51
FB
418 env->wim = tswapl(registers[66]);
419 env->tbr = tswapl(registers[67]);
420 env->pc = tswapl(registers[68]);
421 env->npc = tswapl(registers[69]);
422 env->fsr = tswapl(registers[70]);
3475187d 423#else
9d9754a3 424 for (i = 0; i < 64; i += 2) {
8979596d
BS
425 uint64_t tmp;
426
427 tmp = tswap64(registers[i / 2 + 32]);
428 *((uint32_t *)&env->fpr[i]) = tmp >> 32;
429 *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
3475187d 430 }
9d9754a3
FB
431 env->pc = tswapl(registers[64]);
432 env->npc = tswapl(registers[65]);
17d996e1
BS
433 {
434 uint64_t tmp = tswapl(registers[66]);
435
436 PUT_CCR(env, tmp >> 32);
437 env->asi = (tmp >> 24) & 0xff;
438 env->pstate = (tmp >> 8) & 0xfff;
439 PUT_CWP64(env, tmp & 0xff);
440 }
9d9754a3
FB
441 env->fsr = tswapl(registers[67]);
442 env->fprs = tswapl(registers[68]);
443 env->y = tswapl(registers[69]);
3475187d 444#endif
9e62fd7f 445}
1fddef4b
FB
446#elif defined (TARGET_ARM)
447static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
448{
449 int i;
450 uint8_t *ptr;
451
452 ptr = mem_buf;
453 /* 16 core integer registers (4 bytes each). */
454 for (i = 0; i < 16; i++)
455 {
456 *(uint32_t *)ptr = tswapl(env->regs[i]);
457 ptr += 4;
458 }
459 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
460 Not yet implemented. */
461 memset (ptr, 0, 8 * 12 + 4);
462 ptr += 8 * 12 + 4;
463 /* CPSR (4 bytes). */
b5ff1b31 464 *(uint32_t *)ptr = tswapl (cpsr_read(env));
1fddef4b
FB
465 ptr += 4;
466
467 return ptr - mem_buf;
468}
6da41eaf 469
1fddef4b
FB
470static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
471{
472 int i;
473 uint8_t *ptr;
474
475 ptr = mem_buf;
476 /* Core integer registers. */
477 for (i = 0; i < 16; i++)
478 {
479 env->regs[i] = tswapl(*(uint32_t *)ptr);
480 ptr += 4;
481 }
482 /* Ignore FPA regs and scr. */
483 ptr += 8 * 12 + 4;
b5ff1b31 484 cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
1fddef4b 485}
e6e5906b
PB
486#elif defined (TARGET_M68K)
487static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
488{
489 int i;
490 uint8_t *ptr;
491 CPU_DoubleU u;
492
493 ptr = mem_buf;
494 /* D0-D7 */
495 for (i = 0; i < 8; i++) {
496 *(uint32_t *)ptr = tswapl(env->dregs[i]);
497 ptr += 4;
498 }
499 /* A0-A7 */
500 for (i = 0; i < 8; i++) {
501 *(uint32_t *)ptr = tswapl(env->aregs[i]);
502 ptr += 4;
503 }
504 *(uint32_t *)ptr = tswapl(env->sr);
505 ptr += 4;
506 *(uint32_t *)ptr = tswapl(env->pc);
507 ptr += 4;
508 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
509 ColdFire has 8-bit double precision registers. */
510 for (i = 0; i < 8; i++) {
511 u.d = env->fregs[i];
512 *(uint32_t *)ptr = tswap32(u.l.upper);
513 *(uint32_t *)ptr = tswap32(u.l.lower);
514 }
515 /* FP control regs (not implemented). */
516 memset (ptr, 0, 3 * 4);
517 ptr += 3 * 4;
518
519 return ptr - mem_buf;
520}
521
522static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
523{
524 int i;
525 uint8_t *ptr;
526 CPU_DoubleU u;
527
528 ptr = mem_buf;
529 /* D0-D7 */
530 for (i = 0; i < 8; i++) {
531 env->dregs[i] = tswapl(*(uint32_t *)ptr);
532 ptr += 4;
533 }
534 /* A0-A7 */
535 for (i = 0; i < 8; i++) {
536 env->aregs[i] = tswapl(*(uint32_t *)ptr);
537 ptr += 4;
538 }
539 env->sr = tswapl(*(uint32_t *)ptr);
540 ptr += 4;
541 env->pc = tswapl(*(uint32_t *)ptr);
542 ptr += 4;
543 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
544 ColdFire has 8-bit double precision registers. */
545 for (i = 0; i < 8; i++) {
5fafdf24 546 u.l.upper = tswap32(*(uint32_t *)ptr);
e6e5906b
PB
547 u.l.lower = tswap32(*(uint32_t *)ptr);
548 env->fregs[i] = u.d;
549 }
550 /* FP control regs (not implemented). */
551 ptr += 3 * 4;
552}
6f970bd9
FB
553#elif defined (TARGET_MIPS)
554static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
555{
556 int i;
557 uint8_t *ptr;
558
559 ptr = mem_buf;
560 for (i = 0; i < 32; i++)
561 {
ead9360e 562 *(target_ulong *)ptr = tswapl(env->gpr[i][env->current_tc]);
2052caa7 563 ptr += sizeof(target_ulong);
6f970bd9
FB
564 }
565
7ac256b8 566 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
2052caa7 567 ptr += sizeof(target_ulong);
6f970bd9 568
ead9360e 569 *(target_ulong *)ptr = tswapl(env->LO[0][env->current_tc]);
2052caa7 570 ptr += sizeof(target_ulong);
6f970bd9 571
ead9360e 572 *(target_ulong *)ptr = tswapl(env->HI[0][env->current_tc]);
2052caa7 573 ptr += sizeof(target_ulong);
6f970bd9 574
2052caa7
TS
575 *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
576 ptr += sizeof(target_ulong);
6f970bd9 577
7ac256b8 578 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
2052caa7 579 ptr += sizeof(target_ulong);
6f970bd9 580
ead9360e 581 *(target_ulong *)ptr = tswapl(env->PC[env->current_tc]);
2052caa7 582 ptr += sizeof(target_ulong);
6f970bd9 583
36d23958 584 if (env->CP0_Config1 & (1 << CP0C1_FP))
8e33c08c 585 {
36d23958
TS
586 for (i = 0; i < 32; i++)
587 {
7ac256b8
TS
588 if (env->CP0_Status & (1 << CP0St_FR))
589 *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
590 else
591 *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
2052caa7 592 ptr += sizeof(target_ulong);
36d23958 593 }
8e33c08c 594
7ac256b8 595 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
2052caa7 596 ptr += sizeof(target_ulong);
8e33c08c 597
7ac256b8 598 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
2052caa7 599 ptr += sizeof(target_ulong);
36d23958 600 }
8e33c08c 601
7ac256b8
TS
602 /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
603 *(target_ulong *)ptr = 0;
604 ptr += sizeof(target_ulong);
605
606 /* Registers for embedded use, we just pad them. */
607 for (i = 0; i < 16; i++)
608 {
609 *(target_ulong *)ptr = 0;
610 ptr += sizeof(target_ulong);
611 }
612
613 /* Processor ID. */
614 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
615 ptr += sizeof(target_ulong);
6f970bd9
FB
616
617 return ptr - mem_buf;
618}
619
8e33c08c
TS
620/* convert MIPS rounding mode in FCR31 to IEEE library */
621static unsigned int ieee_rm[] =
622 {
623 float_round_nearest_even,
624 float_round_to_zero,
625 float_round_up,
626 float_round_down
627 };
628#define RESTORE_ROUNDING_MODE \
ead9360e 629 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
8e33c08c 630
6f970bd9
FB
631static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
632{
633 int i;
634 uint8_t *ptr;
635
636 ptr = mem_buf;
637 for (i = 0; i < 32; i++)
638 {
ead9360e 639 env->gpr[i][env->current_tc] = tswapl(*(target_ulong *)ptr);
2052caa7 640 ptr += sizeof(target_ulong);
6f970bd9
FB
641 }
642
2052caa7
TS
643 env->CP0_Status = tswapl(*(target_ulong *)ptr);
644 ptr += sizeof(target_ulong);
6f970bd9 645
ead9360e 646 env->LO[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
2052caa7 647 ptr += sizeof(target_ulong);
6f970bd9 648
ead9360e 649 env->HI[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
2052caa7 650 ptr += sizeof(target_ulong);
6f970bd9 651
2052caa7
TS
652 env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
653 ptr += sizeof(target_ulong);
6f970bd9 654
2052caa7
TS
655 env->CP0_Cause = tswapl(*(target_ulong *)ptr);
656 ptr += sizeof(target_ulong);
6f970bd9 657
ead9360e 658 env->PC[env->current_tc] = tswapl(*(target_ulong *)ptr);
2052caa7 659 ptr += sizeof(target_ulong);
8e33c08c 660
36d23958 661 if (env->CP0_Config1 & (1 << CP0C1_FP))
8e33c08c 662 {
36d23958
TS
663 for (i = 0; i < 32; i++)
664 {
7ac256b8
TS
665 if (env->CP0_Status & (1 << CP0St_FR))
666 env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
667 else
668 env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
2052caa7 669 ptr += sizeof(target_ulong);
36d23958 670 }
8e33c08c 671
7ac256b8 672 env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
2052caa7 673 ptr += sizeof(target_ulong);
8e33c08c 674
7ac256b8 675 /* The remaining registers are assumed to be read-only. */
8e33c08c 676
36d23958
TS
677 /* set rounding mode */
678 RESTORE_ROUNDING_MODE;
8e33c08c
TS
679
680#ifndef CONFIG_SOFTFLOAT
36d23958
TS
681 /* no floating point exception for native float */
682 SET_FP_ENABLE(env->fcr31, 0);
8e33c08c 683#endif
36d23958 684 }
6f970bd9 685}
fdf9b3e8 686#elif defined (TARGET_SH4)
6ef99fc5
TS
687
688/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
689
fdf9b3e8
FB
690static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
691{
692 uint32_t *ptr = (uint32_t *)mem_buf;
693 int i;
694
695#define SAVE(x) *ptr++=tswapl(x)
9c2a9ea1
PB
696 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
697 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
698 } else {
699 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
700 }
701 for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
fdf9b3e8
FB
702 SAVE (env->pc);
703 SAVE (env->pr);
704 SAVE (env->gbr);
705 SAVE (env->vbr);
706 SAVE (env->mach);
707 SAVE (env->macl);
708 SAVE (env->sr);
6ef99fc5
TS
709 SAVE (env->fpul);
710 SAVE (env->fpscr);
711 for (i = 0; i < 16; i++)
712 SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
713 SAVE (env->ssr);
714 SAVE (env->spc);
715 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
716 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
fdf9b3e8
FB
717 return ((uint8_t *)ptr - mem_buf);
718}
719
720static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
721{
722 uint32_t *ptr = (uint32_t *)mem_buf;
723 int i;
724
725#define LOAD(x) (x)=*ptr++;
9c2a9ea1
PB
726 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
727 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
728 } else {
729 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
730 }
731 for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
fdf9b3e8
FB
732 LOAD (env->pc);
733 LOAD (env->pr);
734 LOAD (env->gbr);
735 LOAD (env->vbr);
736 LOAD (env->mach);
737 LOAD (env->macl);
738 LOAD (env->sr);
6ef99fc5
TS
739 LOAD (env->fpul);
740 LOAD (env->fpscr);
741 for (i = 0; i < 16; i++)
742 LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
743 LOAD (env->ssr);
744 LOAD (env->spc);
745 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
746 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
fdf9b3e8 747}
f1ccf904
TS
748#elif defined (TARGET_CRIS)
749
750static int cris_save_32 (unsigned char *d, uint32_t value)
751{
752 *d++ = (value);
753 *d++ = (value >>= 8);
754 *d++ = (value >>= 8);
755 *d++ = (value >>= 8);
756 return 4;
757}
758static int cris_save_16 (unsigned char *d, uint32_t value)
759{
760 *d++ = (value);
761 *d++ = (value >>= 8);
762 return 2;
763}
764static int cris_save_8 (unsigned char *d, uint32_t value)
765{
766 *d++ = (value);
767 return 1;
768}
769
770/* FIXME: this will bug on archs not supporting unaligned word accesses. */
771static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
772{
773 uint8_t *ptr = mem_buf;
774 uint8_t srs;
775 int i;
776
777 for (i = 0; i < 16; i++)
778 ptr += cris_save_32 (ptr, env->regs[i]);
779
780 srs = env->pregs[SR_SRS];
781
782 ptr += cris_save_8 (ptr, env->pregs[0]);
783 ptr += cris_save_8 (ptr, env->pregs[1]);
784 ptr += cris_save_32 (ptr, env->pregs[2]);
785 ptr += cris_save_8 (ptr, srs);
786 ptr += cris_save_16 (ptr, env->pregs[4]);
787
788 for (i = 5; i < 16; i++)
789 ptr += cris_save_32 (ptr, env->pregs[i]);
790
791 ptr += cris_save_32 (ptr, env->pc);
792
793 for (i = 0; i < 16; i++)
794 ptr += cris_save_32 (ptr, env->sregs[srs][i]);
795
796 return ((uint8_t *)ptr - mem_buf);
797}
798
799static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
800{
801 uint32_t *ptr = (uint32_t *)mem_buf;
802 int i;
803
804#define LOAD(x) (x)=*ptr++;
805 for (i = 0; i < 16; i++) LOAD(env->regs[i]);
806 LOAD (env->pc);
807}
1fddef4b 808#else
6da41eaf
FB
809static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
810{
811 return 0;
812}
813
814static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
815{
816}
817
818#endif
b4608c04 819
1fddef4b 820static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
b4608c04 821{
b4608c04 822 const char *p;
858693c6 823 int ch, reg_size, type;
b4608c04 824 char buf[4096];
f1ccf904 825 uint8_t mem_buf[4096];
b4608c04 826 uint32_t *registers;
9d9754a3 827 target_ulong addr, len;
3b46e624 828
858693c6
FB
829#ifdef DEBUG_GDB
830 printf("command='%s'\n", line_buf);
831#endif
832 p = line_buf;
833 ch = *p++;
834 switch(ch) {
835 case '?':
1fddef4b 836 /* TODO: Make this return the correct value for user-mode. */
858693c6
FB
837 snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
838 put_packet(s, buf);
839 break;
840 case 'c':
841 if (*p != '\0') {
9d9754a3 842 addr = strtoull(p, (char **)&p, 16);
4c3a88a2 843#if defined(TARGET_I386)
858693c6 844 env->eip = addr;
5be1a8e0 845#elif defined (TARGET_PPC)
858693c6 846 env->nip = addr;
8d5f07fa
FB
847#elif defined (TARGET_SPARC)
848 env->pc = addr;
849 env->npc = addr + 4;
b5ff1b31
FB
850#elif defined (TARGET_ARM)
851 env->regs[15] = addr;
fdf9b3e8 852#elif defined (TARGET_SH4)
8fac5803
TS
853 env->pc = addr;
854#elif defined (TARGET_MIPS)
ead9360e 855 env->PC[env->current_tc] = addr;
f1ccf904
TS
856#elif defined (TARGET_CRIS)
857 env->pc = addr;
4c3a88a2 858#endif
858693c6 859 }
41625033
FB
860#ifdef CONFIG_USER_ONLY
861 s->running_state = 1;
862#else
863 vm_start();
864#endif
865 return RS_IDLE;
858693c6
FB
866 case 's':
867 if (*p != '\0') {
8fac5803 868 addr = strtoull(p, (char **)&p, 16);
c33a346e 869#if defined(TARGET_I386)
858693c6 870 env->eip = addr;
5be1a8e0 871#elif defined (TARGET_PPC)
858693c6 872 env->nip = addr;
8d5f07fa
FB
873#elif defined (TARGET_SPARC)
874 env->pc = addr;
875 env->npc = addr + 4;
b5ff1b31
FB
876#elif defined (TARGET_ARM)
877 env->regs[15] = addr;
fdf9b3e8 878#elif defined (TARGET_SH4)
8fac5803
TS
879 env->pc = addr;
880#elif defined (TARGET_MIPS)
ead9360e 881 env->PC[env->current_tc] = addr;
f1ccf904
TS
882#elif defined (TARGET_CRIS)
883 env->pc = addr;
c33a346e 884#endif
858693c6
FB
885 }
886 cpu_single_step(env, 1);
41625033
FB
887#ifdef CONFIG_USER_ONLY
888 s->running_state = 1;
889#else
890 vm_start();
891#endif
892 return RS_IDLE;
a2d1ebaf
PB
893 case 'F':
894 {
895 target_ulong ret;
896 target_ulong err;
897
898 ret = strtoull(p, (char **)&p, 16);
899 if (*p == ',') {
900 p++;
901 err = strtoull(p, (char **)&p, 16);
902 } else {
903 err = 0;
904 }
905 if (*p == ',')
906 p++;
907 type = *p;
908 if (gdb_current_syscall_cb)
909 gdb_current_syscall_cb(s->env, ret, err);
910 if (type == 'C') {
911 put_packet(s, "T02");
912 } else {
913#ifdef CONFIG_USER_ONLY
914 s->running_state = 1;
915#else
916 vm_start();
917#endif
918 }
919 }
920 break;
858693c6
FB
921 case 'g':
922 reg_size = cpu_gdb_read_registers(env, mem_buf);
923 memtohex(buf, mem_buf, reg_size);
924 put_packet(s, buf);
925 break;
926 case 'G':
927 registers = (void *)mem_buf;
928 len = strlen(p) / 2;
929 hextomem((uint8_t *)registers, p, len);
930 cpu_gdb_write_registers(env, mem_buf, len);
931 put_packet(s, "OK");
932 break;
933 case 'm':
9d9754a3 934 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
935 if (*p == ',')
936 p++;
9d9754a3 937 len = strtoull(p, NULL, 16);
6f970bd9
FB
938 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
939 put_packet (s, "E14");
940 } else {
941 memtohex(buf, mem_buf, len);
942 put_packet(s, buf);
943 }
858693c6
FB
944 break;
945 case 'M':
9d9754a3 946 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
947 if (*p == ',')
948 p++;
9d9754a3 949 len = strtoull(p, (char **)&p, 16);
b328f873 950 if (*p == ':')
858693c6
FB
951 p++;
952 hextomem(mem_buf, p, len);
953 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
905f20b1 954 put_packet(s, "E14");
858693c6
FB
955 else
956 put_packet(s, "OK");
957 break;
958 case 'Z':
959 type = strtoul(p, (char **)&p, 16);
960 if (*p == ',')
961 p++;
9d9754a3 962 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
963 if (*p == ',')
964 p++;
9d9754a3 965 len = strtoull(p, (char **)&p, 16);
858693c6
FB
966 if (type == 0 || type == 1) {
967 if (cpu_breakpoint_insert(env, addr) < 0)
968 goto breakpoint_error;
969 put_packet(s, "OK");
6658ffb8
PB
970#ifndef CONFIG_USER_ONLY
971 } else if (type == 2) {
972 if (cpu_watchpoint_insert(env, addr) < 0)
973 goto breakpoint_error;
974 put_packet(s, "OK");
975#endif
858693c6
FB
976 } else {
977 breakpoint_error:
905f20b1 978 put_packet(s, "E22");
858693c6
FB
979 }
980 break;
981 case 'z':
982 type = strtoul(p, (char **)&p, 16);
983 if (*p == ',')
984 p++;
9d9754a3 985 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
986 if (*p == ',')
987 p++;
9d9754a3 988 len = strtoull(p, (char **)&p, 16);
858693c6
FB
989 if (type == 0 || type == 1) {
990 cpu_breakpoint_remove(env, addr);
991 put_packet(s, "OK");
6658ffb8
PB
992#ifndef CONFIG_USER_ONLY
993 } else if (type == 2) {
994 cpu_watchpoint_remove(env, addr);
995 put_packet(s, "OK");
996#endif
858693c6
FB
997 } else {
998 goto breakpoint_error;
999 }
1000 break;
831b7825 1001#ifdef CONFIG_LINUX_USER
978efd6a
PB
1002 case 'q':
1003 if (strncmp(p, "Offsets", 7) == 0) {
1004 TaskState *ts = env->opaque;
1005
fe834d04
TS
1006 sprintf(buf,
1007 "Text=" TARGET_FMT_lx ";Data=" TARGET_FMT_lx ";Bss=" TARGET_FMT_lx,
1008 ts->info->code_offset,
1009 ts->info->data_offset,
1010 ts->info->data_offset);
978efd6a
PB
1011 put_packet(s, buf);
1012 break;
1013 }
1014 /* Fall through. */
1015#endif
858693c6
FB
1016 default:
1017 // unknown_command:
1018 /* put empty packet */
1019 buf[0] = '\0';
1020 put_packet(s, buf);
1021 break;
1022 }
1023 return RS_IDLE;
1024}
1025
612458f5
FB
1026extern void tb_flush(CPUState *env);
1027
1fddef4b 1028#ifndef CONFIG_USER_ONLY
858693c6
FB
1029static void gdb_vm_stopped(void *opaque, int reason)
1030{
1031 GDBState *s = opaque;
1032 char buf[256];
1033 int ret;
1034
a2d1ebaf
PB
1035 if (s->state == RS_SYSCALL)
1036 return;
1037
858693c6 1038 /* disable single step if it was enable */
6a00d601 1039 cpu_single_step(s->env, 0);
858693c6 1040
e80cfcfc 1041 if (reason == EXCP_DEBUG) {
6658ffb8 1042 if (s->env->watchpoint_hit) {
aa6290b7
PB
1043 snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
1044 SIGTRAP,
6658ffb8
PB
1045 s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
1046 put_packet(s, buf);
1047 s->env->watchpoint_hit = 0;
1048 return;
1049 }
6a00d601 1050 tb_flush(s->env);
858693c6 1051 ret = SIGTRAP;
bbeb7b5c
FB
1052 } else if (reason == EXCP_INTERRUPT) {
1053 ret = SIGINT;
1054 } else {
858693c6 1055 ret = 0;
bbeb7b5c 1056 }
858693c6
FB
1057 snprintf(buf, sizeof(buf), "S%02x", ret);
1058 put_packet(s, buf);
1059}
1fddef4b 1060#endif
858693c6 1061
a2d1ebaf
PB
1062/* Send a gdb syscall request.
1063 This accepts limited printf-style format specifiers, specifically:
a87295e8
PB
1064 %x - target_ulong argument printed in hex.
1065 %lx - 64-bit argument printed in hex.
1066 %s - string pointer (target_ulong) and length (int) pair. */
a2d1ebaf
PB
1067void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...)
1068{
1069 va_list va;
1070 char buf[256];
1071 char *p;
1072 target_ulong addr;
a87295e8 1073 uint64_t i64;
a2d1ebaf
PB
1074 GDBState *s;
1075
1076 s = gdb_syscall_state;
1077 if (!s)
1078 return;
1079 gdb_current_syscall_cb = cb;
1080 s->state = RS_SYSCALL;
1081#ifndef CONFIG_USER_ONLY
1082 vm_stop(EXCP_DEBUG);
1083#endif
1084 s->state = RS_IDLE;
1085 va_start(va, fmt);
1086 p = buf;
1087 *(p++) = 'F';
1088 while (*fmt) {
1089 if (*fmt == '%') {
1090 fmt++;
1091 switch (*fmt++) {
1092 case 'x':
1093 addr = va_arg(va, target_ulong);
1094 p += sprintf(p, TARGET_FMT_lx, addr);
1095 break;
a87295e8
PB
1096 case 'l':
1097 if (*(fmt++) != 'x')
1098 goto bad_format;
1099 i64 = va_arg(va, uint64_t);
1100 p += sprintf(p, "%" PRIx64, i64);
1101 break;
a2d1ebaf
PB
1102 case 's':
1103 addr = va_arg(va, target_ulong);
1104 p += sprintf(p, TARGET_FMT_lx "/%x", addr, va_arg(va, int));
1105 break;
1106 default:
a87295e8 1107 bad_format:
a2d1ebaf
PB
1108 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1109 fmt - 1);
1110 break;
1111 }
1112 } else {
1113 *(p++) = *(fmt++);
1114 }
1115 }
8a93e02a 1116 *p = 0;
a2d1ebaf
PB
1117 va_end(va);
1118 put_packet(s, buf);
1119#ifdef CONFIG_USER_ONLY
1120 gdb_handlesig(s->env, 0);
1121#else
1122 cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
1123#endif
1124}
1125
6a00d601 1126static void gdb_read_byte(GDBState *s, int ch)
858693c6 1127{
6a00d601 1128 CPUState *env = s->env;
858693c6
FB
1129 int i, csum;
1130 char reply[1];
1131
1fddef4b 1132#ifndef CONFIG_USER_ONLY
4046d913
PB
1133 if (s->last_packet_len) {
1134 /* Waiting for a response to the last packet. If we see the start
1135 of a new command then abandon the previous response. */
1136 if (ch == '-') {
1137#ifdef DEBUG_GDB
1138 printf("Got NACK, retransmitting\n");
1139#endif
1140 put_buffer(s, s->last_packet, s->last_packet_len);
1141 }
1142#ifdef DEBUG_GDB
1143 else if (ch == '+')
1144 printf("Got ACK\n");
1145 else
1146 printf("Got '%c' when expecting ACK/NACK\n", ch);
1147#endif
1148 if (ch == '+' || ch == '$')
1149 s->last_packet_len = 0;
1150 if (ch != '$')
1151 return;
1152 }
858693c6
FB
1153 if (vm_running) {
1154 /* when the CPU is running, we cannot do anything except stop
1155 it when receiving a char */
1156 vm_stop(EXCP_INTERRUPT);
5fafdf24 1157 } else
1fddef4b 1158#endif
41625033 1159 {
858693c6
FB
1160 switch(s->state) {
1161 case RS_IDLE:
1162 if (ch == '$') {
1163 s->line_buf_index = 0;
1164 s->state = RS_GETLINE;
c33a346e 1165 }
b4608c04 1166 break;
858693c6
FB
1167 case RS_GETLINE:
1168 if (ch == '#') {
1169 s->state = RS_CHKSUM1;
1170 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1171 s->state = RS_IDLE;
4c3a88a2 1172 } else {
858693c6 1173 s->line_buf[s->line_buf_index++] = ch;
4c3a88a2
FB
1174 }
1175 break;
858693c6
FB
1176 case RS_CHKSUM1:
1177 s->line_buf[s->line_buf_index] = '\0';
1178 s->line_csum = fromhex(ch) << 4;
1179 s->state = RS_CHKSUM2;
1180 break;
1181 case RS_CHKSUM2:
1182 s->line_csum |= fromhex(ch);
1183 csum = 0;
1184 for(i = 0; i < s->line_buf_index; i++) {
1185 csum += s->line_buf[i];
1186 }
1187 if (s->line_csum != (csum & 0xff)) {
1188 reply[0] = '-';
1189 put_buffer(s, reply, 1);
1190 s->state = RS_IDLE;
4c3a88a2 1191 } else {
858693c6
FB
1192 reply[0] = '+';
1193 put_buffer(s, reply, 1);
1fddef4b 1194 s->state = gdb_handle_packet(s, env, s->line_buf);
4c3a88a2
FB
1195 }
1196 break;
a2d1ebaf
PB
1197 default:
1198 abort();
858693c6
FB
1199 }
1200 }
1201}
1202
1fddef4b
FB
1203#ifdef CONFIG_USER_ONLY
1204int
1205gdb_handlesig (CPUState *env, int sig)
1206{
1207 GDBState *s;
1208 char buf[256];
1209 int n;
1210
1211 if (gdbserver_fd < 0)
1212 return sig;
1213
1214 s = &gdbserver_state;
1215
1216 /* disable single step if it was enabled */
1217 cpu_single_step(env, 0);
1218 tb_flush(env);
1219
1220 if (sig != 0)
1221 {
1222 snprintf(buf, sizeof(buf), "S%02x", sig);
1223 put_packet(s, buf);
1224 }
1225
1fddef4b
FB
1226 sig = 0;
1227 s->state = RS_IDLE;
41625033
FB
1228 s->running_state = 0;
1229 while (s->running_state == 0) {
1fddef4b
FB
1230 n = read (s->fd, buf, 256);
1231 if (n > 0)
1232 {
1233 int i;
1234
1235 for (i = 0; i < n; i++)
6a00d601 1236 gdb_read_byte (s, buf[i]);
1fddef4b
FB
1237 }
1238 else if (n == 0 || errno != EAGAIN)
1239 {
1240 /* XXX: Connection closed. Should probably wait for annother
1241 connection before continuing. */
1242 return sig;
1243 }
41625033 1244 }
1fddef4b
FB
1245 return sig;
1246}
e9009676
FB
1247
1248/* Tell the remote gdb that the process has exited. */
1249void gdb_exit(CPUState *env, int code)
1250{
1251 GDBState *s;
1252 char buf[4];
1253
1254 if (gdbserver_fd < 0)
1255 return;
1256
1257 s = &gdbserver_state;
1258
1259 snprintf(buf, sizeof(buf), "W%02x", code);
1260 put_packet(s, buf);
1261}
1262
1fddef4b 1263
7c9d8e07 1264static void gdb_accept(void *opaque)
858693c6
FB
1265{
1266 GDBState *s;
1267 struct sockaddr_in sockaddr;
1268 socklen_t len;
1269 int val, fd;
1270
1271 for(;;) {
1272 len = sizeof(sockaddr);
1273 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1274 if (fd < 0 && errno != EINTR) {
1275 perror("accept");
1276 return;
1277 } else if (fd >= 0) {
b4608c04
FB
1278 break;
1279 }
1280 }
858693c6
FB
1281
1282 /* set short latency */
1283 val = 1;
8f447cc7 1284 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
3b46e624 1285
1fddef4b
FB
1286 s = &gdbserver_state;
1287 memset (s, 0, sizeof (GDBState));
6a00d601 1288 s->env = first_cpu; /* XXX: allow to change CPU */
858693c6
FB
1289 s->fd = fd;
1290
a2d1ebaf
PB
1291 gdb_syscall_state = s;
1292
858693c6 1293 fcntl(fd, F_SETFL, O_NONBLOCK);
858693c6
FB
1294}
1295
1296static int gdbserver_open(int port)
1297{
1298 struct sockaddr_in sockaddr;
1299 int fd, val, ret;
1300
1301 fd = socket(PF_INET, SOCK_STREAM, 0);
1302 if (fd < 0) {
1303 perror("socket");
1304 return -1;
1305 }
1306
1307 /* allow fast reuse */
1308 val = 1;
8f447cc7 1309 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
858693c6
FB
1310
1311 sockaddr.sin_family = AF_INET;
1312 sockaddr.sin_port = htons(port);
1313 sockaddr.sin_addr.s_addr = 0;
1314 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1315 if (ret < 0) {
1316 perror("bind");
1317 return -1;
1318 }
1319 ret = listen(fd, 0);
1320 if (ret < 0) {
1321 perror("listen");
1322 return -1;
1323 }
858693c6
FB
1324 return fd;
1325}
1326
1327int gdbserver_start(int port)
1328{
1329 gdbserver_fd = gdbserver_open(port);
1330 if (gdbserver_fd < 0)
1331 return -1;
1332 /* accept connections */
7c9d8e07 1333 gdb_accept (NULL);
4046d913
PB
1334 return 0;
1335}
1fddef4b 1336#else
aa1f17c1 1337static int gdb_chr_can_receive(void *opaque)
4046d913
PB
1338{
1339 return 1;
1340}
1341
aa1f17c1 1342static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
4046d913
PB
1343{
1344 GDBState *s = opaque;
1345 int i;
1346
1347 for (i = 0; i < size; i++) {
1348 gdb_read_byte(s, buf[i]);
1349 }
1350}
1351
1352static void gdb_chr_event(void *opaque, int event)
1353{
1354 switch (event) {
1355 case CHR_EVENT_RESET:
1356 vm_stop(EXCP_INTERRUPT);
a2d1ebaf 1357 gdb_syscall_state = opaque;
4046d913
PB
1358 break;
1359 default:
1360 break;
1361 }
1362}
1363
cfc3475a 1364int gdbserver_start(const char *port)
4046d913
PB
1365{
1366 GDBState *s;
cfc3475a
PB
1367 char gdbstub_port_name[128];
1368 int port_num;
1369 char *p;
1370 CharDriverState *chr;
1371
1372 if (!port || !*port)
1373 return -1;
4046d913 1374
cfc3475a
PB
1375 port_num = strtol(port, &p, 10);
1376 if (*p == 0) {
1377 /* A numeric value is interpreted as a port number. */
1378 snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
1379 "tcp::%d,nowait,nodelay,server", port_num);
1380 port = gdbstub_port_name;
1381 }
1382
1383 chr = qemu_chr_open(port);
4046d913
PB
1384 if (!chr)
1385 return -1;
1386
1387 s = qemu_mallocz(sizeof(GDBState));
1388 if (!s) {
1389 return -1;
1390 }
1391 s->env = first_cpu; /* XXX: allow to change CPU */
1392 s->chr = chr;
aa1f17c1 1393 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
4046d913
PB
1394 gdb_chr_event, s);
1395 qemu_add_vm_stop_handler(gdb_vm_stopped, s);
b4608c04
FB
1396 return 0;
1397}
4046d913 1398#endif