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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
346160cb | 14 | #include "qemu/units.h" |
da34e65c | 15 | #include "qapi/error.h" |
c7c3c9f8 | 16 | #include "hw/misc/unimp.h" |
00442402 | 17 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 18 | #include "hw/char/serial.h" |
0b8fa32f | 19 | #include "qemu/module.h" |
ece09bee | 20 | #include "qemu/error-report.h" |
16020011 | 21 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 22 | #include "net/net.h" |
46517dd4 | 23 | #include "sysemu/sysemu.h" |
d780d056 | 24 | #include "target/arm/cpu-qom.h" |
43e3346e | 25 | |
ff90606f | 26 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 |
d783d1fe CLG |
27 | |
28 | static const hwaddr aspeed_soc_ast2400_memmap[] = { | |
5aa281d7 | 29 | [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, |
347df6f8 EH |
30 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
31 | [ASPEED_DEV_FMC] = 0x1E620000, | |
32 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
33 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
34 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
35 | [ASPEED_DEV_SDMC] = 0x1E6E0000, | |
36 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
a3888d75 | 37 | [ASPEED_DEV_HACE] = 0x1E6E3000, |
347df6f8 EH |
38 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
39 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
40 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
41 | [ASPEED_DEV_SRAM] = 0x1E720000, | |
42 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
43 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
44 | [ASPEED_DEV_RTC] = 0x1E781000, | |
45 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
46 | [ASPEED_DEV_WDT] = 0x1E785000, | |
47 | [ASPEED_DEV_PWM] = 0x1E786000, | |
48 | [ASPEED_DEV_LPC] = 0x1E789000, | |
49 | [ASPEED_DEV_IBT] = 0x1E789140, | |
50 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
55c57023 | 51 | [ASPEED_DEV_PECI] = 0x1E78B000, |
347df6f8 EH |
52 | [ASPEED_DEV_ETH1] = 0x1E660000, |
53 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
54 | [ASPEED_DEV_UART1] = 0x1E783000, | |
ab5e8605 PD |
55 | [ASPEED_DEV_UART2] = 0x1E78D000, |
56 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
57 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 EH |
58 | [ASPEED_DEV_UART5] = 0x1E784000, |
59 | [ASPEED_DEV_VUART] = 0x1E787000, | |
60 | [ASPEED_DEV_SDRAM] = 0x40000000, | |
d783d1fe CLG |
61 | }; |
62 | ||
63 | static const hwaddr aspeed_soc_ast2500_memmap[] = { | |
5aa281d7 | 64 | [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, |
347df6f8 EH |
65 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
66 | [ASPEED_DEV_FMC] = 0x1E620000, | |
67 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
68 | [ASPEED_DEV_SPI2] = 0x1E631000, | |
69 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
70 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
71 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
72 | [ASPEED_DEV_SDMC] = 0x1E6E0000, | |
73 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
a3888d75 | 74 | [ASPEED_DEV_HACE] = 0x1E6E3000, |
347df6f8 EH |
75 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
76 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
77 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
78 | [ASPEED_DEV_SRAM] = 0x1E720000, | |
79 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
80 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
81 | [ASPEED_DEV_RTC] = 0x1E781000, | |
82 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
83 | [ASPEED_DEV_WDT] = 0x1E785000, | |
84 | [ASPEED_DEV_PWM] = 0x1E786000, | |
85 | [ASPEED_DEV_LPC] = 0x1E789000, | |
86 | [ASPEED_DEV_IBT] = 0x1E789140, | |
87 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
55c57023 | 88 | [ASPEED_DEV_PECI] = 0x1E78B000, |
347df6f8 EH |
89 | [ASPEED_DEV_ETH1] = 0x1E660000, |
90 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
91 | [ASPEED_DEV_UART1] = 0x1E783000, | |
ab5e8605 PD |
92 | [ASPEED_DEV_UART2] = 0x1E78D000, |
93 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
94 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 EH |
95 | [ASPEED_DEV_UART5] = 0x1E784000, |
96 | [ASPEED_DEV_VUART] = 0x1E787000, | |
97 | [ASPEED_DEV_SDRAM] = 0x80000000, | |
d783d1fe | 98 | }; |
ff90606f | 99 | |
b456b113 | 100 | static const int aspeed_soc_ast2400_irqmap[] = { |
347df6f8 EH |
101 | [ASPEED_DEV_UART1] = 9, |
102 | [ASPEED_DEV_UART2] = 32, | |
103 | [ASPEED_DEV_UART3] = 33, | |
104 | [ASPEED_DEV_UART4] = 34, | |
105 | [ASPEED_DEV_UART5] = 10, | |
106 | [ASPEED_DEV_VUART] = 8, | |
107 | [ASPEED_DEV_FMC] = 19, | |
108 | [ASPEED_DEV_EHCI1] = 5, | |
109 | [ASPEED_DEV_EHCI2] = 13, | |
110 | [ASPEED_DEV_SDMC] = 0, | |
111 | [ASPEED_DEV_SCU] = 21, | |
112 | [ASPEED_DEV_ADC] = 31, | |
113 | [ASPEED_DEV_GPIO] = 20, | |
114 | [ASPEED_DEV_RTC] = 22, | |
115 | [ASPEED_DEV_TIMER1] = 16, | |
116 | [ASPEED_DEV_TIMER2] = 17, | |
117 | [ASPEED_DEV_TIMER3] = 18, | |
118 | [ASPEED_DEV_TIMER4] = 35, | |
119 | [ASPEED_DEV_TIMER5] = 36, | |
120 | [ASPEED_DEV_TIMER6] = 37, | |
121 | [ASPEED_DEV_TIMER7] = 38, | |
122 | [ASPEED_DEV_TIMER8] = 39, | |
123 | [ASPEED_DEV_WDT] = 27, | |
124 | [ASPEED_DEV_PWM] = 28, | |
125 | [ASPEED_DEV_LPC] = 8, | |
347df6f8 | 126 | [ASPEED_DEV_I2C] = 12, |
55c57023 | 127 | [ASPEED_DEV_PECI] = 15, |
347df6f8 EH |
128 | [ASPEED_DEV_ETH1] = 2, |
129 | [ASPEED_DEV_ETH2] = 3, | |
130 | [ASPEED_DEV_XDMA] = 6, | |
131 | [ASPEED_DEV_SDHCI] = 26, | |
a3888d75 | 132 | [ASPEED_DEV_HACE] = 4, |
b456b113 | 133 | }; |
43e3346e | 134 | |
b456b113 CLG |
135 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap |
136 | ||
699db715 | 137 | static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) |
b456b113 | 138 | { |
dd41ce7a | 139 | Aspeed2400SoCState *a = ASPEED2400_SOC(s); |
b456b113 CLG |
140 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
141 | ||
dd41ce7a | 142 | return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); |
b456b113 CLG |
143 | } |
144 | ||
a1508362 | 145 | static void aspeed_ast2400_soc_init(Object *obj) |
43e3346e | 146 | { |
dd41ce7a | 147 | Aspeed2400SoCState *a = ASPEED2400_SOC(obj); |
ff90606f | 148 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 149 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 150 | int i; |
811a5b1d CLG |
151 | char socname[8]; |
152 | char typename[64]; | |
153 | ||
54ecafb7 | 154 | if (sscanf(sc->name, "%7s", socname) != 1) { |
811a5b1d CLG |
155 | g_assert_not_reached(); |
156 | } | |
43e3346e | 157 | |
54ecafb7 | 158 | for (i = 0; i < sc->num_cpus; i++) { |
d815649c PMD |
159 | object_initialize_child(obj, "cpu[*]", &a->cpu[i], |
160 | aspeed_soc_cpu_type(sc)); | |
ece09bee | 161 | } |
43e3346e | 162 | |
9a937f6c | 163 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
db873cc5 | 164 | object_initialize_child(obj, "scu", &s->scu, typename); |
334973bb | 165 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
54ecafb7 | 166 | sc->silicon_rev); |
334973bb | 167 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
d2623129 | 168 | "hw-strap1"); |
334973bb | 169 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 170 | "hw-strap2"); |
b6e70d1d | 171 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 172 | "hw-prot-key"); |
7c1c69bc | 173 | |
dd41ce7a | 174 | object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); |
e2a11ca8 | 175 | |
db873cc5 | 176 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
75fb4577 | 177 | |
72d96f8e | 178 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
db873cc5 | 179 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
e2a11ca8 | 180 | |
199fd623 AJ |
181 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
182 | object_initialize_child(obj, "adc", &s->adc, typename); | |
183 | ||
f7da1aa8 | 184 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 185 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
e2a11ca8 | 186 | |
55c57023 PD |
187 | object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); |
188 | ||
811a5b1d | 189 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
db873cc5 | 190 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
7c1c69bc | 191 | |
54ecafb7 | 192 | for (i = 0; i < sc->spis_num; i++) { |
811a5b1d | 193 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); |
db873cc5 | 194 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
dbcabeeb | 195 | } |
c2da8a8b | 196 | |
bfdd34f1 | 197 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
198 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
199 | TYPE_PLATFORM_EHCI); | |
bfdd34f1 GR |
200 | } |
201 | ||
8e00d1a9 | 202 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 203 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
c6c7cfb0 | 204 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 205 | "ram-size"); |
013befe1 | 206 | |
54ecafb7 | 207 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d | 208 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); |
db873cc5 | 209 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f986ee1d | 210 | } |
ea337c65 | 211 | |
d300db02 | 212 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
213 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
214 | TYPE_FTGMAC100); | |
67340990 | 215 | } |
118c82e7 | 216 | |
d2b3eaef PD |
217 | for (i = 0; i < sc->uarts_num; i++) { |
218 | object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); | |
219 | } | |
220 | ||
8efbee28 CLG |
221 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
222 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
fdcc7c06 | 223 | |
811a5b1d | 224 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
db873cc5 | 225 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
2bea128c | 226 | |
db873cc5 | 227 | object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); |
2bea128c | 228 | |
5325cc34 | 229 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 230 | |
2bea128c EJ |
231 | /* Init sd card slot class here so that they're under the correct parent */ |
232 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
233 | object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], |
234 | TYPE_SYSBUS_SDHCI); | |
2bea128c | 235 | } |
2ecf1726 CLG |
236 | |
237 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
238 | |
239 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
240 | object_initialize_child(obj, "hace", &s->hace, typename); | |
80beb085 PD |
241 | |
242 | object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); | |
243 | object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); | |
43e3346e AJ |
244 | } |
245 | ||
aa6c6697 | 246 | static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
247 | { |
248 | int i; | |
dd41ce7a | 249 | Aspeed2400SoCState *a = ASPEED2400_SOC(dev); |
ff90606f | 250 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 251 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
72a7c473 | 252 | g_autofree char *sram_name = NULL; |
43e3346e | 253 | |
5aa281d7 CLG |
254 | /* Default boot region (SPI memory or ROMs) */ |
255 | memory_region_init(&s->spi_boot_container, OBJECT(s), | |
256 | "aspeed.spi_boot_container", 0x10000000); | |
257 | memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], | |
258 | &s->spi_boot_container); | |
259 | ||
43e3346e | 260 | /* IO space */ |
80beb085 PD |
261 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", |
262 | sc->memmap[ASPEED_DEV_IOMEM], | |
263 | ASPEED_SOC_IOMEM_SIZE); | |
43e3346e | 264 | |
514bcf6f | 265 | /* Video engine stub */ |
80beb085 PD |
266 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", |
267 | sc->memmap[ASPEED_DEV_VIDEO], 0x1000); | |
514bcf6f | 268 | |
2d105bd6 | 269 | /* CPU */ |
b7f1a0cb | 270 | for (i = 0; i < sc->num_cpus; i++) { |
dd41ce7a | 271 | object_property_set_link(OBJECT(&a->cpu[i]), "memory", |
4dd9d554 | 272 | OBJECT(s->memory), &error_abort); |
dd41ce7a | 273 | if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { |
ece09bee CLG |
274 | return; |
275 | } | |
2d105bd6 CLG |
276 | } |
277 | ||
74af4eec | 278 | /* SRAM */ |
dd41ce7a | 279 | sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); |
2198f5f0 PMD |
280 | if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, |
281 | errp)) { | |
74af4eec CLG |
282 | return; |
283 | } | |
4dd9d554 | 284 | memory_region_add_subregion(s->memory, |
347df6f8 | 285 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
74af4eec | 286 | |
e2a11ca8 | 287 | /* SCU */ |
668f62ec | 288 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
e2a11ca8 CLG |
289 | return; |
290 | } | |
5bfcbda7 | 291 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
e2a11ca8 | 292 | |
43e3346e | 293 | /* VIC */ |
dd41ce7a | 294 | if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { |
43e3346e AJ |
295 | return; |
296 | } | |
dd41ce7a PMD |
297 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); |
298 | sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, | |
299 | qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); | |
300 | sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, | |
301 | qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); | |
43e3346e | 302 | |
75fb4577 | 303 | /* RTC */ |
668f62ec | 304 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
75fb4577 JS |
305 | return; |
306 | } | |
5bfcbda7 | 307 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
75fb4577 | 308 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 309 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
75fb4577 | 310 | |
43e3346e | 311 | /* Timer */ |
5325cc34 MA |
312 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
313 | &error_abort); | |
668f62ec | 314 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
43e3346e AJ |
315 | return; |
316 | } | |
5bfcbda7 | 317 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, |
347df6f8 | 318 | sc->memmap[ASPEED_DEV_TIMER1]); |
b456b113 | 319 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
347df6f8 | 320 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
43e3346e AJ |
321 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
322 | } | |
323 | ||
199fd623 AJ |
324 | /* ADC */ |
325 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
326 | return; | |
327 | } | |
5bfcbda7 | 328 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); |
199fd623 AJ |
329 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, |
330 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
331 | ||
470253b6 | 332 | /* UART */ |
d2b3eaef PD |
333 | if (!aspeed_soc_uart_realize(s, errp)) { |
334 | return; | |
335 | } | |
16020011 CLG |
336 | |
337 | /* I2C */ | |
5325cc34 | 338 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 339 | &error_abort); |
668f62ec | 340 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
16020011 CLG |
341 | return; |
342 | } | |
5bfcbda7 | 343 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
16020011 | 344 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
347df6f8 | 345 | aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); |
7c1c69bc | 346 | |
55c57023 PD |
347 | /* PECI */ |
348 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { | |
349 | return; | |
350 | } | |
351 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, | |
352 | sc->memmap[ASPEED_DEV_PECI]); | |
353 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, | |
354 | aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); | |
355 | ||
26d5df95 | 356 | /* FMC, The number of CS is set at the board level */ |
5325cc34 | 357 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 358 | &error_abort); |
668f62ec | 359 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
7c1c69bc CLG |
360 | return; |
361 | } | |
5bfcbda7 PD |
362 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
363 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, | |
30b6852c | 364 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
0e5803df | 365 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 366 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
7c1c69bc | 367 | |
5aa281d7 CLG |
368 | /* Set up an alias on the FMC CE0 region (boot default) */ |
369 | MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; | |
370 | memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", | |
371 | fmc0_mmio, 0, memory_region_size(fmc0_mmio)); | |
372 | memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); | |
373 | ||
7c1c69bc | 374 | /* SPI */ |
54ecafb7 | 375 | for (i = 0; i < sc->spis_num; i++) { |
668f62ec | 376 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
dbcabeeb CLG |
377 | return; |
378 | } | |
5bfcbda7 | 379 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, |
347df6f8 | 380 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
5bfcbda7 | 381 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, |
30b6852c | 382 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
7c1c69bc | 383 | } |
c2da8a8b | 384 | |
bfdd34f1 GR |
385 | /* EHCI */ |
386 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 387 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
bfdd34f1 GR |
388 | return; |
389 | } | |
5bfcbda7 | 390 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 391 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
bfdd34f1 | 392 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 393 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
bfdd34f1 GR |
394 | } |
395 | ||
c2da8a8b | 396 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 397 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
c2da8a8b CLG |
398 | return; |
399 | } | |
5bfcbda7 PD |
400 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, |
401 | sc->memmap[ASPEED_DEV_SDMC]); | |
013befe1 CLG |
402 | |
403 | /* Watch dog */ | |
54ecafb7 | 404 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d | 405 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); |
6fdb4381 | 406 | hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; |
6112bd6d | 407 | |
5325cc34 MA |
408 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
409 | &error_abort); | |
668f62ec | 410 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f986ee1d JS |
411 | return; |
412 | } | |
6fdb4381 | 413 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); |
013befe1 | 414 | } |
ea337c65 | 415 | |
346160cb CLG |
416 | /* RAM */ |
417 | if (!aspeed_soc_dram_init(s, errp)) { | |
418 | return; | |
419 | } | |
420 | ||
ea337c65 | 421 | /* Net */ |
d3bad7e7 | 422 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 423 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 424 | &error_abort); |
668f62ec | 425 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 426 | return; |
67340990 | 427 | } |
5bfcbda7 | 428 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 429 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
67340990 | 430 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 431 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
ea337c65 | 432 | } |
118c82e7 EJ |
433 | |
434 | /* XDMA */ | |
668f62ec | 435 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
118c82e7 EJ |
436 | return; |
437 | } | |
5bfcbda7 | 438 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 439 | sc->memmap[ASPEED_DEV_XDMA]); |
118c82e7 | 440 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 441 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
fdcc7c06 RG |
442 | |
443 | /* GPIO */ | |
668f62ec | 444 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
fdcc7c06 RG |
445 | return; |
446 | } | |
5bfcbda7 PD |
447 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, |
448 | sc->memmap[ASPEED_DEV_GPIO]); | |
fdcc7c06 | 449 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 450 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
2bea128c EJ |
451 | |
452 | /* SDHCI */ | |
668f62ec | 453 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
2bea128c EJ |
454 | return; |
455 | } | |
5bfcbda7 | 456 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 457 | sc->memmap[ASPEED_DEV_SDHCI]); |
2bea128c | 458 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 459 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
2ecf1726 CLG |
460 | |
461 | /* LPC */ | |
462 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
463 | return; | |
464 | } | |
5bfcbda7 | 465 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); |
c59f781e AJ |
466 | |
467 | /* Connect the LPC IRQ to the VIC */ | |
2ecf1726 CLG |
468 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
469 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
470 | |
471 | /* | |
472 | * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the | |
473 | * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by | |
474 | * contrast, on the AST2600, the subdevice IRQs are connected straight to | |
475 | * the GIC). | |
476 | * | |
477 | * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output | |
478 | * to the VIC is at offset 0. | |
479 | */ | |
480 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
481 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); | |
482 | ||
483 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
484 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); | |
485 | ||
486 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
487 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); | |
488 | ||
489 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
490 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); | |
a3888d75 JS |
491 | |
492 | /* HACE */ | |
493 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
494 | &error_abort); | |
495 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
496 | return; | |
497 | } | |
5bfcbda7 PD |
498 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, |
499 | sc->memmap[ASPEED_DEV_HACE]); | |
a3888d75 JS |
500 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, |
501 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
43e3346e | 502 | } |
43e3346e | 503 | |
54ecafb7 | 504 | static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) |
43e3346e | 505 | { |
dc13909e PMD |
506 | static const char * const valid_cpu_types[] = { |
507 | ARM_CPU_TYPE_NAME("arm926"), | |
508 | NULL | |
509 | }; | |
54ecafb7 | 510 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
aa6c6697 PMD |
511 | DeviceClass *dc = DEVICE_CLASS(oc); |
512 | ||
513 | dc->realize = aspeed_ast2400_soc_realize; | |
514 | /* Reason: Uses serial_hds and nd_table in realize() directly */ | |
515 | dc->user_creatable = false; | |
b033271f | 516 | |
54ecafb7 | 517 | sc->name = "ast2400-a1"; |
dc13909e | 518 | sc->valid_cpu_types = valid_cpu_types; |
54ecafb7 CLG |
519 | sc->silicon_rev = AST2400_A1_SILICON_REV; |
520 | sc->sram_size = 0x8000; | |
521 | sc->spis_num = 1; | |
bfdd34f1 | 522 | sc->ehcis_num = 1; |
54ecafb7 | 523 | sc->wdts_num = 2; |
d300db02 | 524 | sc->macs_num = 2; |
c5e1bdb9 | 525 | sc->uarts_num = 5; |
54ecafb7 CLG |
526 | sc->irqmap = aspeed_soc_ast2400_irqmap; |
527 | sc->memmap = aspeed_soc_ast2400_memmap; | |
528 | sc->num_cpus = 1; | |
699db715 | 529 | sc->get_irq = aspeed_soc_ast2400_get_irq; |
54ecafb7 CLG |
530 | } |
531 | ||
54ecafb7 CLG |
532 | static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) |
533 | { | |
dc13909e PMD |
534 | static const char * const valid_cpu_types[] = { |
535 | ARM_CPU_TYPE_NAME("arm1176"), | |
536 | NULL | |
537 | }; | |
54ecafb7 | 538 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
aa6c6697 PMD |
539 | DeviceClass *dc = DEVICE_CLASS(oc); |
540 | ||
541 | dc->realize = aspeed_ast2400_soc_realize; | |
542 | /* Reason: Uses serial_hds and nd_table in realize() directly */ | |
543 | dc->user_creatable = false; | |
54ecafb7 CLG |
544 | |
545 | sc->name = "ast2500-a1"; | |
dc13909e | 546 | sc->valid_cpu_types = valid_cpu_types; |
54ecafb7 CLG |
547 | sc->silicon_rev = AST2500_A1_SILICON_REV; |
548 | sc->sram_size = 0x9000; | |
549 | sc->spis_num = 2; | |
bfdd34f1 | 550 | sc->ehcis_num = 2; |
54ecafb7 | 551 | sc->wdts_num = 3; |
d300db02 | 552 | sc->macs_num = 2; |
c5e1bdb9 | 553 | sc->uarts_num = 5; |
54ecafb7 CLG |
554 | sc->irqmap = aspeed_soc_ast2500_irqmap; |
555 | sc->memmap = aspeed_soc_ast2500_memmap; | |
556 | sc->num_cpus = 1; | |
699db715 | 557 | sc->get_irq = aspeed_soc_ast2400_get_irq; |
43e3346e AJ |
558 | } |
559 | ||
1a94fae4 PMD |
560 | static const TypeInfo aspeed_soc_ast2400_types[] = { |
561 | { | |
562 | .name = TYPE_ASPEED2400_SOC, | |
563 | .parent = TYPE_ASPEED_SOC, | |
564 | .instance_init = aspeed_ast2400_soc_init, | |
565 | .instance_size = sizeof(Aspeed2400SoCState), | |
566 | .abstract = true, | |
567 | }, { | |
568 | .name = "ast2400-a1", | |
569 | .parent = TYPE_ASPEED2400_SOC, | |
570 | .class_init = aspeed_soc_ast2400_class_init, | |
571 | }, { | |
572 | .name = "ast2500-a1", | |
573 | .parent = TYPE_ASPEED2400_SOC, | |
574 | .class_init = aspeed_soc_ast2500_class_init, | |
575 | }, | |
54ecafb7 CLG |
576 | }; |
577 | ||
1a94fae4 | 578 | DEFINE_TYPES(aspeed_soc_ast2400_types) |