]>
Commit | Line | Data |
---|---|---|
2f4ec776 PMD |
1 | /* |
2 | * ASPEED SoC family | |
3 | * | |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
14 | #include "qapi/error.h" | |
1a94fae4 | 15 | #include "hw/qdev-properties.h" |
2f4ec776 PMD |
16 | #include "hw/misc/unimp.h" |
17 | #include "hw/arm/aspeed_soc.h" | |
18 | #include "hw/char/serial.h" | |
19 | ||
20 | ||
d815649c PMD |
21 | const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) |
22 | { | |
23 | return sc->cpu_type; | |
24 | } | |
25 | ||
2f4ec776 PMD |
26 | qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) |
27 | { | |
28 | return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); | |
29 | } | |
30 | ||
31 | bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) | |
32 | { | |
33 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
34 | SerialMM *smm; | |
35 | ||
36 | for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { | |
37 | smm = &s->uart[i]; | |
38 | ||
39 | /* Chardev property is set by the machine. */ | |
40 | qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); | |
41 | qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); | |
42 | qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); | |
43 | qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); | |
44 | if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { | |
45 | return false; | |
46 | } | |
47 | ||
48 | sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart)); | |
49 | aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); | |
50 | } | |
51 | ||
52 | return true; | |
53 | } | |
54 | ||
55 | void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) | |
56 | { | |
57 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
58 | int i = dev - ASPEED_DEV_UART1; | |
59 | ||
60 | g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); | |
61 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); | |
62 | } | |
63 | ||
64 | /* | |
65 | * SDMC should be realized first to get correct RAM size and max size | |
66 | * values | |
67 | */ | |
68 | bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) | |
69 | { | |
70 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
71 | ram_addr_t ram_size, max_ram_size; | |
72 | ||
73 | ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", | |
74 | &error_abort); | |
75 | max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", | |
76 | &error_abort); | |
77 | ||
78 | memory_region_init(&s->dram_container, OBJECT(s), "ram-container", | |
79 | max_ram_size); | |
80 | memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); | |
81 | ||
82 | /* | |
83 | * Add a memory region beyond the RAM region to let firmwares scan | |
84 | * the address space with load/store and guess how much RAM the | |
85 | * SoC has. | |
86 | */ | |
87 | if (ram_size < max_ram_size) { | |
88 | DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); | |
89 | ||
90 | qdev_prop_set_string(dev, "name", "ram-empty"); | |
91 | qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); | |
92 | if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { | |
93 | return false; | |
94 | } | |
95 | ||
96 | memory_region_add_subregion_overlap(&s->dram_container, ram_size, | |
97 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); | |
98 | } | |
99 | ||
100 | memory_region_add_subregion(s->memory, | |
101 | sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); | |
102 | return true; | |
103 | } | |
104 | ||
105 | void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr) | |
106 | { | |
107 | memory_region_add_subregion(s->memory, addr, | |
108 | sysbus_mmio_get_region(dev, n)); | |
109 | } | |
110 | ||
111 | void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, | |
112 | const char *name, hwaddr addr, uint64_t size) | |
113 | { | |
114 | qdev_prop_set_string(DEVICE(dev), "name", name); | |
115 | qdev_prop_set_uint64(DEVICE(dev), "size", size); | |
116 | sysbus_realize(dev, &error_abort); | |
117 | ||
118 | memory_region_add_subregion_overlap(s->memory, addr, | |
119 | sysbus_mmio_get_region(dev, 0), -1000); | |
120 | } | |
1a94fae4 | 121 | |
24a88476 PMD |
122 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
123 | { | |
124 | AspeedSoCState *s = ASPEED_SOC(dev); | |
125 | ||
126 | if (!s->memory) { | |
127 | error_setg(errp, "'memory' link is not set"); | |
128 | return; | |
129 | } | |
130 | } | |
131 | ||
1a94fae4 PMD |
132 | static Property aspeed_soc_properties[] = { |
133 | DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, | |
134 | MemoryRegion *), | |
135 | DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, | |
136 | MemoryRegion *), | |
137 | DEFINE_PROP_END_OF_LIST(), | |
138 | }; | |
139 | ||
140 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) | |
141 | { | |
142 | DeviceClass *dc = DEVICE_CLASS(oc); | |
143 | ||
24a88476 | 144 | dc->realize = aspeed_soc_realize; |
1a94fae4 PMD |
145 | device_class_set_props(dc, aspeed_soc_properties); |
146 | } | |
147 | ||
148 | static const TypeInfo aspeed_soc_types[] = { | |
149 | { | |
150 | .name = TYPE_ASPEED_SOC, | |
151 | .parent = TYPE_DEVICE, | |
152 | .instance_size = sizeof(AspeedSoCState), | |
153 | .class_size = sizeof(AspeedSoCClass), | |
154 | .class_init = aspeed_soc_class_init, | |
155 | .abstract = true, | |
156 | }, | |
157 | }; | |
158 | ||
159 | DEFINE_TYPES(aspeed_soc_types) |