[mirror_qemu.git] / hw / arm / msf2-soc.c

/*
 * SmartFusion2 SoC emulation.
 *
 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "exec/address-spaces.h"
#include "hw/char/serial.h"
#include "hw/irq.h"
#include "hw/arm/msf2-soc.h"
#include "hw/misc/unimp.h"
#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"

#define MSF2_TIMER_BASE       0x40004000
#define MSF2_SYSREG_BASE      0x40038000
#define MSF2_EMAC_BASE        0x40041000

#define ENVM_BASE_ADDRESS     0x60000000

#define SRAM_BASE_ADDRESS     0x20000000

#define MSF2_EMAC_IRQ         12

#define MSF2_ENVM_MAX_SIZE    (512 * KiB)

/*
 * eSRAM max size is 80k without SECDED(Single error correction and
 * dual error detection) feature and 64k with SECDED.
 * We do not support SECDED now.
 */
#define MSF2_ESRAM_MAX_SIZE       (80 * KiB)

static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };

static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };

static void do_sys_reset(void *opaque, int n, int level)
{
    if (level) {
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
    }
}

static void m2sxxx_soc_initfn(Object *obj)
{
    MSF2State *s = MSF2_SOC(obj);
    int i;

    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);

    object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG);

    object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER);

    for (i = 0; i < MSF2_NUM_SPIS; i++) {
        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI);
    }

    object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
    if (nd_table[0].used) {
        qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
        qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
    }
}

static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
{
    MSF2State *s = MSF2_SOC(dev_soc);
    DeviceState *dev, *armv7m;
    SysBusDevice *busdev;
    Error *err = NULL;
    int i;

    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *nvm = g_new(MemoryRegion, 1);
    MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
    MemoryRegion *sram = g_new(MemoryRegion, 1);

    memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
                           &error_fatal);
    /*
     * On power-on, the eNVM region 0x60000000 is automatically
     * remapped to the Cortex-M3 processor executable region
     * start address (0x0). We do not support remapping other eNVM,
     * eSRAM and DDR regions by guest(via Sysreg) currently.
     */
    memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0,
                             s->envm_size);

    memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
    memory_region_add_subregion(system_memory, 0, nvm_alias);

    memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
                           &error_fatal);
    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);

    armv7m = DEVICE(&s->armv7m);
    qdev_prop_set_uint32(armv7m, "num-irq", 81);
    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
    qdev_prop_set_bit(armv7m, "enable-bitband", true);
    object_property_set_link(OBJECT(&s->armv7m), "memory",
                             OBJECT(get_system_memory()), &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err)) {
        error_propagate(errp, err);
        return;
    }

    if (!s->m3clk) {
        error_setg(errp, "Invalid m3clk value");
        error_append_hint(errp, "m3clk can not be zero\n");
        return;
    }

    qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
                                qemu_allocate_irq(&do_sys_reset, NULL, 0));

    system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;

    for (i = 0; i < MSF2_NUM_UARTS; i++) {
        if (serial_hd(i)) {
            serial_mm_init(get_system_memory(), uart_addr[i], 2,
                           qdev_get_gpio_in(armv7m, uart_irq[i]),
                           115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
        }
    }

    dev = DEVICE(&s->timer);
    /* APB0 clock is the timer input clock */
    qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), &err)) {
        error_propagate(errp, err);
        return;
    }
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
    sysbus_connect_irq(busdev, 0,
                           qdev_get_gpio_in(armv7m, timer_irq[0]));
    sysbus_connect_irq(busdev, 1,
                           qdev_get_gpio_in(armv7m, timer_irq[1]));

    dev = DEVICE(&s->sysreg);
    qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
    qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), &err)) {
        error_propagate(errp, err);
        return;
    }
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);

    for (i = 0; i < MSF2_NUM_SPIS; i++) {
        gchar *bus_name;

        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                           qdev_get_gpio_in(armv7m, spi_irq[i]));

        /* Alias controller SPI bus to the SoC itself */
        bus_name = g_strdup_printf("spi%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->spi[i]), "spi");
        g_free(bus_name);
    }

    dev = DEVICE(&s->emac);
    object_property_set_link(OBJECT(&s->emac), "ahb-bus",
                             OBJECT(get_system_memory()), &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err)) {
        error_propagate(errp, err);
        return;
    }
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
    sysbus_connect_irq(busdev, 0,
                       qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));

    /* Below devices are not modelled yet. */
    create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
    create_unimplemented_device("dma", 0x40003000, 0x1000);
    create_unimplemented_device("watchdog", 0x40005000, 0x1000);
    create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
    create_unimplemented_device("gpio", 0x40013000, 0x1000);
    create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
    create_unimplemented_device("can", 0x40015000, 0x1000);
    create_unimplemented_device("rtc", 0x40017000, 0x1000);
    create_unimplemented_device("apb_config", 0x40020000, 0x10000);
    create_unimplemented_device("usb", 0x40043000, 0x1000);
}

static Property m2sxxx_soc_properties[] = {
    /*
     * part name specifies the type of SmartFusion2 device variant(this
     * property is for information purpose only.
     */
    DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
    DEFINE_PROP_STRING("part-name", MSF2State, part_name),
    DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
    DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
                        MSF2_ESRAM_MAX_SIZE),
    /* Libero GUI shows 100Mhz as default for clocks */
    DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
    /* default divisors in Libero GUI */
    DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
    DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
    DEFINE_PROP_END_OF_LIST(),
};

static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = m2sxxx_soc_realize;
    device_class_set_props(dc, m2sxxx_soc_properties);
}

static const TypeInfo m2sxxx_soc_info = {
    .name          = TYPE_MSF2_SOC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MSF2State),
    .instance_init = m2sxxx_soc_initfn,
    .class_init    = m2sxxx_soc_class_init,
};

static void m2sxxx_soc_types(void)
{
    type_register_static(&m2sxxx_soc_info);
}

type_init(m2sxxx_soc_types)
Commit	Line	Data
ebc1fbb4 SS	1	/*
	2	* SmartFusion2 SoC emulation.
	3	*
05b7374a	4	* Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
ebc1fbb4 SS	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "qemu/osdep.h"
fc6b3cf9	26	#include "qemu/units.h"
ebc1fbb4	27	#include "qapi/error.h"
ebc1fbb4 SS	28	#include "exec/address-spaces.h"
ebc1fbb4 SS	29	#include "hw/char/serial.h"
64552b6b	30	#include "hw/irq.h"
ebc1fbb4 SS	31	#include "hw/arm/msf2-soc.h"
ebc1fbb4 SS	32	#include "hw/misc/unimp.h"
54d31236	33	#include "sysemu/runstate.h"
46517dd4	34	#include "sysemu/sysemu.h"
ebc1fbb4 SS	35
	36	#define MSF2_TIMER_BASE 0x40004000
	37	#define MSF2_SYSREG_BASE 0x40038000
05b7374a	38	#define MSF2_EMAC_BASE 0x40041000
ebc1fbb4 SS	39
	40	#define ENVM_BASE_ADDRESS 0x60000000
	41
	42	#define SRAM_BASE_ADDRESS 0x20000000
	43
05b7374a SS	44	#define MSF2_EMAC_IRQ 12
05b7374a SS	45
d23b6caa	46	#define MSF2_ENVM_MAX_SIZE (512 * KiB)
ebc1fbb4 SS	47
	48	/*
	49	* eSRAM max size is 80k without SECDED(Single error correction and
	50	* dual error detection) feature and 64k with SECDED.
	51	* We do not support SECDED now.
	52	*/
d23b6caa	53	#define MSF2_ESRAM_MAX_SIZE (80 * KiB)
ebc1fbb4 SS	54
	55	static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
	56	static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
	57
	58	static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
	59	static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
	60	static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
	61
db7b98c6 SS	62	static void do_sys_reset(void *opaque, int n, int level)
	63	{
	64	if (level) {
	65	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
	66	}
	67	}
	68
ebc1fbb4 SS	69	static void m2sxxx_soc_initfn(Object *obj)
	70	{
	71	MSF2State *s = MSF2_SOC(obj);
	72	int i;
	73
db873cc5	74	object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
ebc1fbb4	75
db873cc5	76	object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG);
ebc1fbb4	77
db873cc5	78	object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER);
ebc1fbb4 SS	79
ebc1fbb4 SS	80	for (i = 0; i < MSF2_NUM_SPIS; i++) {
db873cc5	81	object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI);
ebc1fbb4	82	}
05b7374a	83
db873cc5	84	object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
05b7374a SS	85	if (nd_table[0].used) {
	86	qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
	87	qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
	88	}
ebc1fbb4 SS	89	}
	90
	91	static void m2sxxx_soc_realize(DeviceState dev_soc, Error *errp)
	92	{
	93	MSF2State *s = MSF2_SOC(dev_soc);
	94	DeviceState dev, armv7m;
	95	SysBusDevice *busdev;
	96	Error *err = NULL;
	97	int i;
	98
	99	MemoryRegion *system_memory = get_system_memory();
	100	MemoryRegion *nvm = g_new(MemoryRegion, 1);
	101	MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
	102	MemoryRegion *sram = g_new(MemoryRegion, 1);
	103
32b9523a	104	memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
ebc1fbb4 SS	105	&error_fatal);
	106	/*
	107	* On power-on, the eNVM region 0x60000000 is automatically
	108	* remapped to the Cortex-M3 processor executable region
	109	* start address (0x0). We do not support remapping other eNVM,
	110	* eSRAM and DDR regions by guest(via Sysreg) currently.
	111	*/
32b9523a PMD	112	memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0,
32b9523a PMD	113	s->envm_size);
ebc1fbb4 SS	114
	115	memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
	116	memory_region_add_subregion(system_memory, 0, nvm_alias);
	117
	118	memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
	119	&error_fatal);
	120	memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
	121
	122	armv7m = DEVICE(&s->armv7m);
	123	qdev_prop_set_uint32(armv7m, "num-irq", 81);
	124	qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
a1c5a062	125	qdev_prop_set_bit(armv7m, "enable-bitband", true);
5325cc34 MA	126	object_property_set_link(OBJECT(&s->armv7m), "memory",
5325cc34 MA	127	OBJECT(get_system_memory()), &error_abort);
118bfd76	128	if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err)) {
ebc1fbb4 SS	129	error_propagate(errp, err);
	130	return;
	131	}
	132
	133	if (!s->m3clk) {
	134	error_setg(errp, "Invalid m3clk value");
	135	error_append_hint(errp, "m3clk can not be zero\n");
	136	return;
	137	}
db7b98c6 SS	138
	139	qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
	140	qemu_allocate_irq(&do_sys_reset, NULL, 0));
	141
ebc1fbb4 SS	142	system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
	143
	144	for (i = 0; i < MSF2_NUM_UARTS; i++) {
9bca0edb	145	if (serial_hd(i)) {
ebc1fbb4 SS	146	serial_mm_init(get_system_memory(), uart_addr[i], 2,
ebc1fbb4 SS	147	qdev_get_gpio_in(armv7m, uart_irq[i]),
9bca0edb	148	115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
ebc1fbb4 SS	149	}
	150	}
	151
	152	dev = DEVICE(&s->timer);
	153	/* APB0 clock is the timer input clock */
	154	qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
118bfd76	155	if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), &err)) {
ebc1fbb4 SS	156	error_propagate(errp, err);
	157	return;
	158	}
	159	busdev = SYS_BUS_DEVICE(dev);
	160	sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
	161	sysbus_connect_irq(busdev, 0,
	162	qdev_get_gpio_in(armv7m, timer_irq[0]));
	163	sysbus_connect_irq(busdev, 1,
	164	qdev_get_gpio_in(armv7m, timer_irq[1]));
	165
	166	dev = DEVICE(&s->sysreg);
	167	qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
	168	qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
118bfd76	169	if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), &err)) {
ebc1fbb4 SS	170	error_propagate(errp, err);
	171	return;
	172	}
	173	busdev = SYS_BUS_DEVICE(dev);
	174	sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
	175
	176	for (i = 0; i < MSF2_NUM_SPIS; i++) {
	177	gchar *bus_name;
	178
118bfd76	179	if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) {
ebc1fbb4 SS	180	error_propagate(errp, err);
	181	return;
	182	}
	183
	184	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
	185	sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
	186	qdev_get_gpio_in(armv7m, spi_irq[i]));
	187
	188	/* Alias controller SPI bus to the SoC itself */
	189	bus_name = g_strdup_printf("spi%d", i);
	190	object_property_add_alias(OBJECT(s), bus_name,
d2623129	191	OBJECT(&s->spi[i]), "spi");
ebc1fbb4 SS	192	g_free(bus_name);
	193	}
	194
05b7374a	195	dev = DEVICE(&s->emac);
5325cc34 MA	196	object_property_set_link(OBJECT(&s->emac), "ahb-bus",
5325cc34 MA	197	OBJECT(get_system_memory()), &error_abort);
118bfd76	198	if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err)) {
05b7374a SS	199	error_propagate(errp, err);
	200	return;
	201	}
	202	busdev = SYS_BUS_DEVICE(dev);
	203	sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
	204	sysbus_connect_irq(busdev, 0,
	205	qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));
	206
ebc1fbb4 SS	207	/* Below devices are not modelled yet. */
	208	create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
	209	create_unimplemented_device("dma", 0x40003000, 0x1000);
	210	create_unimplemented_device("watchdog", 0x40005000, 0x1000);
	211	create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
	212	create_unimplemented_device("gpio", 0x40013000, 0x1000);
	213	create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
	214	create_unimplemented_device("can", 0x40015000, 0x1000);
	215	create_unimplemented_device("rtc", 0x40017000, 0x1000);
	216	create_unimplemented_device("apb_config", 0x40020000, 0x10000);
ebc1fbb4 SS	217	create_unimplemented_device("usb", 0x40043000, 0x1000);
	218	}
	219
	220	static Property m2sxxx_soc_properties[] = {
	221	/*
	222	* part name specifies the type of SmartFusion2 device variant(this
	223	* property is for information purpose only.
	224	*/
	225	DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
	226	DEFINE_PROP_STRING("part-name", MSF2State, part_name),
	227	DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
	228	DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
	229	MSF2_ESRAM_MAX_SIZE),
	230	/* Libero GUI shows 100Mhz as default for clocks */
	231	DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
	232	/* default divisors in Libero GUI */
	233	DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
	234	DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
	235	DEFINE_PROP_END_OF_LIST(),
	236	};
	237
	238	static void m2sxxx_soc_class_init(ObjectClass klass, void data)
	239	{
	240	DeviceClass *dc = DEVICE_CLASS(klass);
	241
	242	dc->realize = m2sxxx_soc_realize;
4f67d30b	243	device_class_set_props(dc, m2sxxx_soc_properties);
ebc1fbb4 SS	244	}
	245
	246	static const TypeInfo m2sxxx_soc_info = {
	247	.name = TYPE_MSF2_SOC,
	248	.parent = TYPE_SYS_BUS_DEVICE,
	249	.instance_size = sizeof(MSF2State),
	250	.instance_init = m2sxxx_soc_initfn,
	251	.class_init = m2sxxx_soc_class_init,
	252	};
	253
	254	static void m2sxxx_soc_types(void)
	255	{
	256	type_register_static(&m2sxxx_soc_info);
	257	}
	258
	259	type_init(m2sxxx_soc_types)