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Commit | Line | Data |
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b89de436 EI |
1 | /* |
2 | * Xilinx Versal SoC model. | |
3 | * | |
4 | * Copyright (c) 2018 Xilinx Inc. | |
5 | * Written by Edgar E. Iglesias | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
a55b441b | 13 | #include "qemu/units.h" |
b89de436 | 14 | #include "qapi/error.h" |
2394c782 | 15 | #include "qapi/qmp/qlist.h" |
0b8fa32f | 16 | #include "qemu/module.h" |
b89de436 EI |
17 | #include "hw/sysbus.h" |
18 | #include "net/net.h" | |
19 | #include "sysemu/sysemu.h" | |
20 | #include "sysemu/kvm.h" | |
12ec8bd5 | 21 | #include "hw/arm/boot.h" |
b89de436 EI |
22 | #include "kvm_arm.h" |
23 | #include "hw/misc/unimp.h" | |
b89de436 | 24 | #include "hw/arm/xlnx-versal.h" |
f7c9aecb | 25 | #include "qemu/log.h" |
d780d056 | 26 | #include "target/arm/cpu-qom.h" |
b89de436 EI |
27 | |
28 | #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") | |
67a645a3 | 29 | #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") |
b89de436 EI |
30 | #define GEM_REVISION 0x40070106 |
31 | ||
4a0244b4 | 32 | #define VERSAL_NUM_PMC_APB_IRQS 18 |
868d9680 | 33 | #define NUM_OSPI_IRQ_LINES 3 |
9a6d4918 | 34 | |
b89de436 EI |
35 | static void versal_create_apu_cpus(Versal *s) |
36 | { | |
37 | int i; | |
38 | ||
8779d00c EI |
39 | object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, |
40 | TYPE_CPU_CLUSTER); | |
41 | qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); | |
42 | ||
b89de436 EI |
43 | for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { |
44 | Object *obj; | |
b89de436 | 45 | |
8779d00c EI |
46 | object_initialize_child(OBJECT(&s->fpd.apu.cluster), |
47 | "apu-cpu[*]", &s->fpd.apu.cpu[i], | |
9fc7fc4d | 48 | XLNX_VERSAL_ACPU_TYPE); |
ced18d5e | 49 | obj = OBJECT(&s->fpd.apu.cpu[i]); |
b89de436 | 50 | if (i) { |
9437a76e | 51 | /* Secondary CPUs start in powered-down state */ |
5325cc34 MA |
52 | object_property_set_bool(obj, "start-powered-off", true, |
53 | &error_abort); | |
b89de436 EI |
54 | } |
55 | ||
5325cc34 MA |
56 | object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu), |
57 | &error_abort); | |
58 | object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr), | |
b89de436 | 59 | &error_abort); |
ce189ab2 | 60 | qdev_realize(DEVICE(obj), NULL, &error_fatal); |
b89de436 | 61 | } |
8779d00c EI |
62 | |
63 | qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); | |
b89de436 EI |
64 | } |
65 | ||
66 | static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | |
67 | { | |
68 | static const uint64_t addrs[] = { | |
69 | MM_GIC_APU_DIST_MAIN, | |
70 | MM_GIC_APU_REDIST_0 | |
71 | }; | |
72 | SysBusDevice *gicbusdev; | |
73 | DeviceState *gicdev; | |
2394c782 | 74 | QList *redist_region_count; |
b89de436 EI |
75 | int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu); |
76 | int i; | |
77 | ||
0074fce6 MA |
78 | object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic, |
79 | gicv3_class_name()); | |
b89de436 EI |
80 | gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic); |
81 | gicdev = DEVICE(&s->fpd.apu.gic); | |
82 | qdev_prop_set_uint32(gicdev, "revision", 3); | |
4565d826 | 83 | qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus); |
b89de436 | 84 | qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); |
2394c782 KW |
85 | |
86 | redist_region_count = qlist_new(); | |
87 | qlist_append_int(redist_region_count, nr_apu_cpus); | |
88 | qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); | |
89 | ||
b89de436 EI |
90 | qdev_prop_set_bit(gicdev, "has-security-extensions", true); |
91 | ||
0074fce6 | 92 | sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal); |
b89de436 EI |
93 | |
94 | for (i = 0; i < ARRAY_SIZE(addrs); i++) { | |
95 | MemoryRegion *mr; | |
96 | ||
97 | mr = sysbus_mmio_get_region(gicbusdev, i); | |
98 | memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr); | |
99 | } | |
100 | ||
101 | for (i = 0; i < nr_apu_cpus; i++) { | |
ced18d5e | 102 | DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]); |
b89de436 EI |
103 | int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; |
104 | qemu_irq maint_irq; | |
105 | int ti; | |
106 | /* Mapping from the output timer irq lines from the CPU to the | |
107 | * GIC PPI inputs. | |
108 | */ | |
109 | const int timer_irq[] = { | |
110 | [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ, | |
111 | [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ, | |
112 | [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ, | |
113 | [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ, | |
114 | }; | |
115 | ||
116 | for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) { | |
117 | qdev_connect_gpio_out(cpudev, ti, | |
118 | qdev_get_gpio_in(gicdev, | |
119 | ppibase + timer_irq[ti])); | |
120 | } | |
121 | maint_irq = qdev_get_gpio_in(gicdev, | |
122 | ppibase + VERSAL_GIC_MAINT_IRQ); | |
123 | qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", | |
124 | 0, maint_irq); | |
125 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | |
126 | sysbus_connect_irq(gicbusdev, i + nr_apu_cpus, | |
127 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
128 | sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus, | |
129 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | |
130 | sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus, | |
131 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | |
132 | } | |
133 | ||
134 | for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) { | |
135 | pic[i] = qdev_get_gpio_in(gicdev, i); | |
136 | } | |
137 | } | |
138 | ||
67a645a3 EI |
139 | static void versal_create_rpu_cpus(Versal *s) |
140 | { | |
141 | int i; | |
142 | ||
143 | object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, | |
144 | TYPE_CPU_CLUSTER); | |
145 | qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); | |
146 | ||
147 | for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { | |
148 | Object *obj; | |
149 | ||
150 | object_initialize_child(OBJECT(&s->lpd.rpu.cluster), | |
151 | "rpu-cpu[*]", &s->lpd.rpu.cpu[i], | |
152 | XLNX_VERSAL_RCPU_TYPE); | |
153 | obj = OBJECT(&s->lpd.rpu.cpu[i]); | |
154 | object_property_set_bool(obj, "start-powered-off", true, | |
155 | &error_abort); | |
156 | ||
157 | object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); | |
158 | object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), | |
159 | &error_abort); | |
160 | object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), | |
161 | &error_abort); | |
162 | qdev_realize(DEVICE(obj), NULL, &error_fatal); | |
163 | } | |
164 | ||
165 | qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); | |
166 | } | |
167 | ||
b89de436 EI |
168 | static void versal_create_uarts(Versal *s, qemu_irq *pic) |
169 | { | |
170 | int i; | |
171 | ||
172 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { | |
173 | static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0}; | |
174 | static const uint64_t addrs[] = { MM_UART0, MM_UART1 }; | |
175 | char *name = g_strdup_printf("uart%d", i); | |
176 | DeviceState *dev; | |
177 | MemoryRegion *mr; | |
178 | ||
0074fce6 MA |
179 | object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i], |
180 | TYPE_PL011); | |
88052ffd | 181 | dev = DEVICE(&s->lpd.iou.uart[i]); |
b89de436 | 182 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
0074fce6 | 183 | sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); |
b89de436 | 184 | |
88052ffd | 185 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
b89de436 EI |
186 | memory_region_add_subregion(&s->mr_ps, addrs[i], mr); |
187 | ||
88052ffd | 188 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); |
b89de436 EI |
189 | g_free(name); |
190 | } | |
191 | } | |
192 | ||
042d6b02 VG |
193 | static void versal_create_canfds(Versal *s, qemu_irq *pic) |
194 | { | |
195 | int i; | |
196 | uint32_t irqs[] = { VERSAL_CANFD0_IRQ_0, VERSAL_CANFD1_IRQ_0}; | |
197 | uint64_t addrs[] = { MM_CANFD0, MM_CANFD1 }; | |
198 | ||
199 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.canfd); i++) { | |
200 | char *name = g_strdup_printf("canfd%d", i); | |
201 | SysBusDevice *sbd; | |
202 | MemoryRegion *mr; | |
203 | ||
204 | object_initialize_child(OBJECT(s), name, &s->lpd.iou.canfd[i], | |
205 | TYPE_XILINX_CANFD); | |
206 | sbd = SYS_BUS_DEVICE(&s->lpd.iou.canfd[i]); | |
207 | ||
208 | object_property_set_int(OBJECT(&s->lpd.iou.canfd[i]), "ext_clk_freq", | |
209 | XLNX_VERSAL_CANFD_REF_CLK , &error_abort); | |
210 | ||
211 | object_property_set_link(OBJECT(&s->lpd.iou.canfd[i]), "canfdbus", | |
212 | OBJECT(s->lpd.iou.canbus[i]), | |
213 | &error_abort); | |
214 | ||
215 | sysbus_realize(sbd, &error_fatal); | |
216 | ||
217 | mr = sysbus_mmio_get_region(sbd, 0); | |
218 | memory_region_add_subregion(&s->mr_ps, addrs[i], mr); | |
219 | ||
220 | sysbus_connect_irq(sbd, 0, pic[irqs[i]]); | |
221 | g_free(name); | |
222 | } | |
223 | } | |
224 | ||
144677d4 VG |
225 | static void versal_create_usbs(Versal *s, qemu_irq *pic) |
226 | { | |
227 | DeviceState *dev; | |
228 | MemoryRegion *mr; | |
229 | ||
230 | object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb, | |
231 | TYPE_XILINX_VERSAL_USB2); | |
232 | dev = DEVICE(&s->lpd.iou.usb); | |
233 | ||
234 | object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), | |
235 | &error_abort); | |
236 | qdev_prop_set_uint32(dev, "intrs", 1); | |
237 | qdev_prop_set_uint32(dev, "slots", 2); | |
238 | ||
239 | sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); | |
240 | ||
241 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
242 | memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr); | |
243 | ||
244 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); | |
245 | ||
246 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
247 | memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); | |
248 | } | |
249 | ||
b89de436 EI |
250 | static void versal_create_gems(Versal *s, qemu_irq *pic) |
251 | { | |
252 | int i; | |
253 | ||
254 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { | |
255 | static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0}; | |
256 | static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 }; | |
257 | char *name = g_strdup_printf("gem%d", i); | |
258 | NICInfo *nd = &nd_table[i]; | |
259 | DeviceState *dev; | |
260 | MemoryRegion *mr; | |
261 | ||
0074fce6 MA |
262 | object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], |
263 | TYPE_CADENCE_GEM); | |
4bd9b59c | 264 | dev = DEVICE(&s->lpd.iou.gem[i]); |
7ad36e2e | 265 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
b89de436 EI |
266 | if (nd->used) { |
267 | qemu_check_nic_model(nd, "cadence_gem"); | |
268 | qdev_set_nic_properties(dev, nd); | |
269 | } | |
dfc38879 | 270 | object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); |
5325cc34 | 271 | object_property_set_int(OBJECT(dev), "num-priority-queues", 2, |
b89de436 | 272 | &error_abort); |
5325cc34 | 273 | object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), |
b89de436 | 274 | &error_abort); |
0074fce6 | 275 | sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); |
b89de436 | 276 | |
4bd9b59c | 277 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
b89de436 EI |
278 | memory_region_add_subregion(&s->mr_ps, addrs[i], mr); |
279 | ||
4bd9b59c | 280 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); |
b89de436 EI |
281 | g_free(name); |
282 | } | |
283 | } | |
284 | ||
8a218651 EI |
285 | static void versal_create_admas(Versal *s, qemu_irq *pic) |
286 | { | |
287 | int i; | |
288 | ||
289 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { | |
290 | char *name = g_strdup_printf("adma%d", i); | |
291 | DeviceState *dev; | |
292 | MemoryRegion *mr; | |
293 | ||
0074fce6 MA |
294 | object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i], |
295 | TYPE_XLNX_ZDMA); | |
f4e3fa37 | 296 | dev = DEVICE(&s->lpd.iou.adma[i]); |
5325cc34 | 297 | object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort); |
783dbab1 PMD |
298 | object_property_set_link(OBJECT(dev), "dma", |
299 | OBJECT(get_system_memory()), &error_fatal); | |
0074fce6 | 300 | sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); |
8a218651 | 301 | |
f4e3fa37 | 302 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
8a218651 EI |
303 | memory_region_add_subregion(&s->mr_ps, |
304 | MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); | |
305 | ||
f4e3fa37 | 306 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]); |
8a218651 EI |
307 | g_free(name); |
308 | } | |
309 | } | |
310 | ||
724c6e12 EI |
311 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */ |
312 | static void versal_create_sds(Versal *s, qemu_irq *pic) | |
313 | { | |
314 | int i; | |
315 | ||
316 | for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) { | |
317 | DeviceState *dev; | |
318 | MemoryRegion *mr; | |
319 | ||
0074fce6 MA |
320 | object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i], |
321 | TYPE_SYSBUS_SDHCI); | |
724c6e12 EI |
322 | dev = DEVICE(&s->pmc.iou.sd[i]); |
323 | ||
5325cc34 MA |
324 | object_property_set_uint(OBJECT(dev), "sd-spec-version", 3, |
325 | &error_fatal); | |
326 | object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES, | |
724c6e12 | 327 | &error_fatal); |
5325cc34 | 328 | object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal); |
0074fce6 | 329 | sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); |
724c6e12 EI |
330 | |
331 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
332 | memory_region_add_subregion(&s->mr_ps, | |
333 | MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr); | |
334 | ||
335 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | |
336 | pic[VERSAL_SD0_IRQ_0 + i * 2]); | |
337 | } | |
338 | } | |
339 | ||
9a6d4918 FI |
340 | static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic) |
341 | { | |
342 | DeviceState *orgate; | |
343 | ||
344 | /* | |
345 | * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following | |
346 | * models: | |
347 | * - RTC | |
348 | * - BBRAM | |
f7c9aecb | 349 | * - PMC SLCR |
4a0244b4 | 350 | * - CFRAME regs (input 3 - 17 to the orgate) |
9a6d4918 FI |
351 | */ |
352 | object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate", | |
353 | &s->pmc.apb_irq_orgate, TYPE_OR_IRQ); | |
354 | orgate = DEVICE(&s->pmc.apb_irq_orgate); | |
355 | object_property_set_int(OBJECT(orgate), | |
356 | "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal); | |
357 | qdev_realize(orgate, NULL, &error_fatal); | |
358 | qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]); | |
359 | } | |
360 | ||
eb1221c5 EI |
361 | static void versal_create_rtc(Versal *s, qemu_irq *pic) |
362 | { | |
363 | SysBusDevice *sbd; | |
364 | MemoryRegion *mr; | |
365 | ||
5a147c8c MA |
366 | object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc, |
367 | TYPE_XLNX_ZYNQMP_RTC); | |
eb1221c5 | 368 | sbd = SYS_BUS_DEVICE(&s->pmc.rtc); |
7d5b0d68 | 369 | sysbus_realize(sbd, &error_fatal); |
eb1221c5 EI |
370 | |
371 | mr = sysbus_mmio_get_region(sbd, 0); | |
372 | memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr); | |
373 | ||
374 | /* | |
375 | * TODO: Connect the ALARM and SECONDS interrupts once our RTC model | |
376 | * supports them. | |
377 | */ | |
9a6d4918 FI |
378 | sysbus_connect_irq(sbd, 1, |
379 | qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0)); | |
eb1221c5 EI |
380 | } |
381 | ||
3b22376b TH |
382 | static void versal_create_trng(Versal *s, qemu_irq *pic) |
383 | { | |
384 | SysBusDevice *sbd; | |
385 | MemoryRegion *mr; | |
386 | ||
387 | object_initialize_child(OBJECT(s), "trng", &s->pmc.trng, | |
388 | TYPE_XLNX_VERSAL_TRNG); | |
389 | sbd = SYS_BUS_DEVICE(&s->pmc.trng); | |
390 | sysbus_realize(sbd, &error_fatal); | |
391 | ||
392 | mr = sysbus_mmio_get_region(sbd, 0); | |
393 | memory_region_add_subregion(&s->mr_ps, MM_PMC_TRNG, mr); | |
394 | sysbus_connect_irq(sbd, 0, pic[VERSAL_TRNG_IRQ]); | |
395 | } | |
396 | ||
a55b441b EI |
397 | static void versal_create_xrams(Versal *s, qemu_irq *pic) |
398 | { | |
399 | int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl); | |
400 | DeviceState *orgate; | |
401 | int i; | |
402 | ||
403 | /* XRAM IRQs get ORed into a single line. */ | |
404 | object_initialize_child(OBJECT(s), "xram-irq-orgate", | |
405 | &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); | |
406 | orgate = DEVICE(&s->lpd.xram.irq_orgate); | |
407 | object_property_set_int(OBJECT(orgate), | |
408 | "num-lines", nr_xrams, &error_fatal); | |
409 | qdev_realize(orgate, NULL, &error_fatal); | |
410 | qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]); | |
411 | ||
412 | for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) { | |
413 | SysBusDevice *sbd; | |
414 | MemoryRegion *mr; | |
415 | ||
416 | object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i], | |
417 | TYPE_XLNX_XRAM_CTRL); | |
418 | sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]); | |
419 | sysbus_realize(sbd, &error_fatal); | |
420 | ||
421 | mr = sysbus_mmio_get_region(sbd, 0); | |
422 | memory_region_add_subregion(&s->mr_ps, | |
423 | MM_XRAMC + i * MM_XRAMC_SIZE, mr); | |
424 | mr = sysbus_mmio_get_region(sbd, 1); | |
425 | memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr); | |
426 | ||
427 | sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i)); | |
428 | } | |
429 | } | |
430 | ||
393185bc TH |
431 | static void versal_create_bbram(Versal *s, qemu_irq *pic) |
432 | { | |
433 | SysBusDevice *sbd; | |
434 | ||
435 | object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram, | |
436 | sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM, | |
437 | &error_fatal, | |
438 | "crc-zpads", "0", | |
439 | NULL); | |
440 | sbd = SYS_BUS_DEVICE(&s->pmc.bbram); | |
441 | ||
442 | sysbus_realize(sbd, &error_fatal); | |
443 | memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL, | |
444 | sysbus_mmio_get_region(sbd, 0)); | |
9a6d4918 FI |
445 | sysbus_connect_irq(sbd, 0, |
446 | qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1)); | |
393185bc TH |
447 | } |
448 | ||
5f4910ff TH |
449 | static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base) |
450 | { | |
451 | SysBusDevice *part = SYS_BUS_DEVICE(dev); | |
452 | ||
453 | object_property_set_link(OBJECT(part), "efuse", | |
454 | OBJECT(&s->pmc.efuse), &error_abort); | |
455 | ||
456 | sysbus_realize(part, &error_abort); | |
457 | memory_region_add_subregion(&s->mr_ps, base, | |
458 | sysbus_mmio_get_region(part, 0)); | |
459 | } | |
460 | ||
461 | static void versal_create_efuse(Versal *s, qemu_irq *pic) | |
462 | { | |
463 | Object *bits = OBJECT(&s->pmc.efuse); | |
464 | Object *ctrl = OBJECT(&s->pmc.efuse_ctrl); | |
465 | Object *cache = OBJECT(&s->pmc.efuse_cache); | |
466 | ||
467 | object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl, | |
468 | TYPE_XLNX_VERSAL_EFUSE_CTRL); | |
469 | ||
470 | object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache, | |
471 | TYPE_XLNX_VERSAL_EFUSE_CACHE); | |
472 | ||
473 | object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, | |
474 | sizeof(s->pmc.efuse), | |
475 | TYPE_XLNX_EFUSE, &error_abort, | |
476 | "efuse-nr", "3", | |
477 | "efuse-size", "8192", | |
478 | NULL); | |
479 | ||
480 | qdev_realize(DEVICE(bits), NULL, &error_abort); | |
481 | versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL); | |
482 | versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE); | |
483 | ||
484 | sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); | |
485 | } | |
486 | ||
f7c9aecb FI |
487 | static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic) |
488 | { | |
489 | SysBusDevice *sbd; | |
490 | ||
491 | object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, | |
492 | TYPE_XILINX_VERSAL_PMC_IOU_SLCR); | |
493 | ||
494 | sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); | |
495 | sysbus_realize(sbd, &error_fatal); | |
496 | ||
497 | memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR, | |
498 | sysbus_mmio_get_region(sbd, 0)); | |
499 | ||
500 | sysbus_connect_irq(sbd, 0, | |
501 | qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2)); | |
502 | } | |
503 | ||
868d9680 FI |
504 | static void versal_create_ospi(Versal *s, qemu_irq *pic) |
505 | { | |
506 | SysBusDevice *sbd; | |
507 | MemoryRegion *mr_dac; | |
508 | qemu_irq ospi_mux_sel; | |
509 | DeviceState *orgate; | |
510 | ||
511 | memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s), | |
512 | "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE); | |
513 | ||
514 | object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi, | |
515 | TYPE_XILINX_VERSAL_OSPI); | |
516 | ||
517 | mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1); | |
518 | memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac); | |
519 | ||
520 | /* Create the OSPI destination DMA */ | |
521 | object_initialize_child(OBJECT(s), "versal-ospi-dma-dst", | |
522 | &s->pmc.iou.ospi.dma_dst, | |
523 | TYPE_XLNX_CSU_DMA); | |
524 | ||
525 | object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst), | |
526 | "dma", OBJECT(get_system_memory()), | |
527 | &error_abort); | |
528 | ||
529 | sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst); | |
530 | sysbus_realize(sbd, &error_fatal); | |
531 | ||
532 | memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST, | |
533 | sysbus_mmio_get_region(sbd, 0)); | |
534 | ||
535 | /* Create the OSPI source DMA */ | |
536 | object_initialize_child(OBJECT(s), "versal-ospi-dma-src", | |
537 | &s->pmc.iou.ospi.dma_src, | |
538 | TYPE_XLNX_CSU_DMA); | |
539 | ||
540 | object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", | |
541 | false, &error_abort); | |
542 | ||
543 | object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), | |
544 | "dma", OBJECT(mr_dac), &error_abort); | |
545 | ||
546 | object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), | |
547 | "stream-connected-dma", | |
548 | OBJECT(&s->pmc.iou.ospi.dma_dst), | |
549 | &error_abort); | |
550 | ||
551 | sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src); | |
552 | sysbus_realize(sbd, &error_fatal); | |
553 | ||
554 | memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC, | |
555 | sysbus_mmio_get_region(sbd, 0)); | |
556 | ||
557 | /* Realize the OSPI */ | |
558 | object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src", | |
559 | OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort); | |
560 | ||
561 | sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi); | |
562 | sysbus_realize(sbd, &error_fatal); | |
563 | ||
564 | memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI, | |
565 | sysbus_mmio_get_region(sbd, 0)); | |
566 | ||
567 | memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC, | |
568 | &s->pmc.iou.ospi.linear_mr); | |
569 | ||
570 | /* ospi_mux_sel */ | |
571 | ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi), | |
572 | "ospi-mux-sel", 0); | |
573 | qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, | |
574 | ospi_mux_sel); | |
575 | ||
576 | /* OSPI irq */ | |
577 | object_initialize_child(OBJECT(s), "ospi-irq-orgate", | |
578 | &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ); | |
579 | object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate), | |
580 | "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal); | |
581 | ||
582 | orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate); | |
583 | qdev_realize(orgate, NULL, &error_fatal); | |
584 | ||
585 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0, | |
586 | qdev_get_gpio_in(orgate, 0)); | |
587 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0, | |
588 | qdev_get_gpio_in(orgate, 1)); | |
589 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0, | |
590 | qdev_get_gpio_in(orgate, 2)); | |
591 | ||
592 | qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); | |
593 | } | |
594 | ||
b286d08a FI |
595 | static void versal_create_cfu(Versal *s, qemu_irq *pic) |
596 | { | |
597 | SysBusDevice *sbd; | |
4a0244b4 FI |
598 | DeviceState *dev; |
599 | int i; | |
600 | const struct { | |
601 | uint64_t reg_base; | |
602 | uint64_t fdri_base; | |
603 | } cframe_addr[] = { | |
604 | { MM_PMC_CFRAME0_REG, MM_PMC_CFRAME0_FDRI }, | |
605 | { MM_PMC_CFRAME1_REG, MM_PMC_CFRAME1_FDRI }, | |
606 | { MM_PMC_CFRAME2_REG, MM_PMC_CFRAME2_FDRI }, | |
607 | { MM_PMC_CFRAME3_REG, MM_PMC_CFRAME3_FDRI }, | |
608 | { MM_PMC_CFRAME4_REG, MM_PMC_CFRAME4_FDRI }, | |
609 | { MM_PMC_CFRAME5_REG, MM_PMC_CFRAME5_FDRI }, | |
610 | { MM_PMC_CFRAME6_REG, MM_PMC_CFRAME6_FDRI }, | |
611 | { MM_PMC_CFRAME7_REG, MM_PMC_CFRAME7_FDRI }, | |
612 | { MM_PMC_CFRAME8_REG, MM_PMC_CFRAME8_FDRI }, | |
613 | { MM_PMC_CFRAME9_REG, MM_PMC_CFRAME9_FDRI }, | |
614 | { MM_PMC_CFRAME10_REG, MM_PMC_CFRAME10_FDRI }, | |
615 | { MM_PMC_CFRAME11_REG, MM_PMC_CFRAME11_FDRI }, | |
616 | { MM_PMC_CFRAME12_REG, MM_PMC_CFRAME12_FDRI }, | |
617 | { MM_PMC_CFRAME13_REG, MM_PMC_CFRAME13_FDRI }, | |
618 | { MM_PMC_CFRAME14_REG, MM_PMC_CFRAME14_FDRI }, | |
619 | }; | |
620 | const struct { | |
621 | uint32_t blktype0_frames; | |
622 | uint32_t blktype1_frames; | |
623 | uint32_t blktype2_frames; | |
624 | uint32_t blktype3_frames; | |
625 | uint32_t blktype4_frames; | |
626 | uint32_t blktype5_frames; | |
627 | uint32_t blktype6_frames; | |
628 | } cframe_cfg[] = { | |
629 | [0] = { 34111, 3528, 12800, 11, 5, 1, 1 }, | |
630 | [1] = { 38498, 3841, 15361, 13, 7, 3, 1 }, | |
631 | [2] = { 38498, 3841, 15361, 13, 7, 3, 1 }, | |
632 | [3] = { 38498, 3841, 15361, 13, 7, 3, 1 }, | |
633 | }; | |
b286d08a FI |
634 | |
635 | /* CFU FDRO */ | |
636 | object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro, | |
637 | TYPE_XLNX_VERSAL_CFU_FDRO); | |
638 | sbd = SYS_BUS_DEVICE(&s->pmc.cfu_fdro); | |
639 | ||
640 | sysbus_realize(sbd, &error_fatal); | |
641 | memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO, | |
642 | sysbus_mmio_get_region(sbd, 0)); | |
643 | ||
4a0244b4 FI |
644 | /* CFRAME REG */ |
645 | for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { | |
646 | g_autofree char *name = g_strdup_printf("cframe%d", i); | |
647 | ||
648 | object_initialize_child(OBJECT(s), name, &s->pmc.cframe[i], | |
649 | TYPE_XLNX_VERSAL_CFRAME_REG); | |
650 | ||
651 | sbd = SYS_BUS_DEVICE(&s->pmc.cframe[i]); | |
652 | dev = DEVICE(&s->pmc.cframe[i]); | |
653 | ||
654 | if (i < ARRAY_SIZE(cframe_cfg)) { | |
655 | object_property_set_int(OBJECT(dev), "blktype0-frames", | |
656 | cframe_cfg[i].blktype0_frames, | |
657 | &error_abort); | |
658 | object_property_set_int(OBJECT(dev), "blktype1-frames", | |
659 | cframe_cfg[i].blktype1_frames, | |
660 | &error_abort); | |
661 | object_property_set_int(OBJECT(dev), "blktype2-frames", | |
662 | cframe_cfg[i].blktype2_frames, | |
663 | &error_abort); | |
664 | object_property_set_int(OBJECT(dev), "blktype3-frames", | |
665 | cframe_cfg[i].blktype3_frames, | |
666 | &error_abort); | |
667 | object_property_set_int(OBJECT(dev), "blktype4-frames", | |
668 | cframe_cfg[i].blktype4_frames, | |
669 | &error_abort); | |
670 | object_property_set_int(OBJECT(dev), "blktype5-frames", | |
671 | cframe_cfg[i].blktype5_frames, | |
672 | &error_abort); | |
673 | object_property_set_int(OBJECT(dev), "blktype6-frames", | |
674 | cframe_cfg[i].blktype6_frames, | |
675 | &error_abort); | |
676 | } | |
677 | object_property_set_link(OBJECT(dev), "cfu-fdro", | |
678 | OBJECT(&s->pmc.cfu_fdro), &error_fatal); | |
679 | ||
680 | sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); | |
681 | ||
682 | memory_region_add_subregion(&s->mr_ps, cframe_addr[i].reg_base, | |
683 | sysbus_mmio_get_region(sbd, 0)); | |
684 | memory_region_add_subregion(&s->mr_ps, cframe_addr[i].fdri_base, | |
685 | sysbus_mmio_get_region(sbd, 1)); | |
686 | sysbus_connect_irq(sbd, 0, | |
687 | qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), | |
688 | 3 + i)); | |
689 | } | |
690 | ||
691 | /* CFRAME BCAST */ | |
692 | object_initialize_child(OBJECT(s), "cframe_bcast", &s->pmc.cframe_bcast, | |
693 | TYPE_XLNX_VERSAL_CFRAME_BCAST_REG); | |
694 | ||
695 | sbd = SYS_BUS_DEVICE(&s->pmc.cframe_bcast); | |
696 | dev = DEVICE(&s->pmc.cframe_bcast); | |
697 | ||
698 | for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { | |
699 | g_autofree char *propname = g_strdup_printf("cframe%d", i); | |
700 | object_property_set_link(OBJECT(dev), propname, | |
701 | OBJECT(&s->pmc.cframe[i]), &error_fatal); | |
702 | } | |
703 | ||
704 | sysbus_realize(sbd, &error_fatal); | |
705 | ||
706 | memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_REG, | |
707 | sysbus_mmio_get_region(sbd, 0)); | |
708 | memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_FDRI, | |
709 | sysbus_mmio_get_region(sbd, 1)); | |
710 | ||
b286d08a FI |
711 | /* CFU APB */ |
712 | object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb, | |
713 | TYPE_XLNX_VERSAL_CFU_APB); | |
714 | sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb); | |
4a0244b4 FI |
715 | dev = DEVICE(&s->pmc.cfu_apb); |
716 | ||
717 | for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) { | |
718 | g_autofree char *propname = g_strdup_printf("cframe%d", i); | |
719 | object_property_set_link(OBJECT(dev), propname, | |
720 | OBJECT(&s->pmc.cframe[i]), &error_fatal); | |
721 | } | |
b286d08a FI |
722 | |
723 | sysbus_realize(sbd, &error_fatal); | |
724 | memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB, | |
725 | sysbus_mmio_get_region(sbd, 0)); | |
726 | memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM, | |
727 | sysbus_mmio_get_region(sbd, 1)); | |
728 | memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM_2, | |
729 | sysbus_mmio_get_region(sbd, 2)); | |
730 | sysbus_connect_irq(sbd, 0, pic[VERSAL_CFU_IRQ_0]); | |
731 | ||
732 | /* CFU SFR */ | |
733 | object_initialize_child(OBJECT(s), "cfu-sfr", &s->pmc.cfu_sfr, | |
734 | TYPE_XLNX_VERSAL_CFU_SFR); | |
735 | ||
736 | sbd = SYS_BUS_DEVICE(&s->pmc.cfu_sfr); | |
737 | ||
738 | object_property_set_link(OBJECT(&s->pmc.cfu_sfr), | |
739 | "cfu", OBJECT(&s->pmc.cfu_apb), &error_abort); | |
740 | ||
741 | sysbus_realize(sbd, &error_fatal); | |
742 | memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_SFR, | |
743 | sysbus_mmio_get_region(sbd, 0)); | |
744 | } | |
745 | ||
d6ccfc7e EI |
746 | static void versal_create_crl(Versal *s, qemu_irq *pic) |
747 | { | |
748 | SysBusDevice *sbd; | |
749 | int i; | |
750 | ||
751 | object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, | |
752 | TYPE_XLNX_VERSAL_CRL); | |
753 | sbd = SYS_BUS_DEVICE(&s->lpd.crl); | |
754 | ||
755 | for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { | |
756 | g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); | |
757 | ||
758 | object_property_set_link(OBJECT(&s->lpd.crl), | |
759 | name, OBJECT(&s->lpd.rpu.cpu[i]), | |
760 | &error_abort); | |
761 | } | |
762 | ||
763 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { | |
764 | g_autofree gchar *name = g_strdup_printf("gem[%d]", i); | |
765 | ||
766 | object_property_set_link(OBJECT(&s->lpd.crl), | |
767 | name, OBJECT(&s->lpd.iou.gem[i]), | |
768 | &error_abort); | |
769 | } | |
770 | ||
771 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { | |
772 | g_autofree gchar *name = g_strdup_printf("adma[%d]", i); | |
773 | ||
774 | object_property_set_link(OBJECT(&s->lpd.crl), | |
775 | name, OBJECT(&s->lpd.iou.adma[i]), | |
776 | &error_abort); | |
777 | } | |
778 | ||
779 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { | |
780 | g_autofree gchar *name = g_strdup_printf("uart[%d]", i); | |
781 | ||
782 | object_property_set_link(OBJECT(&s->lpd.crl), | |
783 | name, OBJECT(&s->lpd.iou.uart[i]), | |
784 | &error_abort); | |
785 | } | |
786 | ||
787 | object_property_set_link(OBJECT(&s->lpd.crl), | |
788 | "usb", OBJECT(&s->lpd.iou.usb), | |
789 | &error_abort); | |
790 | ||
791 | sysbus_realize(sbd, &error_fatal); | |
792 | memory_region_add_subregion(&s->mr_ps, MM_CRL, | |
793 | sysbus_mmio_get_region(sbd, 0)); | |
794 | sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); | |
795 | } | |
796 | ||
b89de436 EI |
797 | /* This takes the board allocated linear DDR memory and creates aliases |
798 | * for each split DDR range/aperture on the Versal address map. | |
799 | */ | |
800 | static void versal_map_ddr(Versal *s) | |
801 | { | |
802 | uint64_t size = memory_region_size(s->cfg.mr_ddr); | |
803 | /* Describes the various split DDR access regions. */ | |
804 | static const struct { | |
805 | uint64_t base; | |
806 | uint64_t size; | |
807 | } addr_ranges[] = { | |
808 | { MM_TOP_DDR, MM_TOP_DDR_SIZE }, | |
809 | { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, | |
810 | { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, | |
811 | { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } | |
812 | }; | |
813 | uint64_t offset = 0; | |
814 | int i; | |
815 | ||
816 | assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges)); | |
817 | for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { | |
818 | char *name; | |
819 | uint64_t mapsize; | |
820 | ||
821 | mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; | |
822 | name = g_strdup_printf("noc-ddr-range%d", i); | |
823 | /* Create the MR alias. */ | |
824 | memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), | |
825 | name, s->cfg.mr_ddr, | |
826 | offset, mapsize); | |
827 | ||
828 | /* Map it onto the NoC MR. */ | |
829 | memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, | |
830 | &s->noc.mr_ddr_ranges[i]); | |
831 | offset += mapsize; | |
832 | size -= mapsize; | |
833 | g_free(name); | |
834 | } | |
835 | } | |
836 | ||
837 | static void versal_unimp_area(Versal *s, const char *name, | |
838 | MemoryRegion *mr, | |
839 | hwaddr base, hwaddr size) | |
840 | { | |
3e80f690 | 841 | DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); |
b89de436 EI |
842 | MemoryRegion *mr_dev; |
843 | ||
844 | qdev_prop_set_string(dev, "name", name); | |
845 | qdev_prop_set_uint64(dev, "size", size); | |
d2623129 | 846 | object_property_add_child(OBJECT(s), name, OBJECT(dev)); |
3c6ef471 | 847 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
b89de436 EI |
848 | |
849 | mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
850 | memory_region_add_subregion(mr, base, mr_dev); | |
851 | } | |
852 | ||
f7c9aecb FI |
853 | static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level) |
854 | { | |
855 | qemu_log_mask(LOG_UNIMP, | |
856 | "Selecting between enabling SD mode or eMMC mode on " | |
857 | "controller %d is not yet implemented\n", n); | |
858 | } | |
859 | ||
860 | static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level) | |
861 | { | |
862 | qemu_log_mask(LOG_UNIMP, | |
863 | "Selecting between enabling the QSPI or OSPI linear address " | |
864 | "region is not yet implemented\n"); | |
865 | } | |
866 | ||
867 | static void versal_unimp_irq_parity_imr(void *opaque, int n, int level) | |
868 | { | |
869 | qemu_log_mask(LOG_UNIMP, | |
870 | "PMC SLCR parity interrupt behaviour " | |
871 | "is not yet implemented\n"); | |
872 | } | |
873 | ||
b89de436 EI |
874 | static void versal_unimp(Versal *s) |
875 | { | |
f7c9aecb FI |
876 | qemu_irq gpio_in; |
877 | ||
b89de436 EI |
878 | versal_unimp_area(s, "psm", &s->mr_ps, |
879 | MM_PSM_START, MM_PSM_END - MM_PSM_START); | |
b89de436 EI |
880 | versal_unimp_area(s, "crf", &s->mr_ps, |
881 | MM_FPD_CRF, MM_FPD_CRF_SIZE); | |
9a0fcb7f TH |
882 | versal_unimp_area(s, "apu", &s->mr_ps, |
883 | MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE); | |
f0138990 EI |
884 | versal_unimp_area(s, "crp", &s->mr_ps, |
885 | MM_PMC_CRP, MM_PMC_CRP_SIZE); | |
b89de436 EI |
886 | versal_unimp_area(s, "iou-scntr", &s->mr_ps, |
887 | MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); | |
888 | versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, | |
889 | MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); | |
f7c9aecb FI |
890 | |
891 | qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel, | |
892 | "sd-emmc-sel-dummy", 2); | |
893 | qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel, | |
894 | "qspi-ospi-mux-sel-dummy", 1); | |
895 | qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr, | |
896 | "irq-parity-imr-dummy", 1); | |
897 | ||
898 | gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 0); | |
899 | qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, | |
900 | gpio_in); | |
901 | ||
902 | gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 1); | |
903 | qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, | |
904 | gpio_in); | |
905 | ||
906 | gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0); | |
907 | qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), | |
908 | "qspi-ospi-mux-sel", 0, | |
909 | gpio_in); | |
910 | ||
911 | gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0); | |
912 | qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), | |
913 | SYSBUS_DEVICE_GPIO_IRQ, 0, | |
914 | gpio_in); | |
b89de436 EI |
915 | } |
916 | ||
917 | static void versal_realize(DeviceState *dev, Error **errp) | |
918 | { | |
919 | Versal *s = XLNX_VERSAL(dev); | |
920 | qemu_irq pic[XLNX_VERSAL_NR_IRQS]; | |
921 | ||
922 | versal_create_apu_cpus(s); | |
923 | versal_create_apu_gic(s, pic); | |
67a645a3 | 924 | versal_create_rpu_cpus(s); |
b89de436 | 925 | versal_create_uarts(s, pic); |
042d6b02 | 926 | versal_create_canfds(s, pic); |
144677d4 | 927 | versal_create_usbs(s, pic); |
b89de436 | 928 | versal_create_gems(s, pic); |
8a218651 | 929 | versal_create_admas(s, pic); |
724c6e12 | 930 | versal_create_sds(s, pic); |
9a6d4918 | 931 | versal_create_pmc_apb_irq_orgate(s, pic); |
eb1221c5 | 932 | versal_create_rtc(s, pic); |
3b22376b | 933 | versal_create_trng(s, pic); |
a55b441b | 934 | versal_create_xrams(s, pic); |
393185bc | 935 | versal_create_bbram(s, pic); |
5f4910ff | 936 | versal_create_efuse(s, pic); |
f7c9aecb | 937 | versal_create_pmc_iou_slcr(s, pic); |
868d9680 | 938 | versal_create_ospi(s, pic); |
d6ccfc7e | 939 | versal_create_crl(s, pic); |
b286d08a | 940 | versal_create_cfu(s, pic); |
b89de436 EI |
941 | versal_map_ddr(s); |
942 | versal_unimp(s); | |
943 | ||
944 | /* Create the On Chip Memory (OCM). */ | |
945 | memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", | |
946 | MM_OCM_SIZE, &error_fatal); | |
947 | ||
948 | memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); | |
949 | memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); | |
67a645a3 EI |
950 | memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, |
951 | &s->lpd.rpu.mr_ps_alias, 0); | |
b89de436 EI |
952 | } |
953 | ||
954 | static void versal_init(Object *obj) | |
955 | { | |
956 | Versal *s = XLNX_VERSAL(obj); | |
957 | ||
958 | memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); | |
67a645a3 | 959 | memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); |
b89de436 | 960 | memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); |
67a645a3 EI |
961 | memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), |
962 | "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); | |
b89de436 EI |
963 | } |
964 | ||
965 | static Property versal_properties[] = { | |
966 | DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, | |
967 | MemoryRegion *), | |
042d6b02 VG |
968 | DEFINE_PROP_LINK("canbus0", Versal, lpd.iou.canbus[0], |
969 | TYPE_CAN_BUS, CanBusState *), | |
970 | DEFINE_PROP_LINK("canbus1", Versal, lpd.iou.canbus[1], | |
971 | TYPE_CAN_BUS, CanBusState *), | |
b89de436 EI |
972 | DEFINE_PROP_END_OF_LIST() |
973 | }; | |
974 | ||
975 | static void versal_class_init(ObjectClass *klass, void *data) | |
976 | { | |
977 | DeviceClass *dc = DEVICE_CLASS(klass); | |
978 | ||
979 | dc->realize = versal_realize; | |
4f67d30b | 980 | device_class_set_props(dc, versal_properties); |
b89de436 EI |
981 | /* No VMSD since we haven't got any top-level SoC state to save. */ |
982 | } | |
983 | ||
984 | static const TypeInfo versal_info = { | |
985 | .name = TYPE_XLNX_VERSAL, | |
986 | .parent = TYPE_SYS_BUS_DEVICE, | |
987 | .instance_size = sizeof(Versal), | |
988 | .instance_init = versal_init, | |
989 | .class_init = versal_class_init, | |
990 | }; | |
991 | ||
992 | static void versal_register_types(void) | |
993 | { | |
994 | type_register_static(&versal_info); | |
995 | } | |
996 | ||
997 | type_init(versal_register_types); |