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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
b6a0aa05 | 24 | #include "qemu/osdep.h" |
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a PB |
26 | #include "hw/i386/pc.h" |
27 | #include "hw/char/serial.h" | |
28 | #include "hw/i386/apic.h" | |
54a40293 EH |
29 | #include "hw/i386/topology.h" |
30 | #include "sysemu/cpus.h" | |
0d09e41a | 31 | #include "hw/block/fdc.h" |
83c9f4ca PB |
32 | #include "hw/ide.h" |
33 | #include "hw/pci/pci.h" | |
2118196b | 34 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
35 | #include "hw/nvram/fw_cfg.h" |
36 | #include "hw/timer/hpet.h" | |
60d8f328 | 37 | #include "hw/smbios/smbios.h" |
83c9f4ca | 38 | #include "hw/loader.h" |
ca20cf32 | 39 | #include "elf.h" |
47b43a1f | 40 | #include "multiboot.h" |
0d09e41a PB |
41 | #include "hw/timer/mc146818rtc.h" |
42 | #include "hw/timer/i8254.h" | |
43 | #include "hw/audio/pcspk.h" | |
83c9f4ca PB |
44 | #include "hw/pci/msi.h" |
45 | #include "hw/sysbus.h" | |
9c17d615 | 46 | #include "sysemu/sysemu.h" |
e35704ba | 47 | #include "sysemu/numa.h" |
9c17d615 | 48 | #include "sysemu/kvm.h" |
b1c12027 | 49 | #include "sysemu/qtest.h" |
1d31f66b | 50 | #include "kvm_i386.h" |
0d09e41a | 51 | #include "hw/xen/xen.h" |
4be74634 | 52 | #include "sysemu/block-backend.h" |
0d09e41a | 53 | #include "hw/block/block.h" |
a19cbfb3 | 54 | #include "ui/qemu-spice.h" |
022c62cb PB |
55 | #include "exec/memory.h" |
56 | #include "exec/address-spaces.h" | |
9c17d615 | 57 | #include "sysemu/arch_init.h" |
1de7afc9 | 58 | #include "qemu/bitmap.h" |
0c764a9d | 59 | #include "qemu/config-file.h" |
d49b6836 | 60 | #include "qemu/error-report.h" |
0445259b | 61 | #include "hw/acpi/acpi.h" |
5ff020b7 | 62 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 63 | #include "hw/boards.h" |
39848901 | 64 | #include "hw/pci/pci_host.h" |
72c194f7 | 65 | #include "acpi-build.h" |
95bee274 | 66 | #include "hw/mem/pc-dimm.h" |
bf1e8939 | 67 | #include "qapi/visitor.h" |
d1048bef | 68 | #include "qapi-visit.h" |
15eafc2e | 69 | #include "qom/cpu.h" |
1255166b | 70 | #include "hw/nmi.h" |
60c5e104 | 71 | #include "hw/i386/intel_iommu.h" |
80cabfad | 72 | |
471fd342 BS |
73 | /* debug PC/ISA interrupts */ |
74 | //#define DEBUG_IRQ | |
75 | ||
76 | #ifdef DEBUG_IRQ | |
77 | #define DPRINTF(fmt, ...) \ | |
78 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
79 | #else | |
80 | #define DPRINTF(fmt, ...) | |
81 | #endif | |
82 | ||
8a92ea2f | 83 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 84 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 85 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 86 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 87 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 88 | |
4c5b10b7 JS |
89 | #define E820_NR_ENTRIES 16 |
90 | ||
91 | struct e820_entry { | |
92 | uint64_t address; | |
93 | uint64_t length; | |
94 | uint32_t type; | |
541dc0d4 | 95 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
96 | |
97 | struct e820_table { | |
98 | uint32_t count; | |
99 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 100 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 | 101 | |
7d67110f GH |
102 | static struct e820_table e820_reserve; |
103 | static struct e820_entry *e820_table; | |
104 | static unsigned e820_entries; | |
dd703b99 | 105 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 106 | |
b881fbe9 | 107 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 108 | { |
b881fbe9 | 109 | GSIState *s = opaque; |
1452411b | 110 | |
b881fbe9 JK |
111 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
112 | if (n < ISA_NUM_IRQS) { | |
113 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 114 | } |
b881fbe9 | 115 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 116 | } |
1452411b | 117 | |
258711c6 JG |
118 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
119 | unsigned size) | |
80cabfad FB |
120 | { |
121 | } | |
122 | ||
c02e1eac JG |
123 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
124 | { | |
a6fc23e5 | 125 | return 0xffffffffffffffffULL; |
c02e1eac JG |
126 | } |
127 | ||
f929aad6 | 128 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 129 | static qemu_irq ferr_irq; |
8e78eb28 IY |
130 | |
131 | void pc_register_ferr_irq(qemu_irq irq) | |
132 | { | |
133 | ferr_irq = irq; | |
134 | } | |
135 | ||
f929aad6 FB |
136 | /* XXX: add IGNNE support */ |
137 | void cpu_set_ferr(CPUX86State *s) | |
138 | { | |
d537cf6c | 139 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
140 | } |
141 | ||
258711c6 JG |
142 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
143 | unsigned size) | |
f929aad6 | 144 | { |
d537cf6c | 145 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
146 | } |
147 | ||
c02e1eac JG |
148 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
149 | { | |
a6fc23e5 | 150 | return 0xffffffffffffffffULL; |
c02e1eac JG |
151 | } |
152 | ||
28ab0e2e | 153 | /* TSC handling */ |
28ab0e2e FB |
154 | uint64_t cpu_get_tsc(CPUX86State *env) |
155 | { | |
4a1418e0 | 156 | return cpu_get_ticks(); |
28ab0e2e FB |
157 | } |
158 | ||
3de388f6 | 159 | /* IRQ handling */ |
4a8fa5dc | 160 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 161 | { |
02e51483 | 162 | X86CPU *cpu = x86_env_get_cpu(env); |
3de388f6 FB |
163 | int intno; |
164 | ||
bb93e099 WL |
165 | if (!kvm_irqchip_in_kernel()) { |
166 | intno = apic_get_interrupt(cpu->apic_state); | |
167 | if (intno >= 0) { | |
168 | return intno; | |
169 | } | |
170 | /* read the irq from the PIC */ | |
171 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
172 | return -1; | |
173 | } | |
cf6d64bf | 174 | } |
0e21e12b | 175 | |
3de388f6 FB |
176 | intno = pic_read_irq(isa_pic); |
177 | return intno; | |
178 | } | |
179 | ||
d537cf6c | 180 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 181 | { |
182735ef AF |
182 | CPUState *cs = first_cpu; |
183 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 184 | |
471fd342 | 185 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
bb93e099 | 186 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { |
bdc44640 | 187 | CPU_FOREACH(cs) { |
182735ef | 188 | cpu = X86_CPU(cs); |
02e51483 CF |
189 | if (apic_accept_pic_intr(cpu->apic_state)) { |
190 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 191 | } |
d5529471 AJ |
192 | } |
193 | } else { | |
d8ed887b | 194 | if (level) { |
c3affe56 | 195 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
196 | } else { |
197 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
198 | } | |
a5b38b51 | 199 | } |
3de388f6 FB |
200 | } |
201 | ||
b0a21b53 FB |
202 | /* PC cmos mappings */ |
203 | ||
80cabfad FB |
204 | #define REG_EQUIPMENT_BYTE 0x14 |
205 | ||
bda05509 | 206 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
207 | { |
208 | int val; | |
209 | ||
210 | switch (fd0) { | |
2da44dd0 | 211 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
212 | /* 1.44 Mb 3"5 drive */ |
213 | val = 4; | |
214 | break; | |
2da44dd0 | 215 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
216 | /* 2.88 Mb 3"5 drive */ |
217 | val = 5; | |
218 | break; | |
2da44dd0 | 219 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
220 | /* 1.2 Mb 5"5 drive */ |
221 | val = 2; | |
222 | break; | |
2da44dd0 | 223 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
224 | default: |
225 | val = 0; | |
226 | break; | |
227 | } | |
228 | return val; | |
229 | } | |
230 | ||
9139046c MA |
231 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
232 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 233 | { |
ba6c2377 FB |
234 | rtc_set_memory(s, type_ofs, 47); |
235 | rtc_set_memory(s, info_ofs, cylinders); | |
236 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
237 | rtc_set_memory(s, info_ofs + 2, heads); | |
238 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
239 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
240 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
241 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
242 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
243 | rtc_set_memory(s, info_ofs + 8, sectors); | |
244 | } | |
245 | ||
6ac0e82d AZ |
246 | /* convert boot_device letter to something recognizable by the bios */ |
247 | static int boot_device2nibble(char boot_device) | |
248 | { | |
249 | switch(boot_device) { | |
250 | case 'a': | |
251 | case 'b': | |
252 | return 0x01; /* floppy boot */ | |
253 | case 'c': | |
254 | return 0x02; /* hard drive boot */ | |
255 | case 'd': | |
256 | return 0x03; /* CD-ROM boot */ | |
257 | case 'n': | |
258 | return 0x04; /* Network boot */ | |
259 | } | |
260 | return 0; | |
261 | } | |
262 | ||
ddcd5531 | 263 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
264 | { |
265 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
266 | int nbds, bds[3] = { 0, }; |
267 | int i; | |
268 | ||
269 | nbds = strlen(boot_device); | |
270 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
271 | error_setg(errp, "Too many boot devices for PC"); |
272 | return; | |
0ecdffbb AJ |
273 | } |
274 | for (i = 0; i < nbds; i++) { | |
275 | bds[i] = boot_device2nibble(boot_device[i]); | |
276 | if (bds[i] == 0) { | |
ddcd5531 GA |
277 | error_setg(errp, "Invalid boot device for PC: '%c'", |
278 | boot_device[i]); | |
279 | return; | |
0ecdffbb AJ |
280 | } |
281 | } | |
282 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 283 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
284 | } |
285 | ||
ddcd5531 | 286 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 287 | { |
ddcd5531 | 288 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
289 | } |
290 | ||
7444ca4e LE |
291 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
292 | { | |
293 | int val, nb, i; | |
2da44dd0 JS |
294 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
295 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
296 | |
297 | /* floppy type */ | |
298 | if (floppy) { | |
299 | for (i = 0; i < 2; i++) { | |
300 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
301 | } | |
302 | } | |
303 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
304 | cmos_get_fd_drive_type(fd_type[1]); | |
305 | rtc_set_memory(rtc_state, 0x10, val); | |
306 | ||
307 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
308 | nb = 0; | |
2da44dd0 | 309 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
310 | nb++; |
311 | } | |
2da44dd0 | 312 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
313 | nb++; |
314 | } | |
315 | switch (nb) { | |
316 | case 0: | |
317 | break; | |
318 | case 1: | |
319 | val |= 0x01; /* 1 drive, ready for boot */ | |
320 | break; | |
321 | case 2: | |
322 | val |= 0x41; /* 2 drives, ready for boot */ | |
323 | break; | |
324 | } | |
325 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
326 | } | |
327 | ||
c0897e0c MA |
328 | typedef struct pc_cmos_init_late_arg { |
329 | ISADevice *rtc_state; | |
9139046c | 330 | BusState *idebus[2]; |
c0897e0c MA |
331 | } pc_cmos_init_late_arg; |
332 | ||
b86f4613 LE |
333 | typedef struct check_fdc_state { |
334 | ISADevice *floppy; | |
335 | bool multiple; | |
336 | } CheckFdcState; | |
337 | ||
338 | static int check_fdc(Object *obj, void *opaque) | |
339 | { | |
340 | CheckFdcState *state = opaque; | |
341 | Object *fdc; | |
342 | uint32_t iobase; | |
343 | Error *local_err = NULL; | |
344 | ||
345 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
346 | if (!fdc) { | |
347 | return 0; | |
348 | } | |
349 | ||
350 | iobase = object_property_get_int(obj, "iobase", &local_err); | |
351 | if (local_err || iobase != 0x3f0) { | |
352 | error_free(local_err); | |
353 | return 0; | |
354 | } | |
355 | ||
356 | if (state->floppy) { | |
357 | state->multiple = true; | |
358 | } else { | |
359 | state->floppy = ISA_DEVICE(obj); | |
360 | } | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static const char * const fdc_container_path[] = { | |
365 | "/unattached", "/peripheral", "/peripheral-anon" | |
366 | }; | |
367 | ||
424e4a87 RK |
368 | /* |
369 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
370 | * and ACPI objects. | |
371 | */ | |
372 | ISADevice *pc_find_fdc0(void) | |
373 | { | |
374 | int i; | |
375 | Object *container; | |
376 | CheckFdcState state = { 0 }; | |
377 | ||
378 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
379 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
380 | object_child_foreach(container, check_fdc, &state); | |
381 | } | |
382 | ||
383 | if (state.multiple) { | |
384 | error_report("warning: multiple floppy disk controllers with " | |
433672b0 MA |
385 | "iobase=0x3f0 have been found"); |
386 | error_printf("the one being picked for CMOS setup might not reflect " | |
7ea7d36e | 387 | "your intent\n"); |
424e4a87 RK |
388 | } |
389 | ||
390 | return state.floppy; | |
391 | } | |
392 | ||
c0897e0c MA |
393 | static void pc_cmos_init_late(void *opaque) |
394 | { | |
395 | pc_cmos_init_late_arg *arg = opaque; | |
396 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
397 | int16_t cylinders; |
398 | int8_t heads, sectors; | |
c0897e0c | 399 | int val; |
2adc99b2 | 400 | int i, trans; |
c0897e0c | 401 | |
9139046c MA |
402 | val = 0; |
403 | if (ide_get_geometry(arg->idebus[0], 0, | |
404 | &cylinders, &heads, §ors) >= 0) { | |
405 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
406 | val |= 0xf0; | |
407 | } | |
408 | if (ide_get_geometry(arg->idebus[0], 1, | |
409 | &cylinders, &heads, §ors) >= 0) { | |
410 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
411 | val |= 0x0f; | |
412 | } | |
413 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
414 | |
415 | val = 0; | |
416 | for (i = 0; i < 4; i++) { | |
9139046c MA |
417 | /* NOTE: ide_get_geometry() returns the physical |
418 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
419 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
420 | geometry can be different if a translation is done. */ | |
421 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
422 | &cylinders, &heads, §ors) >= 0) { | |
2adc99b2 MA |
423 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
424 | assert((trans & ~3) == 0); | |
425 | val |= trans << (i * 2); | |
c0897e0c MA |
426 | } |
427 | } | |
428 | rtc_set_memory(s, 0x39, val); | |
429 | ||
424e4a87 | 430 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 431 | |
c0897e0c MA |
432 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
433 | } | |
434 | ||
23d30407 | 435 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 436 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 437 | ISADevice *s) |
80cabfad | 438 | { |
7444ca4e | 439 | int val; |
c0897e0c | 440 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 441 | |
b0a21b53 | 442 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
443 | |
444 | /* memory size */ | |
e89001f7 | 445 | /* base memory (first MiB) */ |
88076854 | 446 | val = MIN(pcms->below_4g_mem_size / 1024, 640); |
333190eb FB |
447 | rtc_set_memory(s, 0x15, val); |
448 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 449 | /* extended memory (next 64MiB) */ |
88076854 EH |
450 | if (pcms->below_4g_mem_size > 1024 * 1024) { |
451 | val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; | |
e89001f7 MA |
452 | } else { |
453 | val = 0; | |
454 | } | |
80cabfad FB |
455 | if (val > 65535) |
456 | val = 65535; | |
b0a21b53 FB |
457 | rtc_set_memory(s, 0x17, val); |
458 | rtc_set_memory(s, 0x18, val >> 8); | |
459 | rtc_set_memory(s, 0x30, val); | |
460 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 461 | /* memory between 16MiB and 4GiB */ |
88076854 EH |
462 | if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { |
463 | val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; | |
e89001f7 | 464 | } else { |
9da98861 | 465 | val = 0; |
e89001f7 | 466 | } |
80cabfad FB |
467 | if (val > 65535) |
468 | val = 65535; | |
b0a21b53 FB |
469 | rtc_set_memory(s, 0x34, val); |
470 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 471 | /* memory above 4GiB */ |
88076854 | 472 | val = pcms->above_4g_mem_size / 65536; |
e89001f7 MA |
473 | rtc_set_memory(s, 0x5b, val); |
474 | rtc_set_memory(s, 0x5c, val >> 8); | |
475 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 476 | |
23d30407 | 477 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 478 | TYPE_ISA_DEVICE, |
ec68007a | 479 | (Object **)&pcms->rtc, |
2d996150 GZ |
480 | object_property_allow_set_link, |
481 | OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); | |
23d30407 | 482 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 483 | "rtc_state", &error_abort); |
298e01b6 | 484 | |
007b0657 | 485 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 486 | |
b0a21b53 | 487 | val = 0; |
b0a21b53 FB |
488 | val |= 0x02; /* FPU is there */ |
489 | val |= 0x04; /* PS/2 mouse installed */ | |
490 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
491 | ||
b86f4613 | 492 | /* hard drives and FDC */ |
c0897e0c | 493 | arg.rtc_state = s; |
9139046c MA |
494 | arg.idebus[0] = idebus0; |
495 | arg.idebus[1] = idebus1; | |
c0897e0c | 496 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
497 | } |
498 | ||
a0881c64 AF |
499 | #define TYPE_PORT92 "port92" |
500 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
501 | ||
4b78a802 BS |
502 | /* port 92 stuff: could be split off */ |
503 | typedef struct Port92State { | |
a0881c64 AF |
504 | ISADevice parent_obj; |
505 | ||
23af670e | 506 | MemoryRegion io; |
4b78a802 | 507 | uint8_t outport; |
d812b3d6 | 508 | qemu_irq a20_out; |
4b78a802 BS |
509 | } Port92State; |
510 | ||
93ef4192 AG |
511 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
512 | unsigned size) | |
4b78a802 BS |
513 | { |
514 | Port92State *s = opaque; | |
4700a316 | 515 | int oldval = s->outport; |
4b78a802 | 516 | |
c5539cb4 | 517 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 | 518 | s->outport = val; |
d812b3d6 | 519 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
4700a316 | 520 | if ((val & 1) && !(oldval & 1)) { |
4b78a802 BS |
521 | qemu_system_reset_request(); |
522 | } | |
523 | } | |
524 | ||
93ef4192 AG |
525 | static uint64_t port92_read(void *opaque, hwaddr addr, |
526 | unsigned size) | |
4b78a802 BS |
527 | { |
528 | Port92State *s = opaque; | |
529 | uint32_t ret; | |
530 | ||
531 | ret = s->outport; | |
532 | DPRINTF("port92: read 0x%02x\n", ret); | |
533 | return ret; | |
534 | } | |
535 | ||
d80fe99d | 536 | static void port92_init(ISADevice *dev, qemu_irq a20_out) |
4b78a802 | 537 | { |
d80fe99d | 538 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); |
4b78a802 BS |
539 | } |
540 | ||
541 | static const VMStateDescription vmstate_port92_isa = { | |
542 | .name = "port92", | |
543 | .version_id = 1, | |
544 | .minimum_version_id = 1, | |
d49805ae | 545 | .fields = (VMStateField[]) { |
4b78a802 BS |
546 | VMSTATE_UINT8(outport, Port92State), |
547 | VMSTATE_END_OF_LIST() | |
548 | } | |
549 | }; | |
550 | ||
551 | static void port92_reset(DeviceState *d) | |
552 | { | |
a0881c64 | 553 | Port92State *s = PORT92(d); |
4b78a802 BS |
554 | |
555 | s->outport &= ~1; | |
556 | } | |
557 | ||
23af670e | 558 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
559 | .read = port92_read, |
560 | .write = port92_write, | |
561 | .impl = { | |
562 | .min_access_size = 1, | |
563 | .max_access_size = 1, | |
564 | }, | |
565 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
566 | }; |
567 | ||
db895a1e | 568 | static void port92_initfn(Object *obj) |
4b78a802 | 569 | { |
db895a1e | 570 | Port92State *s = PORT92(obj); |
4b78a802 | 571 | |
1437c94b | 572 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 573 | |
4b78a802 | 574 | s->outport = 0; |
d812b3d6 EV |
575 | |
576 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
db895a1e AF |
577 | } |
578 | ||
579 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
580 | { | |
581 | ISADevice *isadev = ISA_DEVICE(dev); | |
582 | Port92State *s = PORT92(dev); | |
583 | ||
584 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
585 | } |
586 | ||
8f04ee08 AL |
587 | static void port92_class_initfn(ObjectClass *klass, void *data) |
588 | { | |
39bffca2 | 589 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 590 | |
db895a1e | 591 | dc->realize = port92_realizefn; |
39bffca2 AL |
592 | dc->reset = port92_reset; |
593 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
594 | /* |
595 | * Reason: unlike ordinary ISA devices, this one needs additional | |
596 | * wiring: its A20 output line needs to be wired up by | |
597 | * port92_init(). | |
598 | */ | |
599 | dc->cannot_instantiate_with_device_add_yet = true; | |
8f04ee08 AL |
600 | } |
601 | ||
8c43a6f0 | 602 | static const TypeInfo port92_info = { |
a0881c64 | 603 | .name = TYPE_PORT92, |
39bffca2 AL |
604 | .parent = TYPE_ISA_DEVICE, |
605 | .instance_size = sizeof(Port92State), | |
db895a1e | 606 | .instance_init = port92_initfn, |
39bffca2 | 607 | .class_init = port92_class_initfn, |
4b78a802 BS |
608 | }; |
609 | ||
83f7d43a | 610 | static void port92_register_types(void) |
4b78a802 | 611 | { |
39bffca2 | 612 | type_register_static(&port92_info); |
4b78a802 | 613 | } |
83f7d43a AF |
614 | |
615 | type_init(port92_register_types) | |
4b78a802 | 616 | |
956a3e6b | 617 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 618 | { |
cc36a7a2 | 619 | X86CPU *cpu = opaque; |
e1a23744 | 620 | |
956a3e6b | 621 | /* XXX: send to all CPUs ? */ |
4b78a802 | 622 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 623 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
624 | } |
625 | ||
4c5b10b7 JS |
626 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
627 | { | |
7d67110f | 628 | int index = le32_to_cpu(e820_reserve.count); |
4c5b10b7 JS |
629 | struct e820_entry *entry; |
630 | ||
7d67110f GH |
631 | if (type != E820_RAM) { |
632 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
633 | if (index >= E820_NR_ENTRIES) { | |
634 | return -EBUSY; | |
635 | } | |
636 | entry = &e820_reserve.entry[index++]; | |
637 | ||
638 | entry->address = cpu_to_le64(address); | |
639 | entry->length = cpu_to_le64(length); | |
640 | entry->type = cpu_to_le32(type); | |
641 | ||
642 | e820_reserve.count = cpu_to_le32(index); | |
643 | } | |
4c5b10b7 | 644 | |
7d67110f | 645 | /* new "etc/e820" file -- include ram too */ |
ab3ad07f | 646 | e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); |
7d67110f GH |
647 | e820_table[e820_entries].address = cpu_to_le64(address); |
648 | e820_table[e820_entries].length = cpu_to_le64(length); | |
649 | e820_table[e820_entries].type = cpu_to_le32(type); | |
650 | e820_entries++; | |
4c5b10b7 | 651 | |
7d67110f | 652 | return e820_entries; |
4c5b10b7 JS |
653 | } |
654 | ||
7bf8ef19 GS |
655 | int e820_get_num_entries(void) |
656 | { | |
657 | return e820_entries; | |
658 | } | |
659 | ||
660 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
661 | { | |
662 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
663 | *address = le64_to_cpu(e820_table[idx].address); | |
664 | *length = le64_to_cpu(e820_table[idx].length); | |
665 | return true; | |
666 | } | |
667 | return false; | |
668 | } | |
669 | ||
54a40293 EH |
670 | /* Enables contiguous-apic-ID mode, for compatibility */ |
671 | static bool compat_apic_id_mode; | |
672 | ||
673 | void enable_compat_apic_id_mode(void) | |
674 | { | |
675 | compat_apic_id_mode = true; | |
676 | } | |
677 | ||
678 | /* Calculates initial APIC ID for a specific CPU index | |
679 | * | |
680 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
681 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
682 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
683 | * all CPUs up to max_cpus. | |
684 | */ | |
685 | static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) | |
686 | { | |
687 | uint32_t correct_id; | |
688 | static bool warned; | |
689 | ||
690 | correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); | |
691 | if (compat_apic_id_mode) { | |
b1c12027 | 692 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { |
54a40293 EH |
693 | error_report("APIC IDs set in compatibility mode, " |
694 | "CPU topology won't match the configuration"); | |
695 | warned = true; | |
696 | } | |
697 | return cpu_index; | |
698 | } else { | |
699 | return correct_id; | |
700 | } | |
701 | } | |
702 | ||
5fd0a9d4 | 703 | static void pc_build_smbios(FWCfgState *fw_cfg) |
80cabfad | 704 | { |
c97294ec GS |
705 | uint8_t *smbios_tables, *smbios_anchor; |
706 | size_t smbios_tables_len, smbios_anchor_len; | |
89cc4a27 WH |
707 | struct smbios_phys_mem_area *mem_array; |
708 | unsigned i, array_count; | |
5fd0a9d4 WH |
709 | |
710 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len); | |
711 | if (smbios_tables) { | |
712 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
713 | smbios_tables, smbios_tables_len); | |
714 | } | |
715 | ||
89cc4a27 WH |
716 | /* build the array of physical mem area from e820 table */ |
717 | mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); | |
718 | for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { | |
719 | uint64_t addr, len; | |
720 | ||
721 | if (e820_get_entry(i, E820_RAM, &addr, &len)) { | |
722 | mem_array[array_count].address = addr; | |
723 | mem_array[array_count].length = len; | |
724 | array_count++; | |
725 | } | |
726 | } | |
727 | smbios_get_tables(mem_array, array_count, | |
728 | &smbios_tables, &smbios_tables_len, | |
5fd0a9d4 | 729 | &smbios_anchor, &smbios_anchor_len); |
89cc4a27 WH |
730 | g_free(mem_array); |
731 | ||
5fd0a9d4 WH |
732 | if (smbios_anchor) { |
733 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", | |
734 | smbios_tables, smbios_tables_len); | |
735 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", | |
736 | smbios_anchor, smbios_anchor_len); | |
737 | } | |
738 | } | |
739 | ||
ebde2465 | 740 | static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) |
5fd0a9d4 WH |
741 | { |
742 | FWCfgState *fw_cfg; | |
11c2fd3e AL |
743 | uint64_t *numa_fw_cfg; |
744 | int i, j; | |
3cce6243 | 745 | |
305ae888 | 746 | fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); |
5836d168 | 747 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
c886fc4c | 748 | |
1d934e89 EH |
749 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
750 | * | |
a3abd0f2 IM |
751 | * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for |
752 | * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, | |
753 | * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface | |
754 | * for CPU hotplug also uses APIC ID and not "CPU index". | |
755 | * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", | |
756 | * but the "limit to the APIC ID values SeaBIOS may see". | |
1d934e89 | 757 | * |
a3abd0f2 IM |
758 | * So for compatibility reasons with old BIOSes we are stuck with |
759 | * "etc/max-cpus" actually being apic_id_limit | |
1d934e89 | 760 | */ |
ebde2465 | 761 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); |
905fdcb5 | 762 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
089da572 MA |
763 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
764 | acpi_tables, acpi_tables_len); | |
9b5b76d4 | 765 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 | 766 | |
089da572 | 767 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, |
7d67110f GH |
768 | &e820_reserve, sizeof(e820_reserve)); |
769 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
770 | sizeof(struct e820_entry) * e820_entries); | |
11c2fd3e | 771 | |
089da572 | 772 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); |
11c2fd3e AL |
773 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
774 | * of nodes, one word for each VCPU->node and one word for each node to | |
775 | * hold the amount of memory. | |
776 | */ | |
ebde2465 | 777 | numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); |
11c2fd3e | 778 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 779 | for (i = 0; i < max_cpus; i++) { |
1d934e89 | 780 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); |
ebde2465 | 781 | assert(apic_id < pcms->apic_id_limit); |
6bea1ddf IM |
782 | j = numa_get_node_for_cpu(i); |
783 | if (j < nb_numa_nodes) { | |
784 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); | |
11c2fd3e AL |
785 | } |
786 | } | |
787 | for (i = 0; i < nb_numa_nodes; i++) { | |
ebde2465 IM |
788 | numa_fw_cfg[pcms->apic_id_limit + 1 + i] = |
789 | cpu_to_le64(numa_info[i].node_mem); | |
11c2fd3e | 790 | } |
089da572 | 791 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
ebde2465 | 792 | (1 + pcms->apic_id_limit + nb_numa_nodes) * |
1d934e89 | 793 | sizeof(*numa_fw_cfg)); |
bf483392 AG |
794 | |
795 | return fw_cfg; | |
80cabfad FB |
796 | } |
797 | ||
642a4f96 TS |
798 | static long get_file_size(FILE *f) |
799 | { | |
800 | long where, size; | |
801 | ||
802 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
803 | ||
804 | where = ftell(f); | |
805 | fseek(f, 0, SEEK_END); | |
806 | size = ftell(f); | |
807 | fseek(f, where, SEEK_SET); | |
808 | ||
809 | return size; | |
810 | } | |
811 | ||
3cbeb524 AB |
812 | /* setup_data types */ |
813 | #define SETUP_NONE 0 | |
814 | #define SETUP_E820_EXT 1 | |
815 | #define SETUP_DTB 2 | |
816 | #define SETUP_PCI 3 | |
817 | #define SETUP_EFI 4 | |
818 | ||
819 | struct setup_data { | |
820 | uint64_t next; | |
821 | uint32_t type; | |
822 | uint32_t len; | |
823 | uint8_t data[0]; | |
824 | } __attribute__((packed)); | |
825 | ||
df1f79fd EH |
826 | static void load_linux(PCMachineState *pcms, |
827 | FWCfgState *fw_cfg) | |
642a4f96 TS |
828 | { |
829 | uint16_t protocol; | |
5cea8590 | 830 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
3cbeb524 | 831 | int dtb_size, setup_data_offset; |
642a4f96 | 832 | uint32_t initrd_max; |
57a46d05 | 833 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
a8170e5e | 834 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 835 | FILE *f; |
bf4e5d92 | 836 | char *vmode; |
df1f79fd | 837 | MachineState *machine = MACHINE(pcms); |
cd4040ec | 838 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
3cbeb524 | 839 | struct setup_data *setup_data; |
df1f79fd EH |
840 | const char *kernel_filename = machine->kernel_filename; |
841 | const char *initrd_filename = machine->initrd_filename; | |
3cbeb524 | 842 | const char *dtb_filename = machine->dtb; |
df1f79fd | 843 | const char *kernel_cmdline = machine->kernel_cmdline; |
642a4f96 TS |
844 | |
845 | /* Align to 16 bytes as a paranoia measure */ | |
846 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
847 | ||
848 | /* load the kernel header */ | |
849 | f = fopen(kernel_filename, "rb"); | |
850 | if (!f || !(kernel_size = get_file_size(f)) || | |
0f9d76e5 LG |
851 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
852 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
853 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
854 | kernel_filename, strerror(errno)); | |
855 | exit(1); | |
642a4f96 TS |
856 | } |
857 | ||
858 | /* kernel protocol version */ | |
bc4edd79 | 859 | #if 0 |
642a4f96 | 860 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 861 | #endif |
0f9d76e5 LG |
862 | if (ldl_p(header+0x202) == 0x53726448) { |
863 | protocol = lduw_p(header+0x206); | |
864 | } else { | |
865 | /* This looks like a multiboot kernel. If it is, let's stop | |
866 | treating it like a Linux kernel. */ | |
52001445 | 867 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
0f9d76e5 | 868 | kernel_cmdline, kernel_size, header)) { |
82663ee2 | 869 | return; |
0f9d76e5 LG |
870 | } |
871 | protocol = 0; | |
f16408df | 872 | } |
642a4f96 TS |
873 | |
874 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
0f9d76e5 LG |
875 | /* Low kernel */ |
876 | real_addr = 0x90000; | |
877 | cmdline_addr = 0x9a000 - cmdline_size; | |
878 | prot_addr = 0x10000; | |
642a4f96 | 879 | } else if (protocol < 0x202) { |
0f9d76e5 LG |
880 | /* High but ancient kernel */ |
881 | real_addr = 0x90000; | |
882 | cmdline_addr = 0x9a000 - cmdline_size; | |
883 | prot_addr = 0x100000; | |
642a4f96 | 884 | } else { |
0f9d76e5 LG |
885 | /* High and recent kernel */ |
886 | real_addr = 0x10000; | |
887 | cmdline_addr = 0x20000; | |
888 | prot_addr = 0x100000; | |
642a4f96 TS |
889 | } |
890 | ||
bc4edd79 | 891 | #if 0 |
642a4f96 | 892 | fprintf(stderr, |
0f9d76e5 LG |
893 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
894 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
895 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
896 | real_addr, | |
897 | cmdline_addr, | |
898 | prot_addr); | |
bc4edd79 | 899 | #endif |
642a4f96 TS |
900 | |
901 | /* highest address for loading the initrd */ | |
0f9d76e5 LG |
902 | if (protocol >= 0x203) { |
903 | initrd_max = ldl_p(header+0x22c); | |
904 | } else { | |
905 | initrd_max = 0x37ffffff; | |
906 | } | |
642a4f96 | 907 | |
cd4040ec EH |
908 | if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { |
909 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
927766c7 | 910 | } |
642a4f96 | 911 | |
57a46d05 AG |
912 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
913 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
96f80586 | 914 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
642a4f96 TS |
915 | |
916 | if (protocol >= 0x202) { | |
0f9d76e5 | 917 | stl_p(header+0x228, cmdline_addr); |
642a4f96 | 918 | } else { |
0f9d76e5 LG |
919 | stw_p(header+0x20, 0xA33F); |
920 | stw_p(header+0x22, cmdline_addr-real_addr); | |
642a4f96 TS |
921 | } |
922 | ||
bf4e5d92 PT |
923 | /* handle vga= parameter */ |
924 | vmode = strstr(kernel_cmdline, "vga="); | |
925 | if (vmode) { | |
926 | unsigned int video_mode; | |
927 | /* skip "vga=" */ | |
928 | vmode += 4; | |
929 | if (!strncmp(vmode, "normal", 6)) { | |
930 | video_mode = 0xffff; | |
931 | } else if (!strncmp(vmode, "ext", 3)) { | |
932 | video_mode = 0xfffe; | |
933 | } else if (!strncmp(vmode, "ask", 3)) { | |
934 | video_mode = 0xfffd; | |
935 | } else { | |
936 | video_mode = strtol(vmode, NULL, 0); | |
937 | } | |
938 | stw_p(header+0x1fa, video_mode); | |
939 | } | |
940 | ||
642a4f96 | 941 | /* loader type */ |
5cbdb3a3 | 942 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
943 | If this code is substantially changed, you may want to consider |
944 | incrementing the revision. */ | |
0f9d76e5 LG |
945 | if (protocol >= 0x200) { |
946 | header[0x210] = 0xB0; | |
947 | } | |
642a4f96 TS |
948 | /* heap */ |
949 | if (protocol >= 0x201) { | |
0f9d76e5 LG |
950 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
951 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
642a4f96 TS |
952 | } |
953 | ||
954 | /* load initrd */ | |
955 | if (initrd_filename) { | |
0f9d76e5 LG |
956 | if (protocol < 0x200) { |
957 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
958 | exit(1); | |
959 | } | |
642a4f96 | 960 | |
0f9d76e5 | 961 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 | 962 | if (initrd_size < 0) { |
7454e51d MT |
963 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", |
964 | initrd_filename, strerror(errno)); | |
d6fa4b77 MK |
965 | exit(1); |
966 | } | |
967 | ||
45a50b16 | 968 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 969 | |
7267c094 | 970 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
971 | load_image(initrd_filename, initrd_data); |
972 | ||
973 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
974 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
975 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 976 | |
0f9d76e5 LG |
977 | stl_p(header+0x218, initrd_addr); |
978 | stl_p(header+0x21c, initrd_size); | |
642a4f96 TS |
979 | } |
980 | ||
45a50b16 | 981 | /* load kernel and setup */ |
642a4f96 | 982 | setup_size = header[0x1f1]; |
0f9d76e5 LG |
983 | if (setup_size == 0) { |
984 | setup_size = 4; | |
985 | } | |
642a4f96 | 986 | setup_size = (setup_size+1)*512; |
ec5fd402 PB |
987 | if (setup_size > kernel_size) { |
988 | fprintf(stderr, "qemu: invalid kernel header\n"); | |
989 | exit(1); | |
990 | } | |
45a50b16 | 991 | kernel_size -= setup_size; |
642a4f96 | 992 | |
7267c094 AL |
993 | setup = g_malloc(setup_size); |
994 | kernel = g_malloc(kernel_size); | |
45a50b16 | 995 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
996 | if (fread(setup, 1, setup_size, f) != setup_size) { |
997 | fprintf(stderr, "fread() failed\n"); | |
998 | exit(1); | |
999 | } | |
1000 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
1001 | fprintf(stderr, "fread() failed\n"); | |
1002 | exit(1); | |
1003 | } | |
642a4f96 | 1004 | fclose(f); |
3cbeb524 AB |
1005 | |
1006 | /* append dtb to kernel */ | |
1007 | if (dtb_filename) { | |
1008 | if (protocol < 0x209) { | |
1009 | fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); | |
1010 | exit(1); | |
1011 | } | |
1012 | ||
1013 | dtb_size = get_image_size(dtb_filename); | |
1014 | if (dtb_size <= 0) { | |
1015 | fprintf(stderr, "qemu: error reading dtb %s: %s\n", | |
1016 | dtb_filename, strerror(errno)); | |
1017 | exit(1); | |
1018 | } | |
1019 | ||
1020 | setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); | |
1021 | kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; | |
1022 | kernel = g_realloc(kernel, kernel_size); | |
1023 | ||
1024 | stq_p(header+0x250, prot_addr + setup_data_offset); | |
1025 | ||
1026 | setup_data = (struct setup_data *)(kernel + setup_data_offset); | |
1027 | setup_data->next = 0; | |
1028 | setup_data->type = cpu_to_le32(SETUP_DTB); | |
1029 | setup_data->len = cpu_to_le32(dtb_size); | |
1030 | ||
1031 | load_image_size(dtb_filename, setup_data->data, dtb_size); | |
1032 | } | |
1033 | ||
45a50b16 | 1034 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
1035 | |
1036 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
1037 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1038 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
1039 | ||
1040 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
1041 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
1042 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
1043 | ||
b2a575a1 MM |
1044 | if (fw_cfg_dma_enabled(fw_cfg)) { |
1045 | option_rom[nb_option_roms].name = "linuxboot_dma.bin"; | |
1046 | option_rom[nb_option_roms].bootindex = 0; | |
1047 | } else { | |
1048 | option_rom[nb_option_roms].name = "linuxboot.bin"; | |
1049 | option_rom[nb_option_roms].bootindex = 0; | |
1050 | } | |
57a46d05 | 1051 | nb_option_roms++; |
642a4f96 TS |
1052 | } |
1053 | ||
b41a2cd1 FB |
1054 | #define NE2000_NB_MAX 6 |
1055 | ||
675d6f82 BS |
1056 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
1057 | 0x280, 0x380 }; | |
1058 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 1059 | |
48a18b3c | 1060 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
1061 | { |
1062 | static int nb_ne2k = 0; | |
1063 | ||
1064 | if (nb_ne2k == NE2000_NB_MAX) | |
1065 | return; | |
48a18b3c | 1066 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 1067 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
1068 | nb_ne2k++; |
1069 | } | |
1070 | ||
92a16d7a | 1071 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 1072 | { |
4917cf44 AF |
1073 | if (current_cpu) { |
1074 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 1075 | return cpu->apic_state; |
0e26b7b8 BS |
1076 | } else { |
1077 | return NULL; | |
1078 | } | |
1079 | } | |
1080 | ||
845773ab | 1081 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 1082 | { |
c3affe56 | 1083 | X86CPU *cpu = opaque; |
53b67b30 BS |
1084 | |
1085 | if (level) { | |
c3affe56 | 1086 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
1087 | } |
1088 | } | |
1089 | ||
eabff158 IM |
1090 | static int pc_present_cpus_count(PCMachineState *pcms) |
1091 | { | |
1092 | int i, boot_cpus = 0; | |
1093 | for (i = 0; i < pcms->possible_cpus->len; i++) { | |
1094 | if (pcms->possible_cpus->cpus[i].cpu) { | |
1095 | boot_cpus++; | |
1096 | } | |
1097 | } | |
1098 | return boot_cpus; | |
1099 | } | |
1100 | ||
6aff24c6 | 1101 | static X86CPU *pc_new_cpu(const char *typename, int64_t apic_id, |
46232aaa | 1102 | Error **errp) |
31050930 | 1103 | { |
e1570d00 | 1104 | X86CPU *cpu = NULL; |
31050930 IM |
1105 | Error *local_err = NULL; |
1106 | ||
6aff24c6 | 1107 | cpu = X86_CPU(object_new(typename)); |
31050930 IM |
1108 | |
1109 | object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); | |
1110 | object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); | |
1111 | ||
1112 | if (local_err) { | |
31050930 | 1113 | error_propagate(errp, local_err); |
cd7b87ff AF |
1114 | object_unref(OBJECT(cpu)); |
1115 | cpu = NULL; | |
31050930 IM |
1116 | } |
1117 | return cpu; | |
1118 | } | |
1119 | ||
c649983b IM |
1120 | void pc_hot_add_cpu(const int64_t id, Error **errp) |
1121 | { | |
0e3bd562 | 1122 | X86CPU *cpu; |
6aff24c6 IM |
1123 | ObjectClass *oc; |
1124 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
c649983b | 1125 | int64_t apic_id = x86_cpu_apic_id_from_index(id); |
0e3bd562 | 1126 | Error *local_err = NULL; |
c649983b | 1127 | |
8de433cb IM |
1128 | if (id < 0) { |
1129 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1130 | return; | |
1131 | } | |
1132 | ||
5ff020b7 EH |
1133 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1134 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1135 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1136 | id, apic_id); | |
1137 | return; | |
1138 | } | |
1139 | ||
6aff24c6 IM |
1140 | assert(pcms->possible_cpus->cpus[0].cpu); /* BSP is always present */ |
1141 | oc = OBJECT_CLASS(CPU_GET_CLASS(pcms->possible_cpus->cpus[0].cpu)); | |
1142 | cpu = pc_new_cpu(object_class_get_name(oc), apic_id, &local_err); | |
0e3bd562 AF |
1143 | if (local_err) { |
1144 | error_propagate(errp, local_err); | |
1145 | return; | |
1146 | } | |
1147 | object_unref(OBJECT(cpu)); | |
c649983b IM |
1148 | } |
1149 | ||
4884b7bf | 1150 | void pc_cpus_init(PCMachineState *pcms) |
70166477 IY |
1151 | { |
1152 | int i; | |
6aff24c6 IM |
1153 | CPUClass *cc; |
1154 | ObjectClass *oc; | |
1155 | const char *typename; | |
1156 | gchar **model_pieces; | |
53a89e26 | 1157 | X86CPU *cpu = NULL; |
4884b7bf | 1158 | MachineState *machine = MACHINE(pcms); |
70166477 IY |
1159 | |
1160 | /* init CPUs */ | |
4884b7bf | 1161 | if (machine->cpu_model == NULL) { |
70166477 | 1162 | #ifdef TARGET_X86_64 |
4884b7bf | 1163 | machine->cpu_model = "qemu64"; |
70166477 | 1164 | #else |
4884b7bf | 1165 | machine->cpu_model = "qemu32"; |
70166477 IY |
1166 | #endif |
1167 | } | |
1168 | ||
6aff24c6 IM |
1169 | model_pieces = g_strsplit(machine->cpu_model, ",", 2); |
1170 | if (!model_pieces[0]) { | |
1171 | error_report("Invalid/empty CPU model name"); | |
1172 | exit(1); | |
1173 | } | |
1174 | ||
1175 | oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); | |
1176 | if (oc == NULL) { | |
1177 | error_report("Unable to find CPU definition: %s", model_pieces[0]); | |
1178 | exit(1); | |
1179 | } | |
1180 | typename = object_class_get_name(oc); | |
1181 | cc = CPU_CLASS(oc); | |
1182 | cc->parse_features(typename, model_pieces[1], &error_fatal); | |
1183 | g_strfreev(model_pieces); | |
1184 | ||
ebde2465 IM |
1185 | /* Calculates the limit to CPU APIC ID values |
1186 | * | |
1187 | * Limit for the APIC ID value, so that all | |
1188 | * CPU APIC IDs are < pcms->apic_id_limit. | |
1189 | * | |
1190 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
1191 | */ | |
1192 | pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
3811ef14 IM |
1193 | pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
1194 | sizeof(CPUArchId) * max_cpus); | |
1195 | for (i = 0; i < max_cpus; i++) { | |
1196 | pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); | |
1197 | pcms->possible_cpus->len++; | |
1198 | if (i < smp_cpus) { | |
6aff24c6 | 1199 | cpu = pc_new_cpu(typename, x86_cpu_apic_id_from_index(i), |
3811ef14 | 1200 | &error_fatal); |
3811ef14 IM |
1201 | object_unref(OBJECT(cpu)); |
1202 | } | |
70166477 | 1203 | } |
53a89e26 | 1204 | |
c97294ec GS |
1205 | /* tell smbios about cpuid version and features */ |
1206 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
70166477 IY |
1207 | } |
1208 | ||
217f1b4a HZ |
1209 | static void pc_build_feature_control_file(PCMachineState *pcms) |
1210 | { | |
1211 | X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu); | |
1212 | CPUX86State *env = &cpu->env; | |
1213 | uint32_t unused, ecx, edx; | |
1214 | uint64_t feature_control_bits = 0; | |
1215 | uint64_t *val; | |
1216 | ||
1217 | cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); | |
1218 | if (ecx & CPUID_EXT_VMX) { | |
1219 | feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1220 | } | |
1221 | ||
1222 | if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == | |
1223 | (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && | |
1224 | (env->mcg_cap & MCG_LMCE_P)) { | |
1225 | feature_control_bits |= FEATURE_CONTROL_LMCE; | |
1226 | } | |
1227 | ||
1228 | if (!feature_control_bits) { | |
1229 | return; | |
1230 | } | |
1231 | ||
1232 | val = g_malloc(sizeof(*val)); | |
1233 | *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); | |
1234 | fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); | |
1235 | } | |
1236 | ||
3459a625 | 1237 | static |
9ebeed0c | 1238 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 1239 | { |
9ebeed0c EH |
1240 | PCMachineState *pcms = container_of(notifier, |
1241 | PCMachineState, machine_done); | |
1242 | PCIBus *bus = pcms->bus; | |
2118196b | 1243 | |
ba157b69 | 1244 | /* set the number of CPUs */ |
eabff158 | 1245 | rtc_set_memory(pcms->rtc, 0x5f, pc_present_cpus_count(pcms) - 1); |
ba157b69 | 1246 | |
2118196b MA |
1247 | if (bus) { |
1248 | int extra_hosts = 0; | |
1249 | ||
1250 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1251 | /* look for expander root buses */ | |
1252 | if (pci_bus_is_root(bus)) { | |
1253 | extra_hosts++; | |
1254 | } | |
1255 | } | |
f264d360 | 1256 | if (extra_hosts && pcms->fw_cfg) { |
2118196b MA |
1257 | uint64_t *val = g_malloc(sizeof(*val)); |
1258 | *val = cpu_to_le64(extra_hosts); | |
f264d360 | 1259 | fw_cfg_add_file(pcms->fw_cfg, |
2118196b MA |
1260 | "etc/extra-pci-roots", val, sizeof(*val)); |
1261 | } | |
1262 | } | |
1263 | ||
bb292f5a | 1264 | acpi_setup(); |
6d42eefa CM |
1265 | if (pcms->fw_cfg) { |
1266 | pc_build_smbios(pcms->fw_cfg); | |
217f1b4a | 1267 | pc_build_feature_control_file(pcms); |
6d42eefa | 1268 | } |
60c5e104 IM |
1269 | |
1270 | if (pcms->apic_id_limit > 255) { | |
1271 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); | |
1272 | ||
1273 | if (!iommu || !iommu->x86_iommu.intr_supported || | |
1274 | iommu->intr_eim != ON_OFF_AUTO_ON) { | |
1275 | error_report("current -smp configuration requires " | |
1276 | "Extended Interrupt Mode enabled. " | |
1277 | "You can add an IOMMU using: " | |
1278 | "-device intel-iommu,intremap=on,eim=on"); | |
1279 | exit(EXIT_FAILURE); | |
1280 | } | |
1281 | } | |
3459a625 MT |
1282 | } |
1283 | ||
e4e8ba04 | 1284 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 1285 | { |
1f3aba37 | 1286 | int i; |
b20c9bd5 | 1287 | |
dd4c2f01 EH |
1288 | pcms->apic_xrupt_override = kvm_allows_irq0_override(); |
1289 | pcms->numa_nodes = nb_numa_nodes; | |
1290 | pcms->node_mem = g_malloc0(pcms->numa_nodes * | |
1291 | sizeof *pcms->node_mem); | |
8c85901e | 1292 | for (i = 0; i < nb_numa_nodes; i++) { |
dd4c2f01 | 1293 | pcms->node_mem[i] = numa_info[i].node_mem; |
8c85901e WG |
1294 | } |
1295 | ||
9ebeed0c EH |
1296 | pcms->machine_done.notify = pc_machine_done; |
1297 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
1298 | } |
1299 | ||
83d08f26 MT |
1300 | /* setup pci memory address space mapping into system address space */ |
1301 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1302 | MemoryRegion *pci_address_space) | |
39848901 | 1303 | { |
83d08f26 MT |
1304 | /* Set to lower priority than RAM */ |
1305 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1306 | pci_address_space, -1); | |
39848901 IM |
1307 | } |
1308 | ||
f7e4dd6c GH |
1309 | void pc_acpi_init(const char *default_dsdt) |
1310 | { | |
c5a98cf3 | 1311 | char *filename; |
f7e4dd6c GH |
1312 | |
1313 | if (acpi_tables != NULL) { | |
1314 | /* manually set via -acpitable, leave it alone */ | |
1315 | return; | |
1316 | } | |
1317 | ||
1318 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
1319 | if (filename == NULL) { | |
1320 | fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); | |
c5a98cf3 | 1321 | } else { |
5bdb59a2 MA |
1322 | QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, |
1323 | &error_abort); | |
c5a98cf3 | 1324 | Error *err = NULL; |
f7e4dd6c | 1325 | |
5bdb59a2 | 1326 | qemu_opt_set(opts, "file", filename, &error_abort); |
0c764a9d | 1327 | |
1a4b2666 | 1328 | acpi_table_add_builtin(opts, &err); |
c5a98cf3 | 1329 | if (err) { |
c29b77f9 MA |
1330 | error_reportf_err(err, "WARNING: failed to load %s: ", |
1331 | filename); | |
c5a98cf3 | 1332 | } |
c5a98cf3 | 1333 | g_free(filename); |
f7e4dd6c | 1334 | } |
f7e4dd6c GH |
1335 | } |
1336 | ||
7bc35e0f | 1337 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
1338 | { |
1339 | int i; | |
1340 | FWCfgState *fw_cfg; | |
1341 | ||
df1f79fd | 1342 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 1343 | |
305ae888 | 1344 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
5836d168 | 1345 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
b33a5bbf CL |
1346 | rom_set_fw(fw_cfg); |
1347 | ||
df1f79fd | 1348 | load_linux(pcms, fw_cfg); |
b33a5bbf CL |
1349 | for (i = 0; i < nb_option_roms; i++) { |
1350 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 1351 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
b33a5bbf CL |
1352 | !strcmp(option_rom[i].name, "multiboot.bin")); |
1353 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1354 | } | |
f264d360 | 1355 | pcms->fw_cfg = fw_cfg; |
b33a5bbf CL |
1356 | } |
1357 | ||
5934e216 EH |
1358 | void pc_memory_init(PCMachineState *pcms, |
1359 | MemoryRegion *system_memory, | |
1360 | MemoryRegion *rom_memory, | |
1361 | MemoryRegion **ram_memory) | |
80cabfad | 1362 | { |
cbc5b5f3 JJ |
1363 | int linux_boot, i; |
1364 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1365 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1366 | FWCfgState *fw_cfg; |
62b160c0 | 1367 | MachineState *machine = MACHINE(pcms); |
16a9e8a5 | 1368 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
d592d303 | 1369 | |
c8d163bc EH |
1370 | assert(machine->ram_size == pcms->below_4g_mem_size + |
1371 | pcms->above_4g_mem_size); | |
9521d42b PB |
1372 | |
1373 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1374 | |
00cb2a99 | 1375 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1376 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1377 | * with older qemus that used qemu_ram_alloc(). |
1378 | */ | |
7267c094 | 1379 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1380 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1381 | machine->ram_size); | |
ae0a5466 | 1382 | *ram_memory = ram; |
7267c094 | 1383 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1384 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
c8d163bc | 1385 | 0, pcms->below_4g_mem_size); |
00cb2a99 | 1386 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
c8d163bc EH |
1387 | e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); |
1388 | if (pcms->above_4g_mem_size > 0) { | |
7267c094 | 1389 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1390 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
c8d163bc EH |
1391 | pcms->below_4g_mem_size, |
1392 | pcms->above_4g_mem_size); | |
00cb2a99 AK |
1393 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
1394 | ram_above_4g); | |
c8d163bc | 1395 | e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); |
bbe80adf | 1396 | } |
82b36dc3 | 1397 | |
bb292f5a | 1398 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 1399 | (machine->ram_slots || |
9521d42b | 1400 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1401 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1402 | ||
1403 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1404 | mc->name); | |
1405 | exit(EXIT_FAILURE); | |
1406 | } | |
1407 | ||
619d11e4 | 1408 | /* initialize hotplug memory address space */ |
bb292f5a | 1409 | if (pcmc->has_reserved_memory && |
9521d42b | 1410 | (machine->ram_size < machine->maxram_size)) { |
619d11e4 | 1411 | ram_addr_t hotplug_mem_size = |
9521d42b | 1412 | machine->maxram_size - machine->ram_size; |
619d11e4 | 1413 | |
a0cc8856 IM |
1414 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1415 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1416 | machine->ram_slots); | |
1417 | exit(EXIT_FAILURE); | |
1418 | } | |
1419 | ||
f2c38522 PK |
1420 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1421 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1422 | error_report("maximum memory size must by aligned to multiple of " | |
1423 | "%d bytes", TARGET_PAGE_SIZE); | |
1424 | exit(EXIT_FAILURE); | |
1425 | } | |
1426 | ||
a7d69ff1 | 1427 | pcms->hotplug_memory.base = |
c8d163bc | 1428 | ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); |
619d11e4 | 1429 | |
16a9e8a5 | 1430 | if (pcmc->enforce_aligned_dimm) { |
085f8e88 IM |
1431 | /* size hotplug region assuming 1G page max alignment per slot */ |
1432 | hotplug_mem_size += (1ULL << 30) * machine->ram_slots; | |
1433 | } | |
1434 | ||
a7d69ff1 | 1435 | if ((pcms->hotplug_memory.base + hotplug_mem_size) < |
619d11e4 IM |
1436 | hotplug_mem_size) { |
1437 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1438 | machine->maxram_size); | |
1439 | exit(EXIT_FAILURE); | |
1440 | } | |
1441 | ||
a7d69ff1 | 1442 | memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), |
619d11e4 | 1443 | "hotplug-memory", hotplug_mem_size); |
a7d69ff1 BR |
1444 | memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, |
1445 | &pcms->hotplug_memory.mr); | |
619d11e4 | 1446 | } |
cbc5b5f3 JJ |
1447 | |
1448 | /* Initialize PC system firmware */ | |
5db3f0de | 1449 | pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); |
00cb2a99 | 1450 | |
7267c094 | 1451 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
49946538 | 1452 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1453 | &error_fatal); |
c5705a77 | 1454 | vmstate_register_ram_global(option_rom_mr); |
4463aee6 | 1455 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1456 | PC_ROM_MIN_VGA, |
1457 | option_rom_mr, | |
1458 | 1); | |
f753ff16 | 1459 | |
ebde2465 | 1460 | fw_cfg = bochs_bios_init(&address_space_memory, pcms); |
c886fc4c | 1461 | |
8832cb80 | 1462 | rom_set_fw(fw_cfg); |
1d108d97 | 1463 | |
bb292f5a | 1464 | if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { |
de268e13 | 1465 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 IM |
1466 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
1467 | uint64_t res_mem_end = pcms->hotplug_memory.base; | |
1468 | ||
1469 | if (!pcmc->broken_reserved_end) { | |
1470 | res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); | |
1471 | } | |
3385e8e2 | 1472 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); |
de268e13 IM |
1473 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1474 | } | |
1475 | ||
f753ff16 | 1476 | if (linux_boot) { |
df1f79fd | 1477 | load_linux(pcms, fw_cfg); |
f753ff16 PB |
1478 | } |
1479 | ||
1480 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1481 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1482 | } |
f264d360 | 1483 | pcms->fw_cfg = fw_cfg; |
cb135f59 PX |
1484 | |
1485 | /* Init default IOAPIC address space */ | |
1486 | pcms->ioapic_as = &address_space_memory; | |
3d53f5c3 IY |
1487 | } |
1488 | ||
0b0cc076 | 1489 | qemu_irq pc_allocate_cpu_irq(void) |
845773ab | 1490 | { |
0b0cc076 | 1491 | return qemu_allocate_irq(pic_irq_request, NULL, 0); |
845773ab IY |
1492 | } |
1493 | ||
48a18b3c | 1494 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1495 | { |
ad6d45fa AL |
1496 | DeviceState *dev = NULL; |
1497 | ||
bab47d9a | 1498 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1499 | if (pci_bus) { |
1500 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1501 | dev = pcidev ? &pcidev->qdev : NULL; | |
1502 | } else if (isa_bus) { | |
1503 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1504 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1505 | } |
bab47d9a | 1506 | rom_reset_order_override(); |
ad6d45fa | 1507 | return dev; |
765d7908 IY |
1508 | } |
1509 | ||
258711c6 JG |
1510 | static const MemoryRegionOps ioport80_io_ops = { |
1511 | .write = ioport80_write, | |
c02e1eac | 1512 | .read = ioport80_read, |
258711c6 JG |
1513 | .endianness = DEVICE_NATIVE_ENDIAN, |
1514 | .impl = { | |
1515 | .min_access_size = 1, | |
1516 | .max_access_size = 1, | |
1517 | }, | |
1518 | }; | |
1519 | ||
1520 | static const MemoryRegionOps ioportF0_io_ops = { | |
1521 | .write = ioportF0_write, | |
c02e1eac | 1522 | .read = ioportF0_read, |
258711c6 JG |
1523 | .endianness = DEVICE_NATIVE_ENDIAN, |
1524 | .impl = { | |
1525 | .min_access_size = 1, | |
1526 | .max_access_size = 1, | |
1527 | }, | |
1528 | }; | |
1529 | ||
48a18b3c | 1530 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1531 | ISADevice **rtc_state, |
fd53c87c | 1532 | bool create_fdctrl, |
7a10ef51 | 1533 | bool no_vmport, |
3a87d009 | 1534 | uint32_t hpet_irqs) |
ffe513da IY |
1535 | { |
1536 | int i; | |
1537 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1538 | DeviceState *hpet = NULL; |
1539 | int pit_isa_irq = 0; | |
1540 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1541 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1542 | qemu_irq *a20_line; |
c2d8d311 | 1543 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
258711c6 JG |
1544 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1545 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1546 | |
2c9b15ca | 1547 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1548 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1549 | |
2c9b15ca | 1550 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1551 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1552 | |
5d17c0d2 JK |
1553 | /* |
1554 | * Check if an HPET shall be created. | |
1555 | * | |
1556 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1557 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1558 | */ | |
1559 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1560 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1561 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1562 | if (hpet) { |
7a10ef51 LPF |
1563 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1564 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1565 | * IRQ8 and IRQ2. | |
1566 | */ | |
1567 | uint8_t compat = object_property_get_int(OBJECT(hpet), | |
1568 | HPET_INTCAP, NULL); | |
1569 | if (!compat) { | |
1570 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1571 | } | |
1572 | qdev_init_nofail(hpet); | |
1573 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1574 | ||
b881fbe9 | 1575 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1576 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1577 | } |
ce967e2f JK |
1578 | pit_isa_irq = -1; |
1579 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1580 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1581 | } |
ffe513da | 1582 | } |
48a18b3c | 1583 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1584 | |
1585 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1586 | ||
c2d8d311 | 1587 | if (!xen_enabled()) { |
15eafc2e | 1588 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1589 | pit = kvm_pit_init(isa_bus, 0x40); |
1590 | } else { | |
1591 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1592 | } | |
1593 | if (hpet) { | |
1594 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1595 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1596 | } |
1597 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1598 | } |
ffe513da | 1599 | |
4496dc49 | 1600 | serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); |
07dc7880 | 1601 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
ffe513da | 1602 | |
182735ef | 1603 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1604 | i8042 = isa_create_simple(isa_bus, "i8042"); |
d80fe99d | 1605 | i8042_setup_a20_line(i8042, a20_line[0]); |
1611977c | 1606 | if (!no_vmport) { |
48a18b3c HP |
1607 | vmport_init(isa_bus); |
1608 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1609 | } else { |
1610 | vmmouse = NULL; | |
1611 | } | |
86d86414 | 1612 | if (vmmouse) { |
4a17cc4f AF |
1613 | DeviceState *dev = DEVICE(vmmouse); |
1614 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1615 | qdev_init_nofail(dev); | |
86d86414 | 1616 | } |
48a18b3c | 1617 | port92 = isa_create_simple(isa_bus, "port92"); |
d80fe99d | 1618 | port92_init(port92, a20_line[1]); |
ac64c5fd | 1619 | g_free(a20_line); |
956a3e6b | 1620 | |
57146941 | 1621 | DMA_init(isa_bus, 0); |
ffe513da IY |
1622 | |
1623 | for(i = 0; i < MAX_FD; i++) { | |
1624 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
936a7c1c | 1625 | create_fdctrl |= !!fd[i]; |
ffe513da | 1626 | } |
220a8846 LE |
1627 | if (create_fdctrl) { |
1628 | fdctrl_init_isa(isa_bus, fd); | |
1629 | } | |
ffe513da IY |
1630 | } |
1631 | ||
9011a1a7 IY |
1632 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) |
1633 | { | |
1634 | int i; | |
1635 | ||
bab47d9a | 1636 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1637 | for (i = 0; i < nb_nics; i++) { |
1638 | NICInfo *nd = &nd_table[i]; | |
1639 | ||
1640 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1641 | pc_init_ne2k_isa(isa_bus, nd); | |
1642 | } else { | |
29b358f9 | 1643 | pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); |
9011a1a7 IY |
1644 | } |
1645 | } | |
bab47d9a | 1646 | rom_reset_order_override(); |
9011a1a7 IY |
1647 | } |
1648 | ||
845773ab | 1649 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1650 | { |
1651 | int max_bus; | |
1652 | int bus; | |
1653 | ||
1654 | max_bus = drive_get_max_bus(IF_SCSI); | |
1655 | for (bus = 0; bus <= max_bus; bus++) { | |
1656 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1657 | } | |
1658 | } | |
a39e3564 JB |
1659 | |
1660 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1661 | { | |
1662 | DeviceState *dev; | |
1663 | SysBusDevice *d; | |
1664 | unsigned int i; | |
1665 | ||
15eafc2e | 1666 | if (kvm_ioapic_in_kernel()) { |
a39e3564 JB |
1667 | dev = qdev_create(NULL, "kvm-ioapic"); |
1668 | } else { | |
1669 | dev = qdev_create(NULL, "ioapic"); | |
1670 | } | |
1671 | if (parent_name) { | |
1672 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1673 | "ioapic", OBJECT(dev), NULL); | |
1674 | } | |
1675 | qdev_init_nofail(dev); | |
1356b98d | 1676 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1677 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1678 | |
1679 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1680 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1681 | } | |
1682 | } | |
d5747cac | 1683 | |
95bee274 IM |
1684 | static void pc_dimm_plug(HotplugHandler *hotplug_dev, |
1685 | DeviceState *dev, Error **errp) | |
1686 | { | |
3fbcdc27 | 1687 | HotplugHandlerClass *hhc; |
95bee274 IM |
1688 | Error *local_err = NULL; |
1689 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
16a9e8a5 | 1690 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
95bee274 IM |
1691 | PCDIMMDevice *dimm = PC_DIMM(dev); |
1692 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1693 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
92a37a04 | 1694 | uint64_t align = TARGET_PAGE_SIZE; |
95bee274 | 1695 | |
16a9e8a5 | 1696 | if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { |
91aa70ab IM |
1697 | align = memory_region_get_alignment(mr); |
1698 | } | |
1699 | ||
3fbcdc27 IM |
1700 | if (!pcms->acpi_dev) { |
1701 | error_setg(&local_err, | |
1702 | "memory hotplug is not enabled: missing acpi device"); | |
1703 | goto out; | |
1704 | } | |
1705 | ||
d6a9b0b8 | 1706 | pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); |
43bbb49e | 1707 | if (local_err) { |
b8865591 IM |
1708 | goto out; |
1709 | } | |
1710 | ||
c7f8d0f3 | 1711 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
284197e4 | 1712 | nvdimm_plug(&pcms->acpi_nvdimm_state); |
c7f8d0f3 XG |
1713 | } |
1714 | ||
3fbcdc27 | 1715 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
8e23184b | 1716 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1717 | out: |
1718 | error_propagate(errp, local_err); | |
1719 | } | |
1720 | ||
64fec58e TC |
1721 | static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, |
1722 | DeviceState *dev, Error **errp) | |
1723 | { | |
1724 | HotplugHandlerClass *hhc; | |
1725 | Error *local_err = NULL; | |
1726 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1727 | ||
1728 | if (!pcms->acpi_dev) { | |
1729 | error_setg(&local_err, | |
1730 | "memory hotplug is not enabled: missing acpi device"); | |
1731 | goto out; | |
1732 | } | |
1733 | ||
b097cc52 XG |
1734 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
1735 | error_setg(&local_err, | |
1736 | "nvdimm device hot unplug is not supported yet."); | |
1737 | goto out; | |
1738 | } | |
1739 | ||
64fec58e TC |
1740 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
1741 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1742 | ||
1743 | out: | |
1744 | error_propagate(errp, local_err); | |
1745 | } | |
1746 | ||
f7d3e29d TC |
1747 | static void pc_dimm_unplug(HotplugHandler *hotplug_dev, |
1748 | DeviceState *dev, Error **errp) | |
1749 | { | |
1750 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1751 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
1752 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1753 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
1754 | HotplugHandlerClass *hhc; | |
1755 | Error *local_err = NULL; | |
1756 | ||
1757 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1758 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1759 | ||
1760 | if (local_err) { | |
1761 | goto out; | |
1762 | } | |
1763 | ||
43bbb49e | 1764 | pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); |
f7d3e29d TC |
1765 | object_unparent(OBJECT(dev)); |
1766 | ||
1767 | out: | |
1768 | error_propagate(errp, local_err); | |
1769 | } | |
1770 | ||
3811ef14 IM |
1771 | static int pc_apic_cmp(const void *a, const void *b) |
1772 | { | |
1773 | CPUArchId *apic_a = (CPUArchId *)a; | |
1774 | CPUArchId *apic_b = (CPUArchId *)b; | |
1775 | ||
1776 | return apic_a->arch_id - apic_b->arch_id; | |
1777 | } | |
1778 | ||
7baef5cf IM |
1779 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id |
1780 | * in pcms->possible_cpus->cpus, if pcms->possible_cpus->cpus has no | |
1781 | * entry correponding to CPU's apic_id returns NULL. | |
1782 | */ | |
1783 | static CPUArchId *pc_find_cpu_slot(PCMachineState *pcms, CPUState *cpu, | |
1784 | int *idx) | |
1785 | { | |
1786 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
1787 | CPUArchId apic_id, *found_cpu; | |
1788 | ||
1789 | apic_id.arch_id = cc->get_arch_id(CPU(cpu)); | |
1790 | found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus, | |
1791 | pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus), | |
1792 | pc_apic_cmp); | |
1793 | if (found_cpu && idx) { | |
1794 | *idx = found_cpu - pcms->possible_cpus->cpus; | |
1795 | } | |
1796 | return found_cpu; | |
1797 | } | |
1798 | ||
5279569e GZ |
1799 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1800 | DeviceState *dev, Error **errp) | |
1801 | { | |
7baef5cf | 1802 | CPUArchId *found_cpu; |
5279569e GZ |
1803 | HotplugHandlerClass *hhc; |
1804 | Error *local_err = NULL; | |
1805 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1806 | ||
a44a49db IM |
1807 | if (pcms->acpi_dev) { |
1808 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1809 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1810 | if (local_err) { | |
1811 | goto out; | |
1812 | } | |
5279569e GZ |
1813 | } |
1814 | ||
a44a49db | 1815 | if (dev->hotplugged) { |
eabff158 IM |
1816 | /* increment the number of CPUs */ |
1817 | rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); | |
2d996150 GZ |
1818 | } |
1819 | ||
7baef5cf | 1820 | found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL); |
3811ef14 | 1821 | found_cpu->cpu = CPU(dev); |
5279569e GZ |
1822 | out: |
1823 | error_propagate(errp, local_err); | |
1824 | } | |
8872c25a IM |
1825 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
1826 | DeviceState *dev, Error **errp) | |
1827 | { | |
73360e27 | 1828 | int idx = -1; |
8872c25a IM |
1829 | HotplugHandlerClass *hhc; |
1830 | Error *local_err = NULL; | |
1831 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1832 | ||
73360e27 IM |
1833 | pc_find_cpu_slot(pcms, CPU(dev), &idx); |
1834 | assert(idx != -1); | |
1835 | if (idx == 0) { | |
1836 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
1837 | goto out; | |
1838 | } | |
1839 | ||
8872c25a IM |
1840 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
1841 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1842 | ||
1843 | if (local_err) { | |
1844 | goto out; | |
1845 | } | |
1846 | ||
1847 | out: | |
1848 | error_propagate(errp, local_err); | |
1849 | ||
1850 | } | |
1851 | ||
1852 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
1853 | DeviceState *dev, Error **errp) | |
1854 | { | |
8fe6374e | 1855 | CPUArchId *found_cpu; |
8872c25a IM |
1856 | HotplugHandlerClass *hhc; |
1857 | Error *local_err = NULL; | |
1858 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1859 | ||
1860 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1861 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1862 | ||
1863 | if (local_err) { | |
1864 | goto out; | |
1865 | } | |
1866 | ||
8fe6374e IM |
1867 | found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL); |
1868 | found_cpu->cpu = NULL; | |
1869 | object_unparent(OBJECT(dev)); | |
8872c25a | 1870 | |
eabff158 | 1871 | rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) - 1); |
8872c25a IM |
1872 | out: |
1873 | error_propagate(errp, local_err); | |
1874 | } | |
5279569e | 1875 | |
4ec60c76 IM |
1876 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, |
1877 | DeviceState *dev, Error **errp) | |
1878 | { | |
1879 | int idx; | |
a15d2728 | 1880 | CPUState *cs; |
e8f7b83e | 1881 | CPUArchId *cpu_slot; |
d89c2b8b | 1882 | X86CPUTopoInfo topo; |
4ec60c76 IM |
1883 | X86CPU *cpu = X86_CPU(dev); |
1884 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
4ec60c76 | 1885 | |
e8f7b83e IM |
1886 | /* if APIC ID is not set, set it based on socket/core/thread properties */ |
1887 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { | |
1888 | int max_socket = (max_cpus - 1) / smp_threads / smp_cores; | |
1889 | ||
1890 | if (cpu->socket_id < 0) { | |
1891 | error_setg(errp, "CPU socket-id is not set"); | |
1892 | return; | |
1893 | } else if (cpu->socket_id > max_socket) { | |
1894 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
1895 | cpu->socket_id, max_socket); | |
1896 | return; | |
1897 | } | |
1898 | if (cpu->core_id < 0) { | |
1899 | error_setg(errp, "CPU core-id is not set"); | |
1900 | return; | |
1901 | } else if (cpu->core_id > (smp_cores - 1)) { | |
1902 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
1903 | cpu->core_id, smp_cores - 1); | |
1904 | return; | |
1905 | } | |
1906 | if (cpu->thread_id < 0) { | |
1907 | error_setg(errp, "CPU thread-id is not set"); | |
1908 | return; | |
1909 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
1910 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
1911 | cpu->thread_id, smp_threads - 1); | |
1912 | return; | |
1913 | } | |
1914 | ||
1915 | topo.pkg_id = cpu->socket_id; | |
1916 | topo.core_id = cpu->core_id; | |
1917 | topo.smt_id = cpu->thread_id; | |
1918 | cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); | |
1919 | } | |
1920 | ||
1921 | cpu_slot = pc_find_cpu_slot(pcms, CPU(dev), &idx); | |
4ec60c76 | 1922 | if (!cpu_slot) { |
e8f7b83e IM |
1923 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); |
1924 | error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" | |
1925 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
1926 | topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, | |
4ec60c76 IM |
1927 | pcms->possible_cpus->len - 1); |
1928 | return; | |
1929 | } | |
1930 | ||
1931 | if (cpu_slot->cpu) { | |
1932 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
1933 | idx, cpu->apic_id); | |
1934 | return; | |
1935 | } | |
d89c2b8b IM |
1936 | |
1937 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
1938 | * so that query_hotpluggable_cpus would show correct values | |
1939 | */ | |
1940 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
1941 | * once -smp refactoring is complete and there will be CPU private | |
1942 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
1943 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); | |
1944 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { | |
1945 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
1946 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
1947 | return; | |
1948 | } | |
1949 | cpu->socket_id = topo.pkg_id; | |
1950 | ||
1951 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { | |
1952 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
1953 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
1954 | return; | |
1955 | } | |
1956 | cpu->core_id = topo.core_id; | |
1957 | ||
1958 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
1959 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
1960 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
1961 | return; | |
1962 | } | |
1963 | cpu->thread_id = topo.smt_id; | |
a15d2728 IM |
1964 | |
1965 | cs = CPU(cpu); | |
1966 | cs->cpu_index = idx; | |
4ec60c76 IM |
1967 | } |
1968 | ||
1969 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | |
1970 | DeviceState *dev, Error **errp) | |
1971 | { | |
1972 | if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
1973 | pc_cpu_pre_plug(hotplug_dev, dev, errp); | |
1974 | } | |
1975 | } | |
1976 | ||
95bee274 IM |
1977 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1978 | DeviceState *dev, Error **errp) | |
1979 | { | |
1980 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
1981 | pc_dimm_plug(hotplug_dev, dev, errp); | |
5279569e GZ |
1982 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1983 | pc_cpu_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1984 | } |
1985 | } | |
1986 | ||
d9c5c5b8 TC |
1987 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1988 | DeviceState *dev, Error **errp) | |
1989 | { | |
64fec58e TC |
1990 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1991 | pc_dimm_unplug_request(hotplug_dev, dev, errp); | |
8872c25a IM |
1992 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1993 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
64fec58e TC |
1994 | } else { |
1995 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1996 | " type: %s", object_get_typename(OBJECT(dev))); | |
1997 | } | |
d9c5c5b8 TC |
1998 | } |
1999 | ||
232391c1 TC |
2000 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
2001 | DeviceState *dev, Error **errp) | |
2002 | { | |
f7d3e29d TC |
2003 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2004 | pc_dimm_unplug(hotplug_dev, dev, errp); | |
8872c25a IM |
2005 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2006 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
f7d3e29d TC |
2007 | } else { |
2008 | error_setg(errp, "acpi: device unplug for not supported device" | |
2009 | " type: %s", object_get_typename(OBJECT(dev))); | |
2010 | } | |
232391c1 TC |
2011 | } |
2012 | ||
95bee274 IM |
2013 | static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, |
2014 | DeviceState *dev) | |
2015 | { | |
2016 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); | |
2017 | ||
5279569e GZ |
2018 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
2019 | object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
95bee274 IM |
2020 | return HOTPLUG_HANDLER(machine); |
2021 | } | |
2022 | ||
2023 | return pcmc->get_hotplug_handler ? | |
2024 | pcmc->get_hotplug_handler(machine, dev) : NULL; | |
2025 | } | |
2026 | ||
bf1e8939 | 2027 | static void |
d7bce999 EB |
2028 | pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, |
2029 | const char *name, void *opaque, | |
2030 | Error **errp) | |
bf1e8939 IM |
2031 | { |
2032 | PCMachineState *pcms = PC_MACHINE(obj); | |
a7d69ff1 | 2033 | int64_t value = memory_region_size(&pcms->hotplug_memory.mr); |
bf1e8939 | 2034 | |
51e72bc1 | 2035 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
2036 | } |
2037 | ||
c87b1520 | 2038 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
d7bce999 EB |
2039 | const char *name, void *opaque, |
2040 | Error **errp) | |
c87b1520 DS |
2041 | { |
2042 | PCMachineState *pcms = PC_MACHINE(obj); | |
2043 | uint64_t value = pcms->max_ram_below_4g; | |
2044 | ||
51e72bc1 | 2045 | visit_type_size(v, name, &value, errp); |
c87b1520 DS |
2046 | } |
2047 | ||
2048 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
d7bce999 EB |
2049 | const char *name, void *opaque, |
2050 | Error **errp) | |
c87b1520 DS |
2051 | { |
2052 | PCMachineState *pcms = PC_MACHINE(obj); | |
2053 | Error *error = NULL; | |
2054 | uint64_t value; | |
2055 | ||
51e72bc1 | 2056 | visit_type_size(v, name, &value, &error); |
c87b1520 DS |
2057 | if (error) { |
2058 | error_propagate(errp, error); | |
2059 | return; | |
2060 | } | |
2061 | if (value > (1ULL << 32)) { | |
455b0fde EB |
2062 | error_setg(&error, |
2063 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
2064 | "' expects size less than or equal to 4G", value); | |
c87b1520 DS |
2065 | error_propagate(errp, error); |
2066 | return; | |
2067 | } | |
2068 | ||
2069 | if (value < (1ULL << 20)) { | |
2070 | error_report("Warning: small max_ram_below_4g(%"PRIu64 | |
2071 | ") less than 1M. BIOS may not work..", | |
2072 | value); | |
2073 | } | |
2074 | ||
2075 | pcms->max_ram_below_4g = value; | |
2076 | } | |
2077 | ||
d7bce999 EB |
2078 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
2079 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2080 | { |
2081 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 2082 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 2083 | |
51e72bc1 | 2084 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
2085 | } |
2086 | ||
d7bce999 EB |
2087 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
2088 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2089 | { |
2090 | PCMachineState *pcms = PC_MACHINE(obj); | |
2091 | ||
51e72bc1 | 2092 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
2093 | } |
2094 | ||
355023f2 PB |
2095 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) |
2096 | { | |
2097 | bool smm_available = false; | |
2098 | ||
2099 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
2100 | return false; | |
2101 | } | |
2102 | ||
2103 | if (tcg_enabled() || qtest_enabled()) { | |
2104 | smm_available = true; | |
2105 | } else if (kvm_enabled()) { | |
2106 | smm_available = kvm_has_smm(); | |
2107 | } | |
2108 | ||
2109 | if (smm_available) { | |
2110 | return true; | |
2111 | } | |
2112 | ||
2113 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
2114 | error_report("System Management Mode not supported by this hypervisor."); | |
2115 | exit(1); | |
2116 | } | |
2117 | return false; | |
2118 | } | |
2119 | ||
d7bce999 EB |
2120 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, |
2121 | void *opaque, Error **errp) | |
355023f2 PB |
2122 | { |
2123 | PCMachineState *pcms = PC_MACHINE(obj); | |
2124 | OnOffAuto smm = pcms->smm; | |
2125 | ||
51e72bc1 | 2126 | visit_type_OnOffAuto(v, name, &smm, errp); |
355023f2 PB |
2127 | } |
2128 | ||
d7bce999 EB |
2129 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, |
2130 | void *opaque, Error **errp) | |
355023f2 PB |
2131 | { |
2132 | PCMachineState *pcms = PC_MACHINE(obj); | |
2133 | ||
51e72bc1 | 2134 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); |
355023f2 PB |
2135 | } |
2136 | ||
87252e1b XG |
2137 | static bool pc_machine_get_nvdimm(Object *obj, Error **errp) |
2138 | { | |
2139 | PCMachineState *pcms = PC_MACHINE(obj); | |
2140 | ||
5fe79386 | 2141 | return pcms->acpi_nvdimm_state.is_enabled; |
87252e1b XG |
2142 | } |
2143 | ||
2144 | static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
2145 | { | |
2146 | PCMachineState *pcms = PC_MACHINE(obj); | |
2147 | ||
5fe79386 | 2148 | pcms->acpi_nvdimm_state.is_enabled = value; |
87252e1b XG |
2149 | } |
2150 | ||
bf1e8939 IM |
2151 | static void pc_machine_initfn(Object *obj) |
2152 | { | |
c87b1520 DS |
2153 | PCMachineState *pcms = PC_MACHINE(obj); |
2154 | ||
5ec7d098 | 2155 | pcms->max_ram_below_4g = 0; /* use default */ |
355023f2 | 2156 | pcms->smm = ON_OFF_AUTO_AUTO; |
d1048bef | 2157 | pcms->vmport = ON_OFF_AUTO_AUTO; |
87252e1b | 2158 | /* nvdimm is disabled on default. */ |
5fe79386 | 2159 | pcms->acpi_nvdimm_state.is_enabled = false; |
021746c1 WL |
2160 | /* acpi build is enabled by default if machine supports it */ |
2161 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
bf1e8939 IM |
2162 | } |
2163 | ||
ae50c55a ZG |
2164 | static void pc_machine_reset(void) |
2165 | { | |
2166 | CPUState *cs; | |
2167 | X86CPU *cpu; | |
2168 | ||
2169 | qemu_devices_reset(); | |
2170 | ||
2171 | /* Reset APIC after devices have been reset to cancel | |
2172 | * any changes that qemu_devices_reset() might have done. | |
2173 | */ | |
2174 | CPU_FOREACH(cs) { | |
2175 | cpu = X86_CPU(cs); | |
2176 | ||
2177 | if (cpu->apic_state) { | |
2178 | device_reset(cpu->apic_state); | |
2179 | } | |
2180 | } | |
2181 | } | |
2182 | ||
fb43b73b IM |
2183 | static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) |
2184 | { | |
ed256144 | 2185 | X86CPUTopoInfo topo; |
fb43b73b | 2186 | x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, |
ed256144 CF |
2187 | &topo); |
2188 | return topo.pkg_id; | |
fb43b73b IM |
2189 | } |
2190 | ||
3811ef14 IM |
2191 | static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine) |
2192 | { | |
2193 | PCMachineState *pcms = PC_MACHINE(machine); | |
2194 | int len = sizeof(CPUArchIdList) + | |
2195 | sizeof(CPUArchId) * (pcms->possible_cpus->len); | |
2196 | CPUArchIdList *list = g_malloc(len); | |
2197 | ||
2198 | memcpy(list, pcms->possible_cpus, len); | |
2199 | return list; | |
2200 | } | |
2201 | ||
4d952914 IM |
2202 | static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine) |
2203 | { | |
2204 | int i; | |
2205 | CPUState *cpu; | |
2206 | HotpluggableCPUList *head = NULL; | |
2207 | PCMachineState *pcms = PC_MACHINE(machine); | |
2208 | const char *cpu_type; | |
2209 | ||
2210 | cpu = pcms->possible_cpus->cpus[0].cpu; | |
2211 | assert(cpu); /* BSP is always present */ | |
2212 | cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu))); | |
2213 | ||
2214 | for (i = 0; i < pcms->possible_cpus->len; i++) { | |
2215 | X86CPUTopoInfo topo; | |
2216 | HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); | |
2217 | HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); | |
2218 | CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); | |
2219 | const uint32_t apic_id = pcms->possible_cpus->cpus[i].arch_id; | |
2220 | ||
2221 | x86_topo_ids_from_apicid(apic_id, smp_cores, smp_threads, &topo); | |
2222 | ||
2223 | cpu_item->type = g_strdup(cpu_type); | |
2224 | cpu_item->vcpus_count = 1; | |
2225 | cpu_props->has_socket_id = true; | |
2226 | cpu_props->socket_id = topo.pkg_id; | |
2227 | cpu_props->has_core_id = true; | |
2228 | cpu_props->core_id = topo.core_id; | |
2229 | cpu_props->has_thread_id = true; | |
2230 | cpu_props->thread_id = topo.smt_id; | |
2231 | cpu_item->props = cpu_props; | |
2232 | ||
2233 | cpu = pcms->possible_cpus->cpus[i].cpu; | |
2234 | if (cpu) { | |
2235 | cpu_item->has_qom_path = true; | |
2236 | cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); | |
2237 | } | |
2238 | ||
2239 | list_item->value = cpu_item; | |
2240 | list_item->next = head; | |
2241 | head = list_item; | |
2242 | } | |
2243 | return head; | |
2244 | } | |
2245 | ||
1255166b BD |
2246 | static void x86_nmi(NMIState *n, int cpu_index, Error **errp) |
2247 | { | |
2248 | /* cpu index isn't used */ | |
2249 | CPUState *cs; | |
2250 | ||
2251 | CPU_FOREACH(cs) { | |
2252 | X86CPU *cpu = X86_CPU(cs); | |
2253 | ||
2254 | if (!cpu->apic_state) { | |
2255 | cpu_interrupt(cs, CPU_INTERRUPT_NMI); | |
2256 | } else { | |
2257 | apic_deliver_nmi(cpu->apic_state); | |
2258 | } | |
2259 | } | |
2260 | } | |
2261 | ||
95bee274 IM |
2262 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
2263 | { | |
2264 | MachineClass *mc = MACHINE_CLASS(oc); | |
2265 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2266 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1255166b | 2267 | NMIClass *nc = NMI_CLASS(oc); |
95bee274 IM |
2268 | |
2269 | pcmc->get_hotplug_handler = mc->get_hotplug_handler; | |
7102fa70 EH |
2270 | pcmc->pci_enabled = true; |
2271 | pcmc->has_acpi_build = true; | |
2272 | pcmc->rsdp_in_ram = true; | |
2273 | pcmc->smbios_defaults = true; | |
2274 | pcmc->smbios_uuid_encoded = true; | |
2275 | pcmc->gigabyte_align = true; | |
2276 | pcmc->has_reserved_memory = true; | |
2277 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 2278 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
2279 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
2280 | * to be used at the moment, 32K should be enough for a while. */ | |
2281 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
36f96c4b | 2282 | pcmc->save_tsc_khz = true; |
95bee274 | 2283 | mc->get_hotplug_handler = pc_get_hotpug_handler; |
fb43b73b | 2284 | mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; |
3811ef14 | 2285 | mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; |
4d952914 | 2286 | mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus; |
41742767 | 2287 | mc->default_boot_order = "cad"; |
4458fb3a EH |
2288 | mc->hot_add_cpu = pc_hot_add_cpu; |
2289 | mc->max_cpus = 255; | |
ae50c55a | 2290 | mc->reset = pc_machine_reset; |
4ec60c76 | 2291 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 2292 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 2293 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 2294 | hc->unplug = pc_machine_device_unplug_cb; |
1255166b | 2295 | nc->nmi_monitor_handler = x86_nmi; |
0efc257d EH |
2296 | |
2297 | object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int", | |
2298 | pc_machine_get_hotplug_memory_region_size, NULL, | |
2299 | NULL, NULL, &error_abort); | |
2300 | ||
2301 | object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
2302 | pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, | |
2303 | NULL, NULL, &error_abort); | |
2304 | ||
2305 | object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, | |
2306 | "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); | |
2307 | ||
2308 | object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", | |
2309 | pc_machine_get_smm, pc_machine_set_smm, | |
2310 | NULL, NULL, &error_abort); | |
2311 | object_class_property_set_description(oc, PC_MACHINE_SMM, | |
2312 | "Enable SMM (pc & q35)", &error_abort); | |
2313 | ||
2314 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", | |
2315 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2316 | NULL, NULL, &error_abort); | |
2317 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2318 | "Enable vmport (pc & q35)", &error_abort); | |
2319 | ||
2320 | object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, | |
2321 | pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); | |
95bee274 IM |
2322 | } |
2323 | ||
d5747cac IM |
2324 | static const TypeInfo pc_machine_info = { |
2325 | .name = TYPE_PC_MACHINE, | |
2326 | .parent = TYPE_MACHINE, | |
2327 | .abstract = true, | |
2328 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 2329 | .instance_init = pc_machine_initfn, |
d5747cac | 2330 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
2331 | .class_init = pc_machine_class_init, |
2332 | .interfaces = (InterfaceInfo[]) { | |
2333 | { TYPE_HOTPLUG_HANDLER }, | |
1255166b | 2334 | { TYPE_NMI }, |
95bee274 IM |
2335 | { } |
2336 | }, | |
d5747cac IM |
2337 | }; |
2338 | ||
2339 | static void pc_machine_register_types(void) | |
2340 | { | |
2341 | type_register_static(&pc_machine_info); | |
2342 | } | |
2343 | ||
2344 | type_init(pc_machine_register_types) |