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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
26 | #include "pc.h" | |
27 | #include "nvram.h" | |
28 | #include "fdc.h" | |
29 | #include "net.h" | |
30 | #include "qemu-timer.h" | |
31 | #include "sysemu.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
3cce6243 | 34 | #include "fw_cfg.h" |
3475187d | 35 | |
9d926598 BS |
36 | //#define DEBUG_IRQ |
37 | ||
38 | #ifdef DEBUG_IRQ | |
39 | #define DPRINTF(fmt, args...) \ | |
40 | do { printf("CPUIRQ: " fmt , ##args); } while (0) | |
41 | #else | |
42 | #define DPRINTF(fmt, args...) | |
43 | #endif | |
44 | ||
83469015 FB |
45 | #define KERNEL_LOAD_ADDR 0x00404000 |
46 | #define CMDLINE_ADDR 0x003ff000 | |
47 | #define INITRD_LOAD_ADDR 0x00300000 | |
ac2e9d66 | 48 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e BS |
49 | #define PROM_ADDR 0x1fff0000000ULL |
50 | #define PROM_VADDR 0x000ffd00000ULL | |
83469015 | 51 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e BS |
52 | #define APB_MEM_BASE 0x1ff00000000ULL |
53 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
54 | #define PROM_FILENAME "openbios-sparc64" | |
83469015 | 55 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 56 | #define MAX_IDE_BUS 2 |
3cce6243 | 57 | #define BIOS_CFG_IOPORT 0x510 |
3475187d | 58 | |
9d926598 BS |
59 | #define MAX_PILS 16 |
60 | ||
c7ba218d BS |
61 | struct hwdef { |
62 | const char * const default_cpu_model; | |
905fdcb5 | 63 | uint16_t machine_id; |
c7ba218d BS |
64 | }; |
65 | ||
3475187d FB |
66 | int DMA_get_channel_mode (int nchan) |
67 | { | |
68 | return 0; | |
69 | } | |
70 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
71 | { | |
72 | return 0; | |
73 | } | |
74 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
75 | { | |
76 | return 0; | |
77 | } | |
78 | void DMA_hold_DREQ (int nchan) {} | |
79 | void DMA_release_DREQ (int nchan) {} | |
80 | void DMA_schedule(int nchan) {} | |
81 | void DMA_run (void) {} | |
82 | void DMA_init (int high_page_enable) {} | |
83 | void DMA_register_channel (int nchan, | |
84 | DMA_transfer_handler transfer_handler, | |
85 | void *opaque) | |
86 | { | |
87 | } | |
88 | ||
81864572 BS |
89 | static int nvram_boot_set(void *opaque, const char *boot_device) |
90 | { | |
91 | unsigned int i; | |
92 | uint8_t image[sizeof(ohwcfg_v3_t)]; | |
93 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ | |
94 | m48t59_t *nvram = (m48t59_t *)opaque; | |
95 | ||
96 | for (i = 0; i < sizeof(image); i++) | |
97 | image[i] = m48t59_read(nvram, i) & 0xff; | |
98 | ||
363a37d5 BS |
99 | pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
100 | boot_device); | |
81864572 BS |
101 | header->nboot_devices = strlen(boot_device) & 0xff; |
102 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); | |
103 | ||
104 | for (i = 0; i < sizeof(image); i++) | |
105 | m48t59_write(nvram, i, image[i]); | |
106 | ||
107 | return 0; | |
108 | } | |
109 | ||
3475187d FB |
110 | extern int nographic; |
111 | ||
d2c63fc1 | 112 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
e7fb1406 | 113 | const char *arch, |
77f193da BS |
114 | ram_addr_t RAM_size, |
115 | const char *boot_devices, | |
d2c63fc1 BS |
116 | uint32_t kernel_image, uint32_t kernel_size, |
117 | const char *cmdline, | |
118 | uint32_t initrd_image, uint32_t initrd_size, | |
119 | uint32_t NVRAM_image, | |
0d31cb99 BS |
120 | int width, int height, int depth, |
121 | const uint8_t *macaddr) | |
83469015 | 122 | { |
66508601 BS |
123 | unsigned int i; |
124 | uint32_t start, end; | |
d2c63fc1 BS |
125 | uint8_t image[0x1ff0]; |
126 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ | |
127 | struct sparc_arch_cfg *sparc_header; | |
128 | struct OpenBIOS_nvpart_v1 *part_header; | |
129 | ||
130 | memset(image, '\0', sizeof(image)); | |
131 | ||
132 | // Try to match PPC NVRAM | |
363a37d5 BS |
133 | pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident), |
134 | "QEMU_BIOS"); | |
d2c63fc1 BS |
135 | header->struct_version = cpu_to_be32(3); /* structure v3 */ |
136 | ||
137 | header->nvram_size = cpu_to_be16(NVRAM_size); | |
138 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t)); | |
139 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); | |
363a37d5 | 140 | pstrcpy((char *)header->arch, sizeof(header->arch), arch); |
d2c63fc1 BS |
141 | header->nb_cpus = smp_cpus & 0xff; |
142 | header->RAM0_base = 0; | |
143 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); | |
363a37d5 BS |
144 | pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
145 | boot_devices); | |
d2c63fc1 BS |
146 | header->nboot_devices = strlen(boot_devices) & 0xff; |
147 | header->kernel_image = cpu_to_be64((uint64_t)kernel_image); | |
148 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); | |
3475187d | 149 | if (cmdline) { |
293f78bc | 150 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline); |
d2c63fc1 BS |
151 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
152 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); | |
3475187d | 153 | } |
d2c63fc1 BS |
154 | header->initrd_image = cpu_to_be64((uint64_t)initrd_image); |
155 | header->initrd_size = cpu_to_be64((uint64_t)initrd_size); | |
156 | header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image); | |
157 | ||
158 | header->width = cpu_to_be16(width); | |
159 | header->height = cpu_to_be16(height); | |
160 | header->depth = cpu_to_be16(depth); | |
161 | if (nographic) | |
162 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); | |
83469015 | 163 | |
d2c63fc1 BS |
164 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
165 | ||
166 | // Architecture specific header | |
167 | start = sizeof(ohwcfg_v3_t); | |
168 | sparc_header = (struct sparc_arch_cfg *)&image[start]; | |
169 | sparc_header->valid = 0; | |
170 | start += sizeof(struct sparc_arch_cfg); | |
83469015 | 171 | |
66508601 BS |
172 | // OpenBIOS nvram variables |
173 | // Variable partition | |
d2c63fc1 BS |
174 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
175 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 176 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 177 | |
d2c63fc1 | 178 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 179 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
180 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
181 | ||
182 | // End marker | |
183 | image[end++] = '\0'; | |
66508601 | 184 | |
66508601 | 185 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 186 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
187 | |
188 | // free partition | |
189 | start = end; | |
d2c63fc1 BS |
190 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
191 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 192 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
193 | |
194 | end = 0x1fd0; | |
d2c63fc1 BS |
195 | OpenBIOS_finish_partition(part_header, end - start); |
196 | ||
0d31cb99 BS |
197 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
198 | ||
d2c63fc1 BS |
199 | for (i = 0; i < sizeof(image); i++) |
200 | m48t59_write(nvram, i, image[i]); | |
66508601 | 201 | |
81864572 BS |
202 | qemu_register_boot_set(nvram_boot_set, nvram); |
203 | ||
83469015 | 204 | return 0; |
3475187d FB |
205 | } |
206 | ||
22548760 | 207 | void pic_info(void) |
3475187d FB |
208 | { |
209 | } | |
210 | ||
22548760 | 211 | void irq_info(void) |
3475187d FB |
212 | { |
213 | } | |
214 | ||
9d926598 BS |
215 | void cpu_check_irqs(CPUState *env) |
216 | { | |
217 | uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | | |
218 | ((env->softint & SOFTINT_TIMER) << 14); | |
219 | ||
220 | if (pil && (env->interrupt_index == 0 || | |
221 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
222 | unsigned int i; | |
223 | ||
224 | for (i = 15; i > 0; i--) { | |
225 | if (pil & (1 << i)) { | |
226 | int old_interrupt = env->interrupt_index; | |
227 | ||
228 | env->interrupt_index = TT_EXTINT | i; | |
229 | if (old_interrupt != env->interrupt_index) { | |
230 | DPRINTF("Set CPU IRQ %d\n", i); | |
231 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
232 | } | |
233 | break; | |
234 | } | |
235 | } | |
236 | } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) { | |
237 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); | |
238 | env->interrupt_index = 0; | |
239 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
240 | } | |
241 | } | |
242 | ||
243 | static void cpu_set_irq(void *opaque, int irq, int level) | |
244 | { | |
245 | CPUState *env = opaque; | |
246 | ||
247 | if (level) { | |
248 | DPRINTF("Raise CPU IRQ %d\n", irq); | |
249 | env->halted = 0; | |
250 | env->pil_in |= 1 << irq; | |
251 | cpu_check_irqs(env); | |
252 | } else { | |
253 | DPRINTF("Lower CPU IRQ %d\n", irq); | |
254 | env->pil_in &= ~(1 << irq); | |
255 | cpu_check_irqs(env); | |
256 | } | |
257 | } | |
258 | ||
83469015 | 259 | void qemu_system_powerdown(void) |
3475187d FB |
260 | { |
261 | } | |
262 | ||
c68ea704 FB |
263 | static void main_cpu_reset(void *opaque) |
264 | { | |
265 | CPUState *env = opaque; | |
20c9f095 | 266 | |
c68ea704 | 267 | cpu_reset(env); |
20c9f095 BS |
268 | ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); |
269 | ptimer_run(env->tick, 0); | |
270 | ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); | |
271 | ptimer_run(env->stick, 0); | |
272 | ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); | |
273 | ptimer_run(env->hstick, 0); | |
274 | } | |
275 | ||
22548760 | 276 | static void tick_irq(void *opaque) |
20c9f095 BS |
277 | { |
278 | CPUState *env = opaque; | |
279 | ||
9d926598 | 280 | env->softint |= SOFTINT_TIMER; |
20c9f095 BS |
281 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
282 | } | |
283 | ||
22548760 | 284 | static void stick_irq(void *opaque) |
20c9f095 BS |
285 | { |
286 | CPUState *env = opaque; | |
287 | ||
9d926598 | 288 | env->softint |= SOFTINT_TIMER; |
20c9f095 BS |
289 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
290 | } | |
291 | ||
22548760 | 292 | static void hstick_irq(void *opaque) |
20c9f095 BS |
293 | { |
294 | CPUState *env = opaque; | |
295 | ||
9d926598 | 296 | env->softint |= SOFTINT_TIMER; |
20c9f095 | 297 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
c68ea704 FB |
298 | } |
299 | ||
83469015 FB |
300 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
301 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
302 | static const int ide_irq[2] = { 14, 15 }; | |
3475187d | 303 | |
83469015 FB |
304 | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
305 | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
306 | ||
307 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
308 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
309 | ||
310 | static fdctrl_t *floppy_controller; | |
3475187d | 311 | |
c7ba218d BS |
312 | static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size, |
313 | const char *boot_devices, DisplayState *ds, | |
314 | const char *kernel_filename, const char *kernel_cmdline, | |
315 | const char *initrd_filename, const char *cpu_model, | |
316 | const struct hwdef *hwdef) | |
3475187d | 317 | { |
c68ea704 | 318 | CPUState *env; |
3475187d | 319 | char buf[1024]; |
83469015 | 320 | m48t59_t *nvram; |
3475187d FB |
321 | int ret, linux_boot; |
322 | unsigned int i; | |
83469015 FB |
323 | long prom_offset, initrd_size, kernel_size; |
324 | PCIBus *pci_bus; | |
20c9f095 | 325 | QEMUBH *bh; |
f19e918d | 326 | qemu_irq *irq; |
22548760 | 327 | int drive_index; |
e4bcb14c TS |
328 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
329 | BlockDriverState *fd[MAX_FD]; | |
3cce6243 | 330 | void *fw_cfg; |
3475187d FB |
331 | |
332 | linux_boot = (kernel_filename != NULL); | |
333 | ||
62724a37 | 334 | /* init CPUs */ |
c7ba218d BS |
335 | if (!cpu_model) |
336 | cpu_model = hwdef->default_cpu_model; | |
337 | ||
aaed909a FB |
338 | env = cpu_init(cpu_model); |
339 | if (!env) { | |
62724a37 BS |
340 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
341 | exit(1); | |
342 | } | |
20c9f095 BS |
343 | bh = qemu_bh_new(tick_irq, env); |
344 | env->tick = ptimer_init(bh); | |
345 | ptimer_set_period(env->tick, 1ULL); | |
346 | ||
347 | bh = qemu_bh_new(stick_irq, env); | |
348 | env->stick = ptimer_init(bh); | |
349 | ptimer_set_period(env->stick, 1ULL); | |
350 | ||
351 | bh = qemu_bh_new(hstick_irq, env); | |
352 | env->hstick = ptimer_init(bh); | |
353 | ptimer_set_period(env->hstick, 1ULL); | |
c68ea704 | 354 | qemu_register_reset(main_cpu_reset, env); |
20c9f095 | 355 | main_cpu_reset(env); |
c68ea704 | 356 | |
3475187d | 357 | /* allocate RAM */ |
22548760 | 358 | cpu_register_physical_memory(0, RAM_size, 0); |
3475187d | 359 | |
22548760 | 360 | prom_offset = RAM_size + vga_ram_size; |
5fafdf24 | 361 | cpu_register_physical_memory(PROM_ADDR, |
77f193da BS |
362 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
363 | TARGET_PAGE_MASK, | |
b3783731 | 364 | prom_offset | IO_MEM_ROM); |
3475187d | 365 | |
1192dad8 JM |
366 | if (bios_name == NULL) |
367 | bios_name = PROM_FILENAME; | |
368 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
f19e918d | 369 | ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
3475187d | 370 | if (ret < 0) { |
f930d07e BS |
371 | fprintf(stderr, "qemu: could not load prom '%s'\n", |
372 | buf); | |
373 | exit(1); | |
3475187d | 374 | } |
3475187d FB |
375 | |
376 | kernel_size = 0; | |
83469015 | 377 | initrd_size = 0; |
3475187d | 378 | if (linux_boot) { |
b3783731 | 379 | /* XXX: put correct offset */ |
74287114 | 380 | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
3475187d | 381 | if (kernel_size < 0) |
293f78bc BS |
382 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
383 | ram_size - KERNEL_LOAD_ADDR); | |
f930d07e | 384 | if (kernel_size < 0) |
293f78bc BS |
385 | kernel_size = load_image_targphys(kernel_filename, |
386 | KERNEL_LOAD_ADDR, | |
387 | ram_size - KERNEL_LOAD_ADDR); | |
3475187d | 388 | if (kernel_size < 0) { |
5fafdf24 | 389 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
3475187d | 390 | kernel_filename); |
f930d07e | 391 | exit(1); |
3475187d FB |
392 | } |
393 | ||
394 | /* load initrd */ | |
3475187d | 395 | if (initrd_filename) { |
293f78bc BS |
396 | initrd_size = load_image_targphys(initrd_filename, |
397 | INITRD_LOAD_ADDR, | |
398 | ram_size - INITRD_LOAD_ADDR); | |
3475187d | 399 | if (initrd_size < 0) { |
5fafdf24 | 400 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
3475187d FB |
401 | initrd_filename); |
402 | exit(1); | |
403 | } | |
404 | } | |
405 | if (initrd_size > 0) { | |
f930d07e | 406 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
293f78bc BS |
407 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
408 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
409 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
f930d07e BS |
410 | break; |
411 | } | |
412 | } | |
3475187d FB |
413 | } |
414 | } | |
502a5395 | 415 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); |
83469015 | 416 | isa_mem_base = VGA_BASE; |
77f193da BS |
417 | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size, |
418 | vga_ram_size); | |
83469015 FB |
419 | |
420 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
421 | if (serial_hds[i]) { | |
cbf5c748 BS |
422 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
423 | serial_hds[i]); | |
83469015 FB |
424 | } |
425 | } | |
426 | ||
427 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
428 | if (parallel_hds[i]) { | |
77f193da BS |
429 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
430 | parallel_hds[i]); | |
83469015 FB |
431 | } |
432 | } | |
433 | ||
434 | for(i = 0; i < nb_nics; i++) { | |
a41b2ff2 PB |
435 | if (!nd_table[i].model) |
436 | nd_table[i].model = "ne2k_pci"; | |
f930d07e | 437 | pci_nic_init(pci_bus, &nd_table[i], -1); |
83469015 FB |
438 | } |
439 | ||
9d926598 | 440 | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
e4bcb14c TS |
441 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
442 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
443 | exit(1); | |
444 | } | |
445 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
22548760 BS |
446 | drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, |
447 | i % MAX_IDE_DEVS); | |
448 | if (drive_index != -1) | |
449 | hd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
450 | else |
451 | hd[i] = NULL; | |
452 | } | |
453 | ||
454 | // XXX pci_cmd646_ide_init(pci_bus, hd, 1); | |
455 | pci_piix3_ide_init(pci_bus, hd, -1, irq); | |
d537cf6c PB |
456 | /* FIXME: wire up interrupts. */ |
457 | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); | |
e4bcb14c | 458 | for(i = 0; i < MAX_FD; i++) { |
22548760 BS |
459 | drive_index = drive_get_index(IF_FLOPPY, 0, i); |
460 | if (drive_index != -1) | |
461 | fd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
462 | else |
463 | fd[i] = NULL; | |
464 | } | |
465 | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); | |
d537cf6c | 466 | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
22548760 | 467 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, |
0d31cb99 BS |
468 | KERNEL_LOAD_ADDR, kernel_size, |
469 | kernel_cmdline, | |
470 | INITRD_LOAD_ADDR, initrd_size, | |
471 | /* XXX: need an option to load a NVRAM image */ | |
472 | 0, | |
473 | graphic_width, graphic_height, graphic_depth, | |
474 | (uint8_t *)&nd_table[0].macaddr); | |
83469015 | 475 | |
3cce6243 BS |
476 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
477 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
478 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
479 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
3475187d FB |
480 | } |
481 | ||
905fdcb5 BS |
482 | enum { |
483 | sun4u_id = 0, | |
484 | sun4v_id = 64, | |
485 | }; | |
486 | ||
c7ba218d BS |
487 | static const struct hwdef hwdefs[] = { |
488 | /* Sun4u generic PC-like machine */ | |
489 | { | |
490 | .default_cpu_model = "TI UltraSparc II", | |
905fdcb5 | 491 | .machine_id = sun4u_id, |
c7ba218d BS |
492 | }, |
493 | /* Sun4v generic PC-like machine */ | |
494 | { | |
495 | .default_cpu_model = "Sun UltraSparc T1", | |
905fdcb5 | 496 | .machine_id = sun4v_id, |
c7ba218d BS |
497 | }, |
498 | }; | |
499 | ||
500 | /* Sun4u hardware initialisation */ | |
501 | static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, | |
502 | const char *boot_devices, DisplayState *ds, | |
503 | const char *kernel_filename, const char *kernel_cmdline, | |
504 | const char *initrd_filename, const char *cpu_model) | |
505 | { | |
506 | sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, | |
507 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]); | |
508 | } | |
509 | ||
510 | /* Sun4v hardware initialisation */ | |
511 | static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size, | |
512 | const char *boot_devices, DisplayState *ds, | |
513 | const char *kernel_filename, const char *kernel_cmdline, | |
514 | const char *initrd_filename, const char *cpu_model) | |
515 | { | |
516 | sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, | |
517 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]); | |
518 | } | |
519 | ||
3475187d | 520 | QEMUMachine sun4u_machine = { |
66de733b BS |
521 | .name = "sun4u", |
522 | .desc = "Sun4u platform", | |
523 | .init = sun4u_init, | |
524 | .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, | |
f88e4b91 | 525 | .nodisk_ok = 1, |
3475187d | 526 | }; |
c7ba218d BS |
527 | |
528 | QEMUMachine sun4v_machine = { | |
66de733b BS |
529 | .name = "sun4v", |
530 | .desc = "Sun4v platform", | |
531 | .init = sun4v_init, | |
532 | .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, | |
f88e4b91 | 533 | .nodisk_ok = 1, |
c7ba218d | 534 | }; |