]>
Commit | Line | Data |
---|---|---|
47d05a86 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
09aae23d | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
71e8a915 | 30 | #include "sysemu/reset.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
32 | #include "hw/boards.h" |
33 | #include "hw/loader.h" | |
47d05a86 | 34 | #include "elf.h" |
022c62cb PB |
35 | #include "exec/memory.h" |
36 | #include "exec/address-spaces.h" | |
8488ab02 | 37 | #include "qemu/error-report.h" |
e53fa62c | 38 | #include "xtensa_memory.h" |
d9e8553b | 39 | #include "xtensa_sim.h" |
b68755c1 | 40 | |
00b941e5 | 41 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
47d05a86 | 42 | { |
00b941e5 AF |
43 | XtensaCPU *cpu = opaque; |
44 | ||
45 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
47d05a86 MF |
46 | } |
47 | ||
11e7bfd7 | 48 | static void sim_reset(void *opaque) |
47d05a86 | 49 | { |
11e7bfd7 AF |
50 | XtensaCPU *cpu = opaque; |
51 | ||
52 | cpu_reset(CPU(cpu)); | |
47d05a86 MF |
53 | } |
54 | ||
d9e8553b | 55 | XtensaCPU *xtensa_sim_common_init(MachineState *machine) |
47d05a86 | 56 | { |
06d26274 | 57 | XtensaCPU *cpu = NULL; |
5bfcb36e | 58 | CPUXtensaState *env = NULL; |
3ef96221 | 59 | ram_addr_t ram_size = machine->ram_size; |
47d05a86 MF |
60 | int n; |
61 | ||
33decbd2 | 62 | for (n = 0; n < machine->smp.cpus; n++) { |
d58eeae3 | 63 | cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); |
06d26274 AF |
64 | env = &cpu->env; |
65 | ||
47d05a86 | 66 | env->sregs[PRID] = n; |
11e7bfd7 | 67 | qemu_register_reset(sim_reset, cpu); |
47d05a86 MF |
68 | /* Need MMU initialized prior to ELF loading, |
69 | * so that ELF gets loaded into virtual addresses | |
70 | */ | |
11e7bfd7 | 71 | sim_reset(cpu); |
47d05a86 MF |
72 | } |
73 | ||
b68755c1 MF |
74 | if (env) { |
75 | XtensaMemory sysram = env->config->sysram; | |
47d05a86 | 76 | |
b68755c1 | 77 | sysram.location[0].size = ram_size; |
e53fa62c MF |
78 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", |
79 | get_system_memory()); | |
80 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", | |
81 | get_system_memory()); | |
82 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", | |
83 | get_system_memory()); | |
84 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", | |
85 | get_system_memory()); | |
86 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
87 | get_system_memory()); | |
88 | xtensa_create_memory_regions(&sysram, "xtensa.sysram", | |
89 | get_system_memory()); | |
b68755c1 | 90 | } |
9bca0edb PM |
91 | if (serial_hd(0)) { |
92 | xtensa_sim_open_console(serial_hd(0)); | |
8128b3e0 | 93 | } |
d9e8553b MF |
94 | return cpu; |
95 | } | |
96 | ||
97 | void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine) | |
98 | { | |
99 | const char *kernel_filename = machine->kernel_filename; | |
47d05a86 | 100 | #ifdef TARGET_WORDS_BIGENDIAN |
d9e8553b | 101 | int big_endian = true; |
47d05a86 | 102 | #else |
d9e8553b | 103 | int big_endian = false; |
47d05a86 | 104 | #endif |
d9e8553b MF |
105 | |
106 | if (kernel_filename) { | |
107 | uint64_t elf_entry; | |
d9e8553b | 108 | int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, |
617160c9 | 109 | &elf_entry, NULL, NULL, NULL, big_endian, |
d9e8553b MF |
110 | EM_XTENSA, 0, 0); |
111 | ||
47d05a86 | 112 | if (success > 0) { |
d9e8553b | 113 | cpu->env.pc = elf_entry; |
47d05a86 MF |
114 | } |
115 | } | |
116 | } | |
117 | ||
d9e8553b MF |
118 | static void xtensa_sim_init(MachineState *machine) |
119 | { | |
120 | XtensaCPU *cpu = xtensa_sim_common_init(machine); | |
121 | ||
122 | xtensa_sim_load_kernel(cpu, machine); | |
123 | } | |
124 | ||
e264d29d | 125 | static void xtensa_sim_machine_init(MachineClass *mc) |
47d05a86 | 126 | { |
e264d29d EH |
127 | mc->desc = "sim machine (" XTENSA_DEFAULT_CPU_MODEL ")"; |
128 | mc->is_default = true; | |
129 | mc->init = xtensa_sim_init; | |
130 | mc->max_cpus = 4; | |
8128b3e0 | 131 | mc->no_serial = 1; |
d58eeae3 | 132 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
47d05a86 MF |
133 | } |
134 | ||
e264d29d | 135 | DEFINE_MACHINE("sim", xtensa_sim_machine_init) |