]>
Commit | Line | Data |
---|---|---|
43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
ff90606f CLG |
12 | #ifndef ASPEED_SOC_H |
13 | #define ASPEED_SOC_H | |
43e3346e | 14 | |
f25c0ae1 | 15 | #include "hw/cpu/a15mpcore.h" |
356b230e | 16 | #include "hw/arm/armv7m.h" |
43e3346e | 17 | #include "hw/intc/aspeed_vic.h" |
334973bb | 18 | #include "hw/misc/aspeed_scu.h" |
199fd623 | 19 | #include "hw/adc/aspeed_adc.h" |
c2da8a8b | 20 | #include "hw/misc/aspeed_sdmc.h" |
118c82e7 | 21 | #include "hw/misc/aspeed_xdma.h" |
43e3346e | 22 | #include "hw/timer/aspeed_timer.h" |
ea5dcf4e | 23 | #include "hw/rtc/aspeed_rtc.h" |
16020011 | 24 | #include "hw/i2c/aspeed_i2c.h" |
3222165d | 25 | #include "hw/misc/aspeed_i3c.h" |
7c1c69bc | 26 | #include "hw/ssi/aspeed_smc.h" |
a3888d75 | 27 | #include "hw/misc/aspeed_hace.h" |
e1acf581 | 28 | #include "hw/misc/aspeed_sbc.h" |
013befe1 | 29 | #include "hw/watchdog/wdt_aspeed.h" |
ea337c65 | 30 | #include "hw/net/ftgmac100.h" |
ec150c7e | 31 | #include "target/arm/cpu.h" |
fdcc7c06 | 32 | #include "hw/gpio/aspeed_gpio.h" |
2bea128c | 33 | #include "hw/sd/aspeed_sdhci.h" |
bfdd34f1 | 34 | #include "hw/usb/hcd-ehci.h" |
db1015e9 | 35 | #include "qom/object.h" |
2ecf1726 | 36 | #include "hw/misc/aspeed_lpc.h" |
80beb085 | 37 | #include "hw/misc/unimp.h" |
55c57023 | 38 | #include "hw/misc/aspeed_peci.h" |
3fd941f3 | 39 | #include "hw/fsi/aspeed_apb2opb.h" |
d2b3eaef | 40 | #include "hw/char/serial.h" |
43e3346e | 41 | |
dbcabeeb | 42 | #define ASPEED_SPIS_NUM 2 |
bfdd34f1 | 43 | #define ASPEED_EHCIS_NUM 2 |
6b2b2a70 | 44 | #define ASPEED_WDTS_NUM 4 |
ece09bee | 45 | #define ASPEED_CPUS_NUM 2 |
d300db02 | 46 | #define ASPEED_MACS_NUM 4 |
d2b3eaef | 47 | #define ASPEED_UARTS_NUM 13 |
72006c61 | 48 | #define ASPEED_JTAG_NUM 2 |
dbcabeeb | 49 | |
db1015e9 | 50 | struct AspeedSoCState { |
43e3346e AJ |
51 | DeviceState parent; |
52 | ||
4dd9d554 | 53 | MemoryRegion *memory; |
95b56e17 | 54 | MemoryRegion *dram_mr; |
346160cb | 55 | MemoryRegion dram_container; |
74af4eec | 56 | MemoryRegion sram; |
5aa281d7 CLG |
57 | MemoryRegion spi_boot_container; |
58 | MemoryRegion spi_boot; | |
75fb4577 | 59 | AspeedRtcState rtc; |
43e3346e | 60 | AspeedTimerCtrlState timerctrl; |
16020011 | 61 | AspeedI2CState i2c; |
3222165d | 62 | AspeedI3CState i3c; |
334973bb | 63 | AspeedSCUState scu; |
a3888d75 | 64 | AspeedHACEState hace; |
118c82e7 | 65 | AspeedXDMAState xdma; |
199fd623 | 66 | AspeedADCState adc; |
0e5803df | 67 | AspeedSMCState fmc; |
dbcabeeb | 68 | AspeedSMCState spi[ASPEED_SPIS_NUM]; |
bfdd34f1 | 69 | EHCISysBusState ehci[ASPEED_EHCIS_NUM]; |
e1acf581 | 70 | AspeedSBCState sbc; |
6ba3dc25 | 71 | MemoryRegion secsram; |
80beb085 | 72 | UnimplementedDeviceState sbc_unimplemented; |
c2da8a8b | 73 | AspeedSDMCState sdmc; |
f986ee1d | 74 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; |
67340990 | 75 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; |
289251b0 | 76 | AspeedMiiState mii[ASPEED_MACS_NUM]; |
fdcc7c06 | 77 | AspeedGPIOState gpio; |
f25c0ae1 | 78 | AspeedGPIOState gpio_1_8v; |
2bea128c | 79 | AspeedSDHCIState sdhci; |
a29e3e12 | 80 | AspeedSDHCIState emmc; |
2ecf1726 | 81 | AspeedLPCState lpc; |
55c57023 | 82 | AspeedPECIState peci; |
d2b3eaef | 83 | SerialMM uart[ASPEED_UARTS_NUM]; |
356b230e | 84 | Clock *sysclk; |
80beb085 PD |
85 | UnimplementedDeviceState iomem; |
86 | UnimplementedDeviceState video; | |
87 | UnimplementedDeviceState emmc_boot_controller; | |
88 | UnimplementedDeviceState dpmcu; | |
72006c61 PMD |
89 | UnimplementedDeviceState pwm; |
90 | UnimplementedDeviceState espi; | |
91 | UnimplementedDeviceState udc; | |
92 | UnimplementedDeviceState sgpiom; | |
93 | UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; | |
3fd941f3 | 94 | AspeedAPB2OPBState fsi[2]; |
db1015e9 | 95 | }; |
43e3346e | 96 | |
ff90606f | 97 | #define TYPE_ASPEED_SOC "aspeed-soc" |
a489d195 | 98 | OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) |
43e3346e | 99 | |
1a94fae4 PMD |
100 | struct Aspeed2400SoCState { |
101 | AspeedSoCState parent; | |
dd41ce7a PMD |
102 | |
103 | ARMCPU cpu[ASPEED_CPUS_NUM]; | |
104 | AspeedVICState vic; | |
1a94fae4 PMD |
105 | }; |
106 | ||
107 | #define TYPE_ASPEED2400_SOC "aspeed2400-soc" | |
108 | OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) | |
109 | ||
4fc5e806 PMD |
110 | struct Aspeed2600SoCState { |
111 | AspeedSoCState parent; | |
c17fc025 PMD |
112 | |
113 | A15MPPrivState a7mpcore; | |
114 | ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ | |
4fc5e806 PMD |
115 | }; |
116 | ||
117 | #define TYPE_ASPEED2600_SOC "aspeed2600-soc" | |
118 | OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) | |
119 | ||
df4ab076 PMD |
120 | struct Aspeed10x0SoCState { |
121 | AspeedSoCState parent; | |
a0c21030 PMD |
122 | |
123 | ARMv7MState armv7m; | |
df4ab076 PMD |
124 | }; |
125 | ||
126 | #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" | |
127 | OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) | |
128 | ||
db1015e9 | 129 | struct AspeedSoCClass { |
54ecafb7 CLG |
130 | DeviceClass parent_class; |
131 | ||
b033271f | 132 | const char *name; |
dc13909e PMD |
133 | /** valid_cpu_types: NULL terminated array of a single CPU type. */ |
134 | const char * const *valid_cpu_types; | |
b033271f | 135 | uint32_t silicon_rev; |
74af4eec | 136 | uint64_t sram_size; |
6ba3dc25 | 137 | uint64_t secsram_size; |
dbcabeeb | 138 | int spis_num; |
bfdd34f1 | 139 | int ehcis_num; |
f986ee1d | 140 | int wdts_num; |
d300db02 | 141 | int macs_num; |
c5e1bdb9 | 142 | int uarts_num; |
b456b113 | 143 | const int *irqmap; |
d783d1fe | 144 | const hwaddr *memmap; |
ece09bee | 145 | uint32_t num_cpus; |
699db715 | 146 | qemu_irq (*get_irq)(AspeedSoCState *s, int dev); |
db1015e9 | 147 | }; |
b033271f | 148 | |
d815649c | 149 | const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); |
43e3346e | 150 | |
b456b113 | 151 | enum { |
5aa281d7 | 152 | ASPEED_DEV_SPI_BOOT, |
347df6f8 EH |
153 | ASPEED_DEV_IOMEM, |
154 | ASPEED_DEV_UART1, | |
155 | ASPEED_DEV_UART2, | |
156 | ASPEED_DEV_UART3, | |
157 | ASPEED_DEV_UART4, | |
158 | ASPEED_DEV_UART5, | |
ab5e8605 PD |
159 | ASPEED_DEV_UART6, |
160 | ASPEED_DEV_UART7, | |
161 | ASPEED_DEV_UART8, | |
162 | ASPEED_DEV_UART9, | |
163 | ASPEED_DEV_UART10, | |
164 | ASPEED_DEV_UART11, | |
165 | ASPEED_DEV_UART12, | |
166 | ASPEED_DEV_UART13, | |
347df6f8 EH |
167 | ASPEED_DEV_VUART, |
168 | ASPEED_DEV_FMC, | |
169 | ASPEED_DEV_SPI1, | |
170 | ASPEED_DEV_SPI2, | |
171 | ASPEED_DEV_EHCI1, | |
172 | ASPEED_DEV_EHCI2, | |
173 | ASPEED_DEV_VIC, | |
174 | ASPEED_DEV_SDMC, | |
175 | ASPEED_DEV_SCU, | |
176 | ASPEED_DEV_ADC, | |
e1acf581 | 177 | ASPEED_DEV_SBC, |
6ba3dc25 | 178 | ASPEED_DEV_SECSRAM, |
fe31a2ec | 179 | ASPEED_DEV_EMMC_BC, |
347df6f8 EH |
180 | ASPEED_DEV_VIDEO, |
181 | ASPEED_DEV_SRAM, | |
182 | ASPEED_DEV_SDHCI, | |
183 | ASPEED_DEV_GPIO, | |
184 | ASPEED_DEV_GPIO_1_8V, | |
185 | ASPEED_DEV_RTC, | |
186 | ASPEED_DEV_TIMER1, | |
187 | ASPEED_DEV_TIMER2, | |
188 | ASPEED_DEV_TIMER3, | |
189 | ASPEED_DEV_TIMER4, | |
190 | ASPEED_DEV_TIMER5, | |
191 | ASPEED_DEV_TIMER6, | |
192 | ASPEED_DEV_TIMER7, | |
193 | ASPEED_DEV_TIMER8, | |
194 | ASPEED_DEV_WDT, | |
195 | ASPEED_DEV_PWM, | |
196 | ASPEED_DEV_LPC, | |
197 | ASPEED_DEV_IBT, | |
198 | ASPEED_DEV_I2C, | |
55c57023 | 199 | ASPEED_DEV_PECI, |
347df6f8 EH |
200 | ASPEED_DEV_ETH1, |
201 | ASPEED_DEV_ETH2, | |
202 | ASPEED_DEV_ETH3, | |
203 | ASPEED_DEV_ETH4, | |
204 | ASPEED_DEV_MII1, | |
205 | ASPEED_DEV_MII2, | |
206 | ASPEED_DEV_MII3, | |
207 | ASPEED_DEV_MII4, | |
208 | ASPEED_DEV_SDRAM, | |
209 | ASPEED_DEV_XDMA, | |
210 | ASPEED_DEV_EMMC, | |
c59f781e | 211 | ASPEED_DEV_KCS, |
a3888d75 | 212 | ASPEED_DEV_HACE, |
d9e9cd59 TL |
213 | ASPEED_DEV_DPMCU, |
214 | ASPEED_DEV_DP, | |
3222165d | 215 | ASPEED_DEV_I3C, |
72006c61 PMD |
216 | ASPEED_DEV_ESPI, |
217 | ASPEED_DEV_UDC, | |
218 | ASPEED_DEV_SGPIOM, | |
219 | ASPEED_DEV_JTAG0, | |
220 | ASPEED_DEV_JTAG1, | |
3fd941f3 NP |
221 | ASPEED_DEV_FSI1, |
222 | ASPEED_DEV_FSI2, | |
b456b113 CLG |
223 | }; |
224 | ||
5aa281d7 CLG |
225 | #define ASPEED_SOC_SPI_BOOT_ADDR 0x0 |
226 | ||
699db715 | 227 | qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); |
d2b3eaef PD |
228 | bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); |
229 | void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); | |
346160cb | 230 | bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); |
5bfcbda7 | 231 | void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); |
80beb085 PD |
232 | void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, |
233 | const char *name, hwaddr addr, | |
234 | uint64_t size); | |
1099ad10 PD |
235 | void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, |
236 | unsigned int count, int unit0); | |
699db715 | 237 | |
ff90606f | 238 | #endif /* ASPEED_SOC_H */ |