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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef HW_PC_H |
2 | #define HW_PC_H | |
376253ec | 3 | |
022c62cb | 4 | #include "exec/memory.h" |
9521d42b | 5 | #include "hw/boards.h" |
0d09e41a PB |
6 | #include "hw/isa/isa.h" |
7 | #include "hw/block/fdc.h" | |
ebc29e1b | 8 | #include "hw/block/flash.h" |
1422e32d | 9 | #include "net/net.h" |
0d09e41a | 10 | #include "hw/i386/ioapic.h" |
376253ec | 11 | |
3459a625 | 12 | #include "qemu/range.h" |
b20c9bd5 | 13 | #include "qemu/bitmap.h" |
0b8fa32f | 14 | #include "qemu/module.h" |
b20c9bd5 MT |
15 | #include "sysemu/sysemu.h" |
16 | #include "hw/pci/pci.h" | |
a7d69ff1 | 17 | #include "hw/mem/pc-dimm.h" |
5fe79386 | 18 | #include "hw/mem/nvdimm.h" |
ac35f13b | 19 | #include "hw/acpi/acpi_dev_interface.h" |
3459a625 | 20 | |
7a10ef51 LPF |
21 | #define HPET_INTCAP "hpet-intcap" |
22 | ||
619d11e4 IM |
23 | /** |
24 | * PCMachineState: | |
781bbd6b | 25 | * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling |
e3cadac0 | 26 | * @boot_cpus: number of present VCPUs |
c26ae610 | 27 | * @smp_dies: number of dies per one package |
619d11e4 | 28 | */ |
d5747cac IM |
29 | struct PCMachineState { |
30 | /*< private >*/ | |
31 | MachineState parent_obj; | |
619d11e4 IM |
32 | |
33 | /* <public> */ | |
13fc8343 EH |
34 | |
35 | /* State for other subsystems/APIs: */ | |
9ebeed0c | 36 | Notifier machine_done; |
781bbd6b | 37 | |
13fc8343 | 38 | /* Pointers to devices and objects: */ |
781bbd6b | 39 | HotplugHandler *acpi_dev; |
2d996150 | 40 | ISADevice *rtc; |
13fc8343 | 41 | PCIBus *bus; |
f264d360 | 42 | FWCfgState *fw_cfg; |
3e6c0c4c | 43 | qemu_irq *gsi; |
ebc29e1b | 44 | PFlashCFI01 *flash[2]; |
c87b1520 | 45 | |
13fc8343 | 46 | /* Configuration options: */ |
c87b1520 | 47 | uint64_t max_ram_below_4g; |
d1048bef | 48 | OnOffAuto vmport; |
355023f2 | 49 | OnOffAuto smm; |
5fe79386 | 50 | |
021746c1 | 51 | bool acpi_build_enabled; |
f5878b03 CM |
52 | bool smbus_enabled; |
53 | bool sata_enabled; | |
54 | bool pit_enabled; | |
021746c1 | 55 | |
13fc8343 | 56 | /* RAM information (sizes, addresses, configuration): */ |
c0aa4e1e | 57 | ram_addr_t below_4g_mem_size, above_4g_mem_size; |
dd4c2f01 EH |
58 | |
59 | /* CPU and apic information: */ | |
60 | bool apic_xrupt_override; | |
61 | unsigned apic_id_limit; | |
e3cadac0 | 62 | uint16_t boot_cpus; |
c26ae610 | 63 | unsigned smp_dies; |
dd4c2f01 EH |
64 | |
65 | /* NUMA information: */ | |
66 | uint64_t numa_nodes; | |
67 | uint64_t *node_mem; | |
cb135f59 PX |
68 | |
69 | /* Address space used by IOAPIC device. All IOAPIC interrupts | |
70 | * will be translated to MSI messages in the address space. */ | |
71 | AddressSpace *ioapic_as; | |
d5747cac IM |
72 | }; |
73 | ||
781bbd6b | 74 | #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" |
f2ffbe2b | 75 | #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" |
c87b1520 | 76 | #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" |
9b23cfb7 | 77 | #define PC_MACHINE_VMPORT "vmport" |
355023f2 | 78 | #define PC_MACHINE_SMM "smm" |
be232eb0 | 79 | #define PC_MACHINE_SMBUS "smbus" |
272f0428 | 80 | #define PC_MACHINE_SATA "sata" |
feddd2fd | 81 | #define PC_MACHINE_PIT "pit" |
781bbd6b | 82 | |
95bee274 IM |
83 | /** |
84 | * PCMachineClass: | |
13fc8343 | 85 | * |
13fc8343 EH |
86 | * Compat fields: |
87 | * | |
16a9e8a5 EH |
88 | * @enforce_aligned_dimm: check that DIMM's address/size is aligned by |
89 | * backend's alignment value if provided | |
13fc8343 EH |
90 | * @acpi_data_size: Size of the chunk of memory at the top of RAM |
91 | * for the BIOS ACPI tables and other BIOS | |
92 | * datastructures. | |
93 | * @gigabyte_align: Make sure that guest addresses aligned at | |
94 | * 1Gbyte boundaries get mapped to host | |
95 | * addresses aligned at 1Gbyte boundaries. This | |
96 | * way we can use 1GByte pages in the host. | |
97 | * | |
95bee274 | 98 | */ |
639f642c | 99 | typedef struct PCMachineClass { |
d5747cac IM |
100 | /*< private >*/ |
101 | MachineClass parent_class; | |
95bee274 IM |
102 | |
103 | /*< public >*/ | |
13fc8343 | 104 | |
13fc8343 | 105 | /* Device configuration: */ |
7102fa70 | 106 | bool pci_enabled; |
13fc8343 | 107 | bool kvmclock_enabled; |
4b9c264b | 108 | const char *default_nic_model; |
13fc8343 EH |
109 | |
110 | /* Compat options: */ | |
111 | ||
112 | /* ACPI compat: */ | |
7102fa70 EH |
113 | bool has_acpi_build; |
114 | bool rsdp_in_ram; | |
13fc8343 EH |
115 | int legacy_acpi_table_size; |
116 | unsigned acpi_data_size; | |
117 | ||
118 | /* SMBIOS compat: */ | |
7102fa70 EH |
119 | bool smbios_defaults; |
120 | bool smbios_legacy_mode; | |
121 | bool smbios_uuid_encoded; | |
13fc8343 EH |
122 | |
123 | /* RAM / address space compat: */ | |
7102fa70 EH |
124 | bool gigabyte_align; |
125 | bool has_reserved_memory; | |
16a9e8a5 | 126 | bool enforce_aligned_dimm; |
13fc8343 | 127 | bool broken_reserved_end; |
36f96c4b HZ |
128 | |
129 | /* TSC rate migration: */ | |
130 | bool save_tsc_khz; | |
679dd1a9 IM |
131 | /* generate legacy CPU hotplug AML */ |
132 | bool legacy_cpu_hotplug; | |
98e753a6 IM |
133 | |
134 | /* use DMA capable linuxboot option rom */ | |
135 | bool linuxboot_dma_enabled; | |
fda672b5 SG |
136 | |
137 | /* use PVH to load kernels that support this feature */ | |
138 | bool pvh_enabled; | |
457cfccc EH |
139 | |
140 | /* Enables contiguous-apic-ID mode */ | |
141 | bool compat_apic_id_mode; | |
639f642c | 142 | } PCMachineClass; |
d5747cac | 143 | |
d5747cac IM |
144 | #define TYPE_PC_MACHINE "generic-pc-machine" |
145 | #define PC_MACHINE(obj) \ | |
146 | OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE) | |
147 | #define PC_MACHINE_GET_CLASS(obj) \ | |
148 | OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE) | |
149 | #define PC_MACHINE_CLASS(klass) \ | |
150 | OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) | |
151 | ||
87ecb68b PB |
152 | /* i8259.c */ |
153 | ||
9aa78c42 | 154 | extern DeviceState *isa_pic; |
48a18b3c | 155 | qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); |
10b61882 | 156 | qemu_irq *kvm_i8259_init(ISABus *bus); |
9aa78c42 JK |
157 | int pic_read_irq(DeviceState *d); |
158 | int pic_get_output(DeviceState *d); | |
87ecb68b | 159 | |
d665d696 PB |
160 | /* ioapic.c */ |
161 | ||
b881fbe9 | 162 | /* Global System Interrupts */ |
96051119 | 163 | |
b881fbe9 | 164 | #define GSI_NUM_PINS IOAPIC_NUM_PINS |
845773ab | 165 | |
b881fbe9 | 166 | typedef struct GSIState { |
43a0db35 | 167 | qemu_irq i8259_irq[ISA_NUM_IRQS]; |
b881fbe9 JK |
168 | qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; |
169 | } GSIState; | |
170 | ||
171 | void gsi_handler(void *opaque, int n, int level); | |
845773ab | 172 | |
87ecb68b | 173 | /* vmport.c */ |
936a6447 | 174 | #define TYPE_VMPORT "vmport" |
d67f679d JK |
175 | typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); |
176 | ||
48a18b3c | 177 | static inline void vmport_init(ISABus *bus) |
6872ef61 | 178 | { |
936a6447 | 179 | isa_create_simple(bus, TYPE_VMPORT); |
6872ef61 | 180 | } |
d67f679d JK |
181 | |
182 | void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); | |
86d86414 BS |
183 | void vmmouse_get_data(uint32_t *data); |
184 | void vmmouse_set_data(const uint32_t *data); | |
87ecb68b | 185 | |
87ecb68b PB |
186 | /* pc.c */ |
187 | extern int fd_bootchk; | |
188 | ||
355023f2 | 189 | bool pc_machine_is_smm_enabled(PCMachineState *pcms); |
8e78eb28 | 190 | void pc_register_ferr_irq(qemu_irq irq); |
845773ab IY |
191 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level); |
192 | ||
4884b7bf | 193 | void pc_cpus_init(PCMachineState *pcms); |
a0628599 | 194 | void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp); |
6f479566 | 195 | void pc_smp_parse(MachineState *ms, QemuOpts *opts); |
3459a625 | 196 | |
e4e8ba04 | 197 | void pc_guest_info_init(PCMachineState *pcms); |
3459a625 | 198 | |
39848901 IM |
199 | #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" |
200 | #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" | |
201 | #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" | |
202 | #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" | |
203 | #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" | |
401f2f3e EV |
204 | #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" |
205 | #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" | |
1466cef3 | 206 | |
39848901 | 207 | |
83d08f26 MT |
208 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, |
209 | MemoryRegion *pci_address_space); | |
39848901 | 210 | |
7bc35e0f | 211 | void xen_load_linux(PCMachineState *pcms); |
5934e216 EH |
212 | void pc_memory_init(PCMachineState *pcms, |
213 | MemoryRegion *system_memory, | |
214 | MemoryRegion *rom_memory, | |
215 | MemoryRegion **ram_memory); | |
9fa99d25 | 216 | uint64_t pc_pci_hole64_start(void); |
0b0cc076 | 217 | qemu_irq pc_allocate_cpu_irq(void); |
48a18b3c HP |
218 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); |
219 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, | |
1611977c | 220 | ISADevice **rtc_state, |
fd53c87c | 221 | bool create_fdctrl, |
7a10ef51 | 222 | bool no_vmport, |
feddd2fd | 223 | bool has_pit, |
3a87d009 | 224 | uint32_t hpet_irqs); |
48a18b3c | 225 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); |
23d30407 | 226 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 227 | BusState *ide0, BusState *ide1, |
63ffb564 | 228 | ISADevice *s); |
4b9c264b | 229 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); |
845773ab | 230 | void pc_pci_device_init(PCIBus *pci_bus); |
8e78eb28 | 231 | |
f885f1ea | 232 | typedef void (*cpu_set_smm_t)(int smm, void *arg); |
f885f1ea | 233 | |
a39e3564 JB |
234 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); |
235 | ||
424e4a87 | 236 | ISADevice *pc_find_fdc0(void); |
bda05509 | 237 | int cmos_get_fd_drive_type(FloppyDriveType fd0); |
424e4a87 | 238 | |
305ae888 GS |
239 | #define FW_CFG_IO_BASE 0x510 |
240 | ||
d812b3d6 EV |
241 | #define PORT92_A20_LINE "a20" |
242 | ||
9d5e77a2 | 243 | /* acpi_piix.c */ |
53b67b30 | 244 | |
a5c82852 AF |
245 | I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
246 | qemu_irq sci_irq, qemu_irq smi_irq, | |
61e66c62 | 247 | int smm_enabled, DeviceState **piix4_pm); |
87ecb68b | 248 | |
16b29ae1 AL |
249 | /* hpet.c */ |
250 | extern int no_hpet; | |
251 | ||
87ecb68b | 252 | /* piix_pci.c */ |
0a3bacf3 JQ |
253 | struct PCII440FXState; |
254 | typedef struct PCII440FXState PCII440FXState; | |
255 | ||
7bb836e4 MT |
256 | #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" |
257 | #define TYPE_I440FX_PCI_DEVICE "i440FX" | |
258 | ||
595a4f07 TC |
259 | #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" |
260 | ||
6103451a PDJ |
261 | /* |
262 | * Reset Control Register: PCI-accessible ISA-Compatible Register at address | |
263 | * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). | |
264 | */ | |
265 | #define RCR_IOPORT 0xcf9 | |
266 | ||
7bb836e4 MT |
267 | PCIBus *i440fx_init(const char *host_type, const char *pci_type, |
268 | PCII440FXState **pi440fx_state, int *piix_devfn, | |
60573079 | 269 | ISABus **isa_bus, qemu_irq *pic, |
aee97b84 AK |
270 | MemoryRegion *address_space_mem, |
271 | MemoryRegion *address_space_io, | |
ae0a5466 | 272 | ram_addr_t ram_size, |
ddaaefb4 | 273 | ram_addr_t below_4g_mem_size, |
39848901 | 274 | ram_addr_t above_4g_mem_size, |
ae0a5466 AK |
275 | MemoryRegion *pci_memory, |
276 | MemoryRegion *ram_memory); | |
87ecb68b | 277 | |
277e9340 | 278 | PCIBus *find_i440fx(void); |
823e675a | 279 | /* piix4.c */ |
b1d8e52e | 280 | extern PCIDevice *piix4_dev; |
142e9787 | 281 | int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); |
87ecb68b | 282 | |
cbc5b5f3 | 283 | /* pc_sysfw.c */ |
ebc29e1b | 284 | void pc_system_flash_create(PCMachineState *pcms); |
5e640a9e | 285 | void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); |
cbc5b5f3 | 286 | |
ac35f13b IM |
287 | /* acpi-build.c */ |
288 | void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, | |
80e5db30 | 289 | const CPUArchIdList *apic_ids, GArray *entry); |
ac35f13b | 290 | |
4c5b10b7 JS |
291 | /* e820 types */ |
292 | #define E820_RAM 1 | |
293 | #define E820_RESERVED 2 | |
294 | #define E820_ACPI 3 | |
295 | #define E820_NVS 4 | |
296 | #define E820_UNUSABLE 5 | |
297 | ||
298 | int e820_add_entry(uint64_t, uint64_t, uint32_t); | |
7bf8ef19 GS |
299 | int e820_get_num_entries(void); |
300 | bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); | |
4c5b10b7 | 301 | |
9bf2650b CH |
302 | extern GlobalProperty pc_compat_4_0[]; |
303 | extern const size_t pc_compat_4_0_len; | |
304 | ||
abd93cc7 MAL |
305 | extern GlobalProperty pc_compat_3_1[]; |
306 | extern const size_t pc_compat_3_1_len; | |
84e060bf | 307 | |
ddb3235d MAL |
308 | extern GlobalProperty pc_compat_3_0[]; |
309 | extern const size_t pc_compat_3_0_len; | |
9b4cf107 | 310 | |
0d47310b MAL |
311 | extern GlobalProperty pc_compat_2_12[]; |
312 | extern const size_t pc_compat_2_12_len; | |
968ee4ad | 313 | |
43df70a9 MAL |
314 | extern GlobalProperty pc_compat_2_11[]; |
315 | extern const size_t pc_compat_2_11_len; | |
df47ce8a | 316 | |
503224f4 MAL |
317 | extern GlobalProperty pc_compat_2_10[]; |
318 | extern const size_t pc_compat_2_10_len; | |
a6fd5b0e | 319 | |
3e803152 MAL |
320 | extern GlobalProperty pc_compat_2_9[]; |
321 | extern const size_t pc_compat_2_9_len; | |
465238d9 | 322 | |
edc24ccd MAL |
323 | extern GlobalProperty pc_compat_2_8[]; |
324 | extern const size_t pc_compat_2_8_len; | |
abc62c89 | 325 | |
5a995064 MAL |
326 | extern GlobalProperty pc_compat_2_7[]; |
327 | extern const size_t pc_compat_2_7_len; | |
14c985cf | 328 | |
ff8f261f MAL |
329 | extern GlobalProperty pc_compat_2_6[]; |
330 | extern const size_t pc_compat_2_6_len; | |
d86c1451 | 331 | |
fe759610 MAL |
332 | extern GlobalProperty pc_compat_2_5[]; |
333 | extern const size_t pc_compat_2_5_len; | |
240240d5 | 334 | |
2f99b9c2 MAL |
335 | extern GlobalProperty pc_compat_2_4[]; |
336 | extern const size_t pc_compat_2_4_len; | |
337 | ||
8995dd90 MAL |
338 | extern GlobalProperty pc_compat_2_3[]; |
339 | extern const size_t pc_compat_2_3_len; | |
340 | ||
1c30044e MAL |
341 | extern GlobalProperty pc_compat_2_2[]; |
342 | extern const size_t pc_compat_2_2_len; | |
343 | ||
c4fc5695 MAL |
344 | extern GlobalProperty pc_compat_2_1[]; |
345 | extern const size_t pc_compat_2_1_len; | |
346 | ||
a310e653 MAL |
347 | extern GlobalProperty pc_compat_2_0[]; |
348 | extern const size_t pc_compat_2_0_len; | |
349 | ||
350 | extern GlobalProperty pc_compat_1_7[]; | |
351 | extern const size_t pc_compat_1_7_len; | |
352 | ||
353 | extern GlobalProperty pc_compat_1_6[]; | |
354 | extern const size_t pc_compat_1_6_len; | |
355 | ||
356 | extern GlobalProperty pc_compat_1_5[]; | |
357 | extern const size_t pc_compat_1_5_len; | |
358 | ||
359 | extern GlobalProperty pc_compat_1_4[]; | |
360 | extern const size_t pc_compat_1_4_len; | |
361 | ||
cd6c1b70 EH |
362 | /* Helper for setting model-id for CPU models that changed model-id |
363 | * depending on QEMU versions up to QEMU 2.4. | |
364 | */ | |
365 | #define PC_CPU_MODEL_IDS(v) \ | |
6c36bddf EH |
366 | { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ |
367 | { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ | |
368 | { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, | |
cd6c1b70 | 369 | |
25519b06 | 370 | #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ |
865906f7 EH |
371 | static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ |
372 | { \ | |
373 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
374 | optsfn(mc); \ | |
865906f7 EH |
375 | mc->init = initfn; \ |
376 | } \ | |
377 | static const TypeInfo pc_machine_type_##suffix = { \ | |
378 | .name = namestr TYPE_MACHINE_SUFFIX, \ | |
379 | .parent = TYPE_PC_MACHINE, \ | |
380 | .class_init = pc_machine_##suffix##_class_init, \ | |
381 | }; \ | |
61f219df EH |
382 | static void pc_machine_init_##suffix(void) \ |
383 | { \ | |
865906f7 | 384 | type_register(&pc_machine_type_##suffix); \ |
61f219df | 385 | } \ |
0e6aac87 | 386 | type_init(pc_machine_init_##suffix) |
61f219df | 387 | |
bd8107d7 | 388 | extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); |
87ecb68b | 389 | #endif |