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Commit | Line | Data |
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54936004 | 1 | /* |
d9f24bf5 | 2 | * RAM allocation and memory access |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
61f3c91a | 9 | * version 2.1 of the License, or (at your option) any later version. |
54936004 FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
14a48c1d | 19 | |
7b31bbc2 | 20 | #include "qemu/osdep.h" |
a8d25326 | 21 | #include "qemu-common.h" |
da34e65c | 22 | #include "qapi/error.h" |
54936004 | 23 | |
f348b6d1 | 24 | #include "qemu/cutils.h" |
084cfca1 | 25 | #include "qemu/cacheflush.h" |
78271684 CF |
26 | |
27 | #ifdef CONFIG_TCG | |
28 | #include "hw/core/tcg-cpu-ops.h" | |
29 | #endif /* CONFIG_TCG */ | |
30 | ||
63c91552 | 31 | #include "exec/exec-all.h" |
51180423 | 32 | #include "exec/target_page.h" |
741da0d3 | 33 | #include "hw/qdev-core.h" |
c7e002c5 | 34 | #include "hw/qdev-properties.h" |
47c8ca53 | 35 | #include "hw/boards.h" |
33c11879 | 36 | #include "hw/xen/xen.h" |
9c17d615 | 37 | #include "sysemu/kvm.h" |
14a48c1d | 38 | #include "sysemu/tcg.h" |
a028edea | 39 | #include "sysemu/qtest.h" |
1de7afc9 PB |
40 | #include "qemu/timer.h" |
41 | #include "qemu/config-file.h" | |
75a34036 | 42 | #include "qemu/error-report.h" |
b6b71cb5 | 43 | #include "qemu/qemu-print.h" |
741da0d3 | 44 | #include "exec/memory.h" |
df43d49c | 45 | #include "exec/ioport.h" |
741da0d3 | 46 | #include "sysemu/dma.h" |
b58c5c2d | 47 | #include "sysemu/hostmem.h" |
79ca7a1b | 48 | #include "sysemu/hw_accel.h" |
741da0d3 | 49 | #include "exec/address-spaces.h" |
9c17d615 | 50 | #include "sysemu/xen-mapcache.h" |
243af022 | 51 | #include "trace/trace-root.h" |
d3a5038c | 52 | |
e2fa71f5 | 53 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE |
e2fa71f5 DDAG |
54 | #include <linux/falloc.h> |
55 | #endif | |
56 | ||
0dc3f44a | 57 | #include "qemu/rcu_queue.h" |
4840f10e | 58 | #include "qemu/main-loop.h" |
3b9bd3f4 | 59 | #include "exec/translate-all.h" |
7615936e | 60 | #include "sysemu/replay.h" |
0cac1b66 | 61 | |
022c62cb | 62 | #include "exec/memory-internal.h" |
220c3ebd | 63 | #include "exec/ram_addr.h" |
508127e2 | 64 | #include "exec/log.h" |
67d95c15 | 65 | |
61c490e2 BM |
66 | #include "qemu/pmem.h" |
67 | ||
9dfeca7c BR |
68 | #include "migration/vmstate.h" |
69 | ||
b35ba30f | 70 | #include "qemu/range.h" |
794e8f30 MT |
71 | #ifndef _WIN32 |
72 | #include "qemu/mmap-alloc.h" | |
73 | #endif | |
b35ba30f | 74 | |
be9b23c4 PX |
75 | #include "monitor/monitor.h" |
76 | ||
ce317be9 JL |
77 | #ifdef CONFIG_LIBDAXCTL |
78 | #include <daxctl/libdaxctl.h> | |
79 | #endif | |
80 | ||
db7b5426 | 81 | //#define DEBUG_SUBPAGE |
1196be37 | 82 | |
0dc3f44a MD |
83 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes |
84 | * are protected by the ramlist lock. | |
85 | */ | |
0d53d9fe | 86 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
87 | |
88 | static MemoryRegion *system_memory; | |
309cb471 | 89 | static MemoryRegion *system_io; |
62152b8a | 90 | |
f6790af6 AK |
91 | AddressSpace address_space_io; |
92 | AddressSpace address_space_memory; | |
2673a5da | 93 | |
acc9d80b | 94 | static MemoryRegion io_mem_unassigned; |
4346ae3e | 95 | |
1db8abb1 PB |
96 | typedef struct PhysPageEntry PhysPageEntry; |
97 | ||
98 | struct PhysPageEntry { | |
9736e55b | 99 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
8b795765 | 100 | uint32_t skip : 6; |
9736e55b | 101 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
8b795765 | 102 | uint32_t ptr : 26; |
1db8abb1 PB |
103 | }; |
104 | ||
8b795765 MT |
105 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
106 | ||
03f49957 | 107 | /* Size of the L2 (and L3, etc) page tables. */ |
57271d63 | 108 | #define ADDR_SPACE_BITS 64 |
03f49957 | 109 | |
026736ce | 110 | #define P_L2_BITS 9 |
03f49957 PB |
111 | #define P_L2_SIZE (1 << P_L2_BITS) |
112 | ||
113 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
114 | ||
115 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
0475d94f | 116 | |
53cb28cb | 117 | typedef struct PhysPageMap { |
79e2b9ae PB |
118 | struct rcu_head rcu; |
119 | ||
53cb28cb MA |
120 | unsigned sections_nb; |
121 | unsigned sections_nb_alloc; | |
122 | unsigned nodes_nb; | |
123 | unsigned nodes_nb_alloc; | |
124 | Node *nodes; | |
125 | MemoryRegionSection *sections; | |
126 | } PhysPageMap; | |
127 | ||
1db8abb1 | 128 | struct AddressSpaceDispatch { |
729633c2 | 129 | MemoryRegionSection *mru_section; |
1db8abb1 PB |
130 | /* This is a multi-level map on the physical address space. |
131 | * The bottom level has pointers to MemoryRegionSections. | |
132 | */ | |
133 | PhysPageEntry phys_map; | |
53cb28cb | 134 | PhysPageMap map; |
1db8abb1 PB |
135 | }; |
136 | ||
90260c6c JK |
137 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
138 | typedef struct subpage_t { | |
139 | MemoryRegion iomem; | |
16620684 | 140 | FlatView *fv; |
90260c6c | 141 | hwaddr base; |
2615fabd | 142 | uint16_t sub_section[]; |
90260c6c JK |
143 | } subpage_t; |
144 | ||
b41aac4f | 145 | #define PHYS_SECTION_UNASSIGNED 0 |
5312bd8b | 146 | |
e2eef170 | 147 | static void io_mem_init(void); |
62152b8a | 148 | static void memory_map_init(void); |
9458a9a1 | 149 | static void tcg_log_global_after_sync(MemoryListener *listener); |
09daed84 | 150 | static void tcg_commit(MemoryListener *listener); |
e2eef170 | 151 | |
32857f4d PM |
152 | /** |
153 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
154 | * @cpu: the CPU whose AddressSpace this is | |
155 | * @as: the AddressSpace itself | |
156 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
157 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
158 | */ | |
159 | struct CPUAddressSpace { | |
160 | CPUState *cpu; | |
161 | AddressSpace *as; | |
162 | struct AddressSpaceDispatch *memory_dispatch; | |
163 | MemoryListener tcg_as_listener; | |
164 | }; | |
165 | ||
8deaf12c GH |
166 | struct DirtyBitmapSnapshot { |
167 | ram_addr_t start; | |
168 | ram_addr_t end; | |
169 | unsigned long dirty[]; | |
170 | }; | |
171 | ||
53cb28cb | 172 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
d6f2ea22 | 173 | { |
101420b8 | 174 | static unsigned alloc_hint = 16; |
53cb28cb | 175 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
c95cfd04 | 176 | map->nodes_nb_alloc = MAX(alloc_hint, map->nodes_nb + nodes); |
53cb28cb | 177 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); |
101420b8 | 178 | alloc_hint = map->nodes_nb_alloc; |
d6f2ea22 | 179 | } |
f7bf5461 AK |
180 | } |
181 | ||
db94604b | 182 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) |
f7bf5461 AK |
183 | { |
184 | unsigned i; | |
8b795765 | 185 | uint32_t ret; |
db94604b PB |
186 | PhysPageEntry e; |
187 | PhysPageEntry *p; | |
f7bf5461 | 188 | |
53cb28cb | 189 | ret = map->nodes_nb++; |
db94604b | 190 | p = map->nodes[ret]; |
f7bf5461 | 191 | assert(ret != PHYS_MAP_NODE_NIL); |
53cb28cb | 192 | assert(ret != map->nodes_nb_alloc); |
db94604b PB |
193 | |
194 | e.skip = leaf ? 0 : 1; | |
195 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
03f49957 | 196 | for (i = 0; i < P_L2_SIZE; ++i) { |
db94604b | 197 | memcpy(&p[i], &e, sizeof(e)); |
d6f2ea22 | 198 | } |
f7bf5461 | 199 | return ret; |
d6f2ea22 AK |
200 | } |
201 | ||
53cb28cb | 202 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
56b15076 | 203 | hwaddr *index, uint64_t *nb, uint16_t leaf, |
2999097b | 204 | int level) |
f7bf5461 AK |
205 | { |
206 | PhysPageEntry *p; | |
03f49957 | 207 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
108c49b8 | 208 | |
9736e55b | 209 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
db94604b | 210 | lp->ptr = phys_map_node_alloc(map, level == 0); |
92e873b9 | 211 | } |
db94604b | 212 | p = map->nodes[lp->ptr]; |
03f49957 | 213 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
f7bf5461 | 214 | |
03f49957 | 215 | while (*nb && lp < &p[P_L2_SIZE]) { |
07f07b31 | 216 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
9736e55b | 217 | lp->skip = 0; |
c19e8800 | 218 | lp->ptr = leaf; |
07f07b31 AK |
219 | *index += step; |
220 | *nb -= step; | |
2999097b | 221 | } else { |
53cb28cb | 222 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
2999097b AK |
223 | } |
224 | ++lp; | |
f7bf5461 AK |
225 | } |
226 | } | |
227 | ||
ac1970fb | 228 | static void phys_page_set(AddressSpaceDispatch *d, |
56b15076 | 229 | hwaddr index, uint64_t nb, |
2999097b | 230 | uint16_t leaf) |
f7bf5461 | 231 | { |
2999097b | 232 | /* Wildly overreserve - it doesn't matter much. */ |
53cb28cb | 233 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
5cd2c5b6 | 234 | |
53cb28cb | 235 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
236 | } |
237 | ||
b35ba30f MT |
238 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
239 | * and update our entry so we can skip it and go directly to the destination. | |
240 | */ | |
efee678d | 241 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes) |
b35ba30f MT |
242 | { |
243 | unsigned valid_ptr = P_L2_SIZE; | |
244 | int valid = 0; | |
245 | PhysPageEntry *p; | |
246 | int i; | |
247 | ||
248 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
249 | return; | |
250 | } | |
251 | ||
252 | p = nodes[lp->ptr]; | |
253 | for (i = 0; i < P_L2_SIZE; i++) { | |
254 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
255 | continue; | |
256 | } | |
257 | ||
258 | valid_ptr = i; | |
259 | valid++; | |
260 | if (p[i].skip) { | |
efee678d | 261 | phys_page_compact(&p[i], nodes); |
b35ba30f MT |
262 | } |
263 | } | |
264 | ||
265 | /* We can only compress if there's only one child. */ | |
266 | if (valid != 1) { | |
267 | return; | |
268 | } | |
269 | ||
270 | assert(valid_ptr < P_L2_SIZE); | |
271 | ||
272 | /* Don't compress if it won't fit in the # of bits we have. */ | |
526ca236 WY |
273 | if (P_L2_LEVELS >= (1 << 6) && |
274 | lp->skip + p[valid_ptr].skip >= (1 << 6)) { | |
b35ba30f MT |
275 | return; |
276 | } | |
277 | ||
278 | lp->ptr = p[valid_ptr].ptr; | |
279 | if (!p[valid_ptr].skip) { | |
280 | /* If our only child is a leaf, make this a leaf. */ | |
281 | /* By design, we should have made this node a leaf to begin with so we | |
282 | * should never reach here. | |
283 | * But since it's so simple to handle this, let's do it just in case we | |
284 | * change this rule. | |
285 | */ | |
286 | lp->skip = 0; | |
287 | } else { | |
288 | lp->skip += p[valid_ptr].skip; | |
289 | } | |
290 | } | |
291 | ||
8629d3fc | 292 | void address_space_dispatch_compact(AddressSpaceDispatch *d) |
b35ba30f | 293 | { |
b35ba30f | 294 | if (d->phys_map.skip) { |
efee678d | 295 | phys_page_compact(&d->phys_map, d->map.nodes); |
b35ba30f MT |
296 | } |
297 | } | |
298 | ||
29cb533d FZ |
299 | static inline bool section_covers_addr(const MemoryRegionSection *section, |
300 | hwaddr addr) | |
301 | { | |
302 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
303 | * the section must cover the entire address space. | |
304 | */ | |
258dfaaa | 305 | return int128_gethi(section->size) || |
29cb533d | 306 | range_covers_byte(section->offset_within_address_space, |
258dfaaa | 307 | int128_getlo(section->size), addr); |
29cb533d FZ |
308 | } |
309 | ||
003a0cf2 | 310 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr) |
92e873b9 | 311 | { |
003a0cf2 PX |
312 | PhysPageEntry lp = d->phys_map, *p; |
313 | Node *nodes = d->map.nodes; | |
314 | MemoryRegionSection *sections = d->map.sections; | |
97115a8d | 315 | hwaddr index = addr >> TARGET_PAGE_BITS; |
31ab2b4a | 316 | int i; |
f1f6e3b8 | 317 | |
9736e55b | 318 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
c19e8800 | 319 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
9affd6fc | 320 | return §ions[PHYS_SECTION_UNASSIGNED]; |
31ab2b4a | 321 | } |
9affd6fc | 322 | p = nodes[lp.ptr]; |
03f49957 | 323 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
5312bd8b | 324 | } |
b35ba30f | 325 | |
29cb533d | 326 | if (section_covers_addr(§ions[lp.ptr], addr)) { |
b35ba30f MT |
327 | return §ions[lp.ptr]; |
328 | } else { | |
329 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
330 | } | |
f3705d53 AK |
331 | } |
332 | ||
79e2b9ae | 333 | /* Called from RCU critical section */ |
c7086b4a | 334 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
90260c6c JK |
335 | hwaddr addr, |
336 | bool resolve_subpage) | |
9f029603 | 337 | { |
d73415a3 | 338 | MemoryRegionSection *section = qatomic_read(&d->mru_section); |
90260c6c JK |
339 | subpage_t *subpage; |
340 | ||
07c114bb PB |
341 | if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] || |
342 | !section_covers_addr(section, addr)) { | |
003a0cf2 | 343 | section = phys_page_find(d, addr); |
d73415a3 | 344 | qatomic_set(&d->mru_section, section); |
729633c2 | 345 | } |
90260c6c JK |
346 | if (resolve_subpage && section->mr->subpage) { |
347 | subpage = container_of(section->mr, subpage_t, iomem); | |
53cb28cb | 348 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
90260c6c JK |
349 | } |
350 | return section; | |
9f029603 JK |
351 | } |
352 | ||
79e2b9ae | 353 | /* Called from RCU critical section */ |
90260c6c | 354 | static MemoryRegionSection * |
c7086b4a | 355 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
90260c6c | 356 | hwaddr *plen, bool resolve_subpage) |
149f54b5 PB |
357 | { |
358 | MemoryRegionSection *section; | |
965eb2fc | 359 | MemoryRegion *mr; |
a87f3954 | 360 | Int128 diff; |
149f54b5 | 361 | |
c7086b4a | 362 | section = address_space_lookup_region(d, addr, resolve_subpage); |
149f54b5 PB |
363 | /* Compute offset within MemoryRegionSection */ |
364 | addr -= section->offset_within_address_space; | |
365 | ||
366 | /* Compute offset within MemoryRegion */ | |
367 | *xlat = addr + section->offset_within_region; | |
368 | ||
965eb2fc | 369 | mr = section->mr; |
b242e0e0 PB |
370 | |
371 | /* MMIO registers can be expected to perform full-width accesses based only | |
372 | * on their address, without considering adjacent registers that could | |
373 | * decode to completely different MemoryRegions. When such registers | |
374 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
375 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
376 | * here. | |
377 | * | |
378 | * If the length is small (as is the case for address_space_ldl/stl), | |
379 | * everything works fine. If the incoming length is large, however, | |
380 | * the caller really has to do the clamping through memory_access_size. | |
381 | */ | |
965eb2fc | 382 | if (memory_region_is_ram(mr)) { |
e4a511f8 | 383 | diff = int128_sub(section->size, int128_make64(addr)); |
965eb2fc PB |
384 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
385 | } | |
149f54b5 PB |
386 | return section; |
387 | } | |
90260c6c | 388 | |
a411c84b PB |
389 | /** |
390 | * address_space_translate_iommu - translate an address through an IOMMU | |
391 | * memory region and then through the target address space. | |
392 | * | |
393 | * @iommu_mr: the IOMMU memory region that we start the translation from | |
394 | * @addr: the address to be translated through the MMU | |
395 | * @xlat: the translated address offset within the destination memory region. | |
396 | * It cannot be %NULL. | |
397 | * @plen_out: valid read/write length of the translated address. It | |
398 | * cannot be %NULL. | |
399 | * @page_mask_out: page mask for the translated address. This | |
400 | * should only be meaningful for IOMMU translated | |
401 | * addresses, since there may be huge pages that this bit | |
402 | * would tell. It can be %NULL if we don't care about it. | |
403 | * @is_write: whether the translation operation is for write | |
404 | * @is_mmio: whether this can be MMIO, set true if it can | |
405 | * @target_as: the address space targeted by the IOMMU | |
2f7b009c | 406 | * @attrs: transaction attributes |
a411c84b PB |
407 | * |
408 | * This function is called from RCU critical section. It is the common | |
409 | * part of flatview_do_translate and address_space_translate_cached. | |
410 | */ | |
411 | static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr, | |
412 | hwaddr *xlat, | |
413 | hwaddr *plen_out, | |
414 | hwaddr *page_mask_out, | |
415 | bool is_write, | |
416 | bool is_mmio, | |
2f7b009c PM |
417 | AddressSpace **target_as, |
418 | MemTxAttrs attrs) | |
a411c84b PB |
419 | { |
420 | MemoryRegionSection *section; | |
421 | hwaddr page_mask = (hwaddr)-1; | |
422 | ||
423 | do { | |
424 | hwaddr addr = *xlat; | |
425 | IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
2c91bcf2 PM |
426 | int iommu_idx = 0; |
427 | IOMMUTLBEntry iotlb; | |
428 | ||
429 | if (imrc->attrs_to_index) { | |
430 | iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | |
431 | } | |
432 | ||
433 | iotlb = imrc->translate(iommu_mr, addr, is_write ? | |
434 | IOMMU_WO : IOMMU_RO, iommu_idx); | |
a411c84b PB |
435 | |
436 | if (!(iotlb.perm & (1 << is_write))) { | |
437 | goto unassigned; | |
438 | } | |
439 | ||
440 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
441 | | (addr & iotlb.addr_mask)); | |
442 | page_mask &= iotlb.addr_mask; | |
443 | *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1); | |
444 | *target_as = iotlb.target_as; | |
445 | ||
446 | section = address_space_translate_internal( | |
447 | address_space_to_dispatch(iotlb.target_as), addr, xlat, | |
448 | plen_out, is_mmio); | |
449 | ||
450 | iommu_mr = memory_region_get_iommu(section->mr); | |
451 | } while (unlikely(iommu_mr)); | |
452 | ||
453 | if (page_mask_out) { | |
454 | *page_mask_out = page_mask; | |
455 | } | |
456 | return *section; | |
457 | ||
458 | unassigned: | |
459 | return (MemoryRegionSection) { .mr = &io_mem_unassigned }; | |
460 | } | |
461 | ||
d5e5fafd PX |
462 | /** |
463 | * flatview_do_translate - translate an address in FlatView | |
464 | * | |
465 | * @fv: the flat view that we want to translate on | |
466 | * @addr: the address to be translated in above address space | |
467 | * @xlat: the translated address offset within memory region. It | |
468 | * cannot be @NULL. | |
469 | * @plen_out: valid read/write length of the translated address. It | |
470 | * can be @NULL when we don't care about it. | |
471 | * @page_mask_out: page mask for the translated address. This | |
472 | * should only be meaningful for IOMMU translated | |
473 | * addresses, since there may be huge pages that this bit | |
474 | * would tell. It can be @NULL if we don't care about it. | |
475 | * @is_write: whether the translation operation is for write | |
476 | * @is_mmio: whether this can be MMIO, set true if it can | |
ad2804d9 | 477 | * @target_as: the address space targeted by the IOMMU |
49e14aa8 | 478 | * @attrs: memory transaction attributes |
d5e5fafd PX |
479 | * |
480 | * This function is called from RCU critical section | |
481 | */ | |
16620684 AK |
482 | static MemoryRegionSection flatview_do_translate(FlatView *fv, |
483 | hwaddr addr, | |
484 | hwaddr *xlat, | |
d5e5fafd PX |
485 | hwaddr *plen_out, |
486 | hwaddr *page_mask_out, | |
16620684 AK |
487 | bool is_write, |
488 | bool is_mmio, | |
49e14aa8 PM |
489 | AddressSpace **target_as, |
490 | MemTxAttrs attrs) | |
052c8fa9 | 491 | { |
052c8fa9 | 492 | MemoryRegionSection *section; |
3df9d748 | 493 | IOMMUMemoryRegion *iommu_mr; |
d5e5fafd PX |
494 | hwaddr plen = (hwaddr)(-1); |
495 | ||
ad2804d9 PB |
496 | if (!plen_out) { |
497 | plen_out = &plen; | |
d5e5fafd | 498 | } |
052c8fa9 | 499 | |
a411c84b PB |
500 | section = address_space_translate_internal( |
501 | flatview_to_dispatch(fv), addr, xlat, | |
502 | plen_out, is_mmio); | |
052c8fa9 | 503 | |
a411c84b PB |
504 | iommu_mr = memory_region_get_iommu(section->mr); |
505 | if (unlikely(iommu_mr)) { | |
506 | return address_space_translate_iommu(iommu_mr, xlat, | |
507 | plen_out, page_mask_out, | |
508 | is_write, is_mmio, | |
2f7b009c | 509 | target_as, attrs); |
052c8fa9 | 510 | } |
d5e5fafd | 511 | if (page_mask_out) { |
a411c84b PB |
512 | /* Not behind an IOMMU, use default page size. */ |
513 | *page_mask_out = ~TARGET_PAGE_MASK; | |
d5e5fafd PX |
514 | } |
515 | ||
a764040c | 516 | return *section; |
052c8fa9 JW |
517 | } |
518 | ||
519 | /* Called from RCU critical section */ | |
a764040c | 520 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, |
7446eb07 | 521 | bool is_write, MemTxAttrs attrs) |
90260c6c | 522 | { |
a764040c | 523 | MemoryRegionSection section; |
076a93d7 | 524 | hwaddr xlat, page_mask; |
30951157 | 525 | |
076a93d7 PX |
526 | /* |
527 | * This can never be MMIO, and we don't really care about plen, | |
528 | * but page mask. | |
529 | */ | |
530 | section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, | |
49e14aa8 PM |
531 | NULL, &page_mask, is_write, false, &as, |
532 | attrs); | |
30951157 | 533 | |
a764040c PX |
534 | /* Illegal translation */ |
535 | if (section.mr == &io_mem_unassigned) { | |
536 | goto iotlb_fail; | |
537 | } | |
30951157 | 538 | |
a764040c PX |
539 | /* Convert memory region offset into address space offset */ |
540 | xlat += section.offset_within_address_space - | |
541 | section.offset_within_region; | |
542 | ||
a764040c | 543 | return (IOMMUTLBEntry) { |
e76bb18f | 544 | .target_as = as, |
076a93d7 PX |
545 | .iova = addr & ~page_mask, |
546 | .translated_addr = xlat & ~page_mask, | |
547 | .addr_mask = page_mask, | |
a764040c PX |
548 | /* IOTLBs are for DMAs, and DMA only allows on RAMs. */ |
549 | .perm = IOMMU_RW, | |
550 | }; | |
551 | ||
552 | iotlb_fail: | |
553 | return (IOMMUTLBEntry) {0}; | |
554 | } | |
555 | ||
556 | /* Called from RCU critical section */ | |
16620684 | 557 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, |
efa99a2f PM |
558 | hwaddr *plen, bool is_write, |
559 | MemTxAttrs attrs) | |
a764040c PX |
560 | { |
561 | MemoryRegion *mr; | |
562 | MemoryRegionSection section; | |
16620684 | 563 | AddressSpace *as = NULL; |
a764040c PX |
564 | |
565 | /* This can be MMIO, so setup MMIO bit. */ | |
d5e5fafd | 566 | section = flatview_do_translate(fv, addr, xlat, plen, NULL, |
49e14aa8 | 567 | is_write, true, &as, attrs); |
a764040c PX |
568 | mr = section.mr; |
569 | ||
fe680d0d | 570 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { |
a87f3954 | 571 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; |
23820dbf | 572 | *plen = MIN(page, *plen); |
a87f3954 PB |
573 | } |
574 | ||
30951157 | 575 | return mr; |
90260c6c JK |
576 | } |
577 | ||
1f871c5e PM |
578 | typedef struct TCGIOMMUNotifier { |
579 | IOMMUNotifier n; | |
580 | MemoryRegion *mr; | |
581 | CPUState *cpu; | |
582 | int iommu_idx; | |
583 | bool active; | |
584 | } TCGIOMMUNotifier; | |
585 | ||
586 | static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb) | |
587 | { | |
588 | TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n); | |
589 | ||
590 | if (!notifier->active) { | |
591 | return; | |
592 | } | |
593 | tlb_flush(notifier->cpu); | |
594 | notifier->active = false; | |
595 | /* We leave the notifier struct on the list to avoid reallocating it later. | |
596 | * Generally the number of IOMMUs a CPU deals with will be small. | |
597 | * In any case we can't unregister the iommu notifier from a notify | |
598 | * callback. | |
599 | */ | |
600 | } | |
601 | ||
602 | static void tcg_register_iommu_notifier(CPUState *cpu, | |
603 | IOMMUMemoryRegion *iommu_mr, | |
604 | int iommu_idx) | |
605 | { | |
606 | /* Make sure this CPU has an IOMMU notifier registered for this | |
607 | * IOMMU/IOMMU index combination, so that we can flush its TLB | |
608 | * when the IOMMU tells us the mappings we've cached have changed. | |
609 | */ | |
610 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); | |
bbf90191 | 611 | TCGIOMMUNotifier *notifier = NULL; |
805d4496 | 612 | int i; |
1f871c5e PM |
613 | |
614 | for (i = 0; i < cpu->iommu_notifiers->len; i++) { | |
5601be3b | 615 | notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); |
1f871c5e PM |
616 | if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) { |
617 | break; | |
618 | } | |
619 | } | |
620 | if (i == cpu->iommu_notifiers->len) { | |
621 | /* Not found, add a new entry at the end of the array */ | |
622 | cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1); | |
5601be3b PM |
623 | notifier = g_new0(TCGIOMMUNotifier, 1); |
624 | g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier; | |
1f871c5e PM |
625 | |
626 | notifier->mr = mr; | |
627 | notifier->iommu_idx = iommu_idx; | |
628 | notifier->cpu = cpu; | |
629 | /* Rather than trying to register interest in the specific part | |
630 | * of the iommu's address space that we've accessed and then | |
631 | * expand it later as subsequent accesses touch more of it, we | |
632 | * just register interest in the whole thing, on the assumption | |
633 | * that iommu reconfiguration will be rare. | |
634 | */ | |
635 | iommu_notifier_init(¬ifier->n, | |
636 | tcg_iommu_unmap_notify, | |
637 | IOMMU_NOTIFIER_UNMAP, | |
638 | 0, | |
639 | HWADDR_MAX, | |
640 | iommu_idx); | |
805d4496 MA |
641 | memory_region_register_iommu_notifier(notifier->mr, ¬ifier->n, |
642 | &error_fatal); | |
1f871c5e PM |
643 | } |
644 | ||
645 | if (!notifier->active) { | |
646 | notifier->active = true; | |
647 | } | |
648 | } | |
649 | ||
d9f24bf5 | 650 | void tcg_iommu_free_notifier_list(CPUState *cpu) |
1f871c5e PM |
651 | { |
652 | /* Destroy the CPU's notifier list */ | |
653 | int i; | |
654 | TCGIOMMUNotifier *notifier; | |
655 | ||
656 | for (i = 0; i < cpu->iommu_notifiers->len; i++) { | |
5601be3b | 657 | notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); |
1f871c5e | 658 | memory_region_unregister_iommu_notifier(notifier->mr, ¬ifier->n); |
5601be3b | 659 | g_free(notifier); |
1f871c5e PM |
660 | } |
661 | g_array_free(cpu->iommu_notifiers, true); | |
662 | } | |
663 | ||
d9f24bf5 PB |
664 | void tcg_iommu_init_notifier_list(CPUState *cpu) |
665 | { | |
666 | cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *)); | |
667 | } | |
668 | ||
79e2b9ae | 669 | /* Called from RCU critical section */ |
90260c6c | 670 | MemoryRegionSection * |
d7898cda | 671 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, |
1f871c5e PM |
672 | hwaddr *xlat, hwaddr *plen, |
673 | MemTxAttrs attrs, int *prot) | |
90260c6c | 674 | { |
30951157 | 675 | MemoryRegionSection *section; |
1f871c5e PM |
676 | IOMMUMemoryRegion *iommu_mr; |
677 | IOMMUMemoryRegionClass *imrc; | |
678 | IOMMUTLBEntry iotlb; | |
679 | int iommu_idx; | |
d73415a3 SH |
680 | AddressSpaceDispatch *d = |
681 | qatomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); | |
d7898cda | 682 | |
1f871c5e PM |
683 | for (;;) { |
684 | section = address_space_translate_internal(d, addr, &addr, plen, false); | |
685 | ||
686 | iommu_mr = memory_region_get_iommu(section->mr); | |
687 | if (!iommu_mr) { | |
688 | break; | |
689 | } | |
690 | ||
691 | imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
692 | ||
693 | iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | |
694 | tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); | |
695 | /* We need all the permissions, so pass IOMMU_NONE so the IOMMU | |
696 | * doesn't short-cut its translation table walk. | |
697 | */ | |
698 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); | |
699 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
700 | | (addr & iotlb.addr_mask)); | |
701 | /* Update the caller's prot bits to remove permissions the IOMMU | |
702 | * is giving us a failure response for. If we get down to no | |
703 | * permissions left at all we can give up now. | |
704 | */ | |
705 | if (!(iotlb.perm & IOMMU_RO)) { | |
706 | *prot &= ~(PAGE_READ | PAGE_EXEC); | |
707 | } | |
708 | if (!(iotlb.perm & IOMMU_WO)) { | |
709 | *prot &= ~PAGE_WRITE; | |
710 | } | |
711 | ||
712 | if (!*prot) { | |
713 | goto translate_fail; | |
714 | } | |
715 | ||
716 | d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as)); | |
717 | } | |
30951157 | 718 | |
3df9d748 | 719 | assert(!memory_region_is_iommu(section->mr)); |
1f871c5e | 720 | *xlat = addr; |
30951157 | 721 | return section; |
1f871c5e PM |
722 | |
723 | translate_fail: | |
724 | return &d->map.sections[PHYS_SECTION_UNASSIGNED]; | |
90260c6c | 725 | } |
1a1562f5 | 726 | |
80ceb07a PX |
727 | void cpu_address_space_init(CPUState *cpu, int asidx, |
728 | const char *prefix, MemoryRegion *mr) | |
09daed84 | 729 | { |
12ebc9a7 | 730 | CPUAddressSpace *newas; |
80ceb07a | 731 | AddressSpace *as = g_new0(AddressSpace, 1); |
87a621d8 | 732 | char *as_name; |
80ceb07a PX |
733 | |
734 | assert(mr); | |
87a621d8 PX |
735 | as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index); |
736 | address_space_init(as, mr, as_name); | |
737 | g_free(as_name); | |
12ebc9a7 PM |
738 | |
739 | /* Target code should have set num_ases before calling us */ | |
740 | assert(asidx < cpu->num_ases); | |
741 | ||
56943e8c PM |
742 | if (asidx == 0) { |
743 | /* address space 0 gets the convenience alias */ | |
744 | cpu->as = as; | |
745 | } | |
746 | ||
12ebc9a7 PM |
747 | /* KVM cannot currently support multiple address spaces. */ |
748 | assert(asidx == 0 || !kvm_enabled()); | |
09daed84 | 749 | |
12ebc9a7 PM |
750 | if (!cpu->cpu_ases) { |
751 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
09daed84 | 752 | } |
32857f4d | 753 | |
12ebc9a7 PM |
754 | newas = &cpu->cpu_ases[asidx]; |
755 | newas->cpu = cpu; | |
756 | newas->as = as; | |
56943e8c | 757 | if (tcg_enabled()) { |
9458a9a1 | 758 | newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync; |
12ebc9a7 PM |
759 | newas->tcg_as_listener.commit = tcg_commit; |
760 | memory_listener_register(&newas->tcg_as_listener, as); | |
56943e8c | 761 | } |
09daed84 | 762 | } |
651a5bc0 PM |
763 | |
764 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
765 | { | |
766 | /* Return the AddressSpace corresponding to the specified index */ | |
767 | return cpu->cpu_ases[asidx].as; | |
768 | } | |
8bca9a03 | 769 | |
6658ffb8 | 770 | /* Add a watchpoint. */ |
75a34036 | 771 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 772 | int flags, CPUWatchpoint **watchpoint) |
6658ffb8 | 773 | { |
c0ce998e | 774 | CPUWatchpoint *wp; |
2e886a24 | 775 | vaddr in_page; |
6658ffb8 | 776 | |
05068c0d | 777 | /* forbid ranges which are empty or run off the end of the address space */ |
07e2863d | 778 | if (len == 0 || (addr + len - 1) < addr) { |
75a34036 AF |
779 | error_report("tried to set invalid watchpoint at %" |
780 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
b4051334 AL |
781 | return -EINVAL; |
782 | } | |
7267c094 | 783 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
784 | |
785 | wp->vaddr = addr; | |
05068c0d | 786 | wp->len = len; |
a1d1bb31 AL |
787 | wp->flags = flags; |
788 | ||
2dc9f411 | 789 | /* keep all GDB-injected watchpoints in front */ |
ff4700b0 AF |
790 | if (flags & BP_GDB) { |
791 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
792 | } else { | |
793 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
794 | } | |
6658ffb8 | 795 | |
2e886a24 AB |
796 | in_page = -(addr | TARGET_PAGE_MASK); |
797 | if (len <= in_page) { | |
798 | tlb_flush_page(cpu, addr); | |
799 | } else { | |
800 | tlb_flush(cpu); | |
801 | } | |
a1d1bb31 AL |
802 | |
803 | if (watchpoint) | |
804 | *watchpoint = wp; | |
805 | return 0; | |
6658ffb8 PB |
806 | } |
807 | ||
a1d1bb31 | 808 | /* Remove a specific watchpoint. */ |
75a34036 | 809 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 810 | int flags) |
6658ffb8 | 811 | { |
a1d1bb31 | 812 | CPUWatchpoint *wp; |
6658ffb8 | 813 | |
ff4700b0 | 814 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 815 | if (addr == wp->vaddr && len == wp->len |
6e140f28 | 816 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
75a34036 | 817 | cpu_watchpoint_remove_by_ref(cpu, wp); |
6658ffb8 PB |
818 | return 0; |
819 | } | |
820 | } | |
a1d1bb31 | 821 | return -ENOENT; |
6658ffb8 PB |
822 | } |
823 | ||
a1d1bb31 | 824 | /* Remove a specific watchpoint by reference. */ |
75a34036 | 825 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) |
a1d1bb31 | 826 | { |
ff4700b0 | 827 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); |
7d03f82f | 828 | |
31b030d4 | 829 | tlb_flush_page(cpu, watchpoint->vaddr); |
a1d1bb31 | 830 | |
7267c094 | 831 | g_free(watchpoint); |
a1d1bb31 AL |
832 | } |
833 | ||
834 | /* Remove all matching watchpoints. */ | |
75a34036 | 835 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 836 | { |
c0ce998e | 837 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 838 | |
ff4700b0 | 839 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { |
75a34036 AF |
840 | if (wp->flags & mask) { |
841 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
842 | } | |
c0ce998e | 843 | } |
7d03f82f | 844 | } |
05068c0d | 845 | |
79fc8d45 | 846 | #ifdef CONFIG_TCG |
05068c0d PM |
847 | /* Return true if this watchpoint address matches the specified |
848 | * access (ie the address range covered by the watchpoint overlaps | |
849 | * partially or completely with the address range covered by the | |
850 | * access). | |
851 | */ | |
56ad8b00 RH |
852 | static inline bool watchpoint_address_matches(CPUWatchpoint *wp, |
853 | vaddr addr, vaddr len) | |
05068c0d PM |
854 | { |
855 | /* We know the lengths are non-zero, but a little caution is | |
856 | * required to avoid errors in the case where the range ends | |
857 | * exactly at the top of the address space and so addr + len | |
858 | * wraps round to zero. | |
859 | */ | |
860 | vaddr wpend = wp->vaddr + wp->len - 1; | |
861 | vaddr addrend = addr + len - 1; | |
862 | ||
863 | return !(addr > wpend || wp->vaddr > addrend); | |
864 | } | |
865 | ||
56ad8b00 RH |
866 | /* Return flags for watchpoints that match addr + prot. */ |
867 | int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) | |
868 | { | |
869 | CPUWatchpoint *wp; | |
870 | int ret = 0; | |
871 | ||
872 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
9835936d | 873 | if (watchpoint_address_matches(wp, addr, len)) { |
56ad8b00 RH |
874 | ret |= wp->flags; |
875 | } | |
876 | } | |
877 | return ret; | |
878 | } | |
7d03f82f | 879 | |
79fc8d45 CF |
880 | /* Generate a debug exception if a watchpoint has been hit. */ |
881 | void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, | |
882 | MemTxAttrs attrs, int flags, uintptr_t ra) | |
883 | { | |
884 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
885 | CPUWatchpoint *wp; | |
886 | ||
887 | assert(tcg_enabled()); | |
888 | if (cpu->watchpoint_hit) { | |
889 | /* | |
890 | * We re-entered the check after replacing the TB. | |
891 | * Now raise the debug interrupt so that it will | |
892 | * trigger after the current instruction. | |
893 | */ | |
894 | qemu_mutex_lock_iothread(); | |
895 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); | |
896 | qemu_mutex_unlock_iothread(); | |
897 | return; | |
898 | } | |
899 | ||
78271684 | 900 | if (cc->tcg_ops->adjust_watchpoint_address) { |
9ea9087b | 901 | /* this is currently used only by ARM BE32 */ |
78271684 | 902 | addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); |
9ea9087b | 903 | } |
79fc8d45 CF |
904 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
905 | if (watchpoint_address_matches(wp, addr, len) | |
906 | && (wp->flags & flags)) { | |
907 | if (replay_running_debug()) { | |
908 | /* | |
909 | * Don't process the watchpoints when we are | |
910 | * in a reverse debugging operation. | |
911 | */ | |
912 | replay_breakpoint(); | |
913 | return; | |
914 | } | |
915 | if (flags == BP_MEM_READ) { | |
916 | wp->flags |= BP_WATCHPOINT_HIT_READ; | |
917 | } else { | |
918 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; | |
919 | } | |
920 | wp->hitaddr = MAX(addr, wp->vaddr); | |
921 | wp->hitattrs = attrs; | |
922 | if (!cpu->watchpoint_hit) { | |
78271684 CF |
923 | if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpoint && |
924 | !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { | |
79fc8d45 CF |
925 | wp->flags &= ~BP_WATCHPOINT_HIT; |
926 | continue; | |
927 | } | |
928 | cpu->watchpoint_hit = wp; | |
929 | ||
930 | mmap_lock(); | |
931 | tb_check_watchpoint(cpu, ra); | |
932 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
933 | cpu->exception_index = EXCP_DEBUG; | |
934 | mmap_unlock(); | |
935 | cpu_loop_exit_restore(cpu, ra); | |
936 | } else { | |
937 | /* Force execution of one insn next time. */ | |
c0ae396a | 938 | cpu->cflags_next_tb = 1 | curr_cflags(cpu); |
79fc8d45 CF |
939 | mmap_unlock(); |
940 | if (ra) { | |
941 | cpu_restore_state(cpu, ra, true); | |
942 | } | |
943 | cpu_loop_exit_noexc(cpu); | |
944 | } | |
945 | } | |
946 | } else { | |
947 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
948 | } | |
949 | } | |
950 | } | |
951 | ||
952 | #endif /* CONFIG_TCG */ | |
953 | ||
0dc3f44a | 954 | /* Called from RCU critical section */ |
041603fe PB |
955 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
956 | { | |
957 | RAMBlock *block; | |
958 | ||
d73415a3 | 959 | block = qatomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 960 | if (block && addr - block->offset < block->max_length) { |
68851b98 | 961 | return block; |
041603fe | 962 | } |
99e15582 | 963 | RAMBLOCK_FOREACH(block) { |
9b8424d5 | 964 | if (addr - block->offset < block->max_length) { |
041603fe PB |
965 | goto found; |
966 | } | |
967 | } | |
968 | ||
969 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
970 | abort(); | |
971 | ||
972 | found: | |
43771539 PB |
973 | /* It is safe to write mru_block outside the iothread lock. This |
974 | * is what happens: | |
975 | * | |
976 | * mru_block = xxx | |
977 | * rcu_read_unlock() | |
978 | * xxx removed from list | |
979 | * rcu_read_lock() | |
980 | * read mru_block | |
981 | * mru_block = NULL; | |
982 | * call_rcu(reclaim_ramblock, xxx); | |
983 | * rcu_read_unlock() | |
984 | * | |
d73415a3 | 985 | * qatomic_rcu_set is not needed here. The block was already published |
43771539 PB |
986 | * when it was placed into the list. Here we're just making an extra |
987 | * copy of the pointer. | |
988 | */ | |
041603fe PB |
989 | ram_list.mru_block = block; |
990 | return block; | |
991 | } | |
992 | ||
a2f4d5be | 993 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
d24981d3 | 994 | { |
9a13565d | 995 | CPUState *cpu; |
041603fe | 996 | ram_addr_t start1; |
a2f4d5be JQ |
997 | RAMBlock *block; |
998 | ram_addr_t end; | |
999 | ||
f28d0dfd | 1000 | assert(tcg_enabled()); |
a2f4d5be JQ |
1001 | end = TARGET_PAGE_ALIGN(start + length); |
1002 | start &= TARGET_PAGE_MASK; | |
d24981d3 | 1003 | |
694ea274 | 1004 | RCU_READ_LOCK_GUARD(); |
041603fe PB |
1005 | block = qemu_get_ram_block(start); |
1006 | assert(block == qemu_get_ram_block(end - 1)); | |
1240be24 | 1007 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); |
9a13565d PC |
1008 | CPU_FOREACH(cpu) { |
1009 | tlb_reset_dirty(cpu, start1, length); | |
1010 | } | |
d24981d3 JQ |
1011 | } |
1012 | ||
5579c7f3 | 1013 | /* Note: start and end must be within the same ram block. */ |
03eebc9e SH |
1014 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, |
1015 | ram_addr_t length, | |
1016 | unsigned client) | |
1ccde1cb | 1017 | { |
5b82b703 | 1018 | DirtyMemoryBlocks *blocks; |
25aa6b37 | 1019 | unsigned long end, page, start_page; |
5b82b703 | 1020 | bool dirty = false; |
077874e0 PX |
1021 | RAMBlock *ramblock; |
1022 | uint64_t mr_offset, mr_size; | |
03eebc9e SH |
1023 | |
1024 | if (length == 0) { | |
1025 | return false; | |
1026 | } | |
f23db169 | 1027 | |
03eebc9e | 1028 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; |
25aa6b37 MB |
1029 | start_page = start >> TARGET_PAGE_BITS; |
1030 | page = start_page; | |
5b82b703 | 1031 | |
694ea274 | 1032 | WITH_RCU_READ_LOCK_GUARD() { |
d73415a3 | 1033 | blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); |
694ea274 DDAG |
1034 | ramblock = qemu_get_ram_block(start); |
1035 | /* Range sanity check on the ramblock */ | |
1036 | assert(start >= ramblock->offset && | |
1037 | start + length <= ramblock->offset + ramblock->used_length); | |
5b82b703 | 1038 | |
694ea274 DDAG |
1039 | while (page < end) { |
1040 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1041 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1042 | unsigned long num = MIN(end - page, | |
1043 | DIRTY_MEMORY_BLOCK_SIZE - offset); | |
5b82b703 | 1044 | |
694ea274 DDAG |
1045 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], |
1046 | offset, num); | |
1047 | page += num; | |
1048 | } | |
5b82b703 | 1049 | |
25aa6b37 MB |
1050 | mr_offset = (ram_addr_t)(start_page << TARGET_PAGE_BITS) - ramblock->offset; |
1051 | mr_size = (end - start_page) << TARGET_PAGE_BITS; | |
694ea274 | 1052 | memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size); |
5b82b703 SH |
1053 | } |
1054 | ||
03eebc9e | 1055 | if (dirty && tcg_enabled()) { |
a2f4d5be | 1056 | tlb_reset_dirty_range_all(start, length); |
5579c7f3 | 1057 | } |
03eebc9e SH |
1058 | |
1059 | return dirty; | |
1ccde1cb FB |
1060 | } |
1061 | ||
8deaf12c | 1062 | DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty |
5dea4079 | 1063 | (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client) |
8deaf12c GH |
1064 | { |
1065 | DirtyMemoryBlocks *blocks; | |
5dea4079 | 1066 | ram_addr_t start = memory_region_get_ram_addr(mr) + offset; |
8deaf12c GH |
1067 | unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL); |
1068 | ram_addr_t first = QEMU_ALIGN_DOWN(start, align); | |
1069 | ram_addr_t last = QEMU_ALIGN_UP(start + length, align); | |
1070 | DirtyBitmapSnapshot *snap; | |
1071 | unsigned long page, end, dest; | |
1072 | ||
1073 | snap = g_malloc0(sizeof(*snap) + | |
1074 | ((last - first) >> (TARGET_PAGE_BITS + 3))); | |
1075 | snap->start = first; | |
1076 | snap->end = last; | |
1077 | ||
1078 | page = first >> TARGET_PAGE_BITS; | |
1079 | end = last >> TARGET_PAGE_BITS; | |
1080 | dest = 0; | |
1081 | ||
694ea274 | 1082 | WITH_RCU_READ_LOCK_GUARD() { |
d73415a3 | 1083 | blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); |
8deaf12c | 1084 | |
694ea274 DDAG |
1085 | while (page < end) { |
1086 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1087 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1088 | unsigned long num = MIN(end - page, | |
1089 | DIRTY_MEMORY_BLOCK_SIZE - offset); | |
8deaf12c | 1090 | |
694ea274 DDAG |
1091 | assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL))); |
1092 | assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL))); | |
1093 | offset >>= BITS_PER_LEVEL; | |
8deaf12c | 1094 | |
694ea274 DDAG |
1095 | bitmap_copy_and_clear_atomic(snap->dirty + dest, |
1096 | blocks->blocks[idx] + offset, | |
1097 | num); | |
1098 | page += num; | |
1099 | dest += num >> BITS_PER_LEVEL; | |
1100 | } | |
8deaf12c GH |
1101 | } |
1102 | ||
8deaf12c GH |
1103 | if (tcg_enabled()) { |
1104 | tlb_reset_dirty_range_all(start, length); | |
1105 | } | |
1106 | ||
077874e0 PX |
1107 | memory_region_clear_dirty_bitmap(mr, offset, length); |
1108 | ||
8deaf12c GH |
1109 | return snap; |
1110 | } | |
1111 | ||
1112 | bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, | |
1113 | ram_addr_t start, | |
1114 | ram_addr_t length) | |
1115 | { | |
1116 | unsigned long page, end; | |
1117 | ||
1118 | assert(start >= snap->start); | |
1119 | assert(start + length <= snap->end); | |
1120 | ||
1121 | end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS; | |
1122 | page = (start - snap->start) >> TARGET_PAGE_BITS; | |
1123 | ||
1124 | while (page < end) { | |
1125 | if (test_bit(page, snap->dirty)) { | |
1126 | return true; | |
1127 | } | |
1128 | page++; | |
1129 | } | |
1130 | return false; | |
1131 | } | |
1132 | ||
79e2b9ae | 1133 | /* Called from RCU critical section */ |
bb0e627a | 1134 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
8f5db641 | 1135 | MemoryRegionSection *section) |
e5548617 | 1136 | { |
8f5db641 RH |
1137 | AddressSpaceDispatch *d = flatview_to_dispatch(section->fv); |
1138 | return section - d->map.sections; | |
e5548617 | 1139 | } |
8da3ff18 | 1140 | |
b797ab1a WY |
1141 | static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end, |
1142 | uint16_t section); | |
16620684 | 1143 | static subpage_t *subpage_init(FlatView *fv, hwaddr base); |
54688b1e | 1144 | |
53cb28cb MA |
1145 | static uint16_t phys_section_add(PhysPageMap *map, |
1146 | MemoryRegionSection *section) | |
5312bd8b | 1147 | { |
68f3f65b PB |
1148 | /* The physical section number is ORed with a page-aligned |
1149 | * pointer to produce the iotlb entries. Thus it should | |
1150 | * never overflow into the page-aligned value. | |
1151 | */ | |
53cb28cb | 1152 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
68f3f65b | 1153 | |
53cb28cb MA |
1154 | if (map->sections_nb == map->sections_nb_alloc) { |
1155 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
1156 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
1157 | map->sections_nb_alloc); | |
5312bd8b | 1158 | } |
53cb28cb | 1159 | map->sections[map->sections_nb] = *section; |
dfde4e6e | 1160 | memory_region_ref(section->mr); |
53cb28cb | 1161 | return map->sections_nb++; |
5312bd8b AK |
1162 | } |
1163 | ||
058bc4b5 PB |
1164 | static void phys_section_destroy(MemoryRegion *mr) |
1165 | { | |
55b4e80b DS |
1166 | bool have_sub_page = mr->subpage; |
1167 | ||
dfde4e6e PB |
1168 | memory_region_unref(mr); |
1169 | ||
55b4e80b | 1170 | if (have_sub_page) { |
058bc4b5 | 1171 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
b4fefef9 | 1172 | object_unref(OBJECT(&subpage->iomem)); |
058bc4b5 PB |
1173 | g_free(subpage); |
1174 | } | |
1175 | } | |
1176 | ||
6092666e | 1177 | static void phys_sections_free(PhysPageMap *map) |
5312bd8b | 1178 | { |
9affd6fc PB |
1179 | while (map->sections_nb > 0) { |
1180 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
058bc4b5 PB |
1181 | phys_section_destroy(section->mr); |
1182 | } | |
9affd6fc PB |
1183 | g_free(map->sections); |
1184 | g_free(map->nodes); | |
5312bd8b AK |
1185 | } |
1186 | ||
9950322a | 1187 | static void register_subpage(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1188 | { |
9950322a | 1189 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
0f0cb164 | 1190 | subpage_t *subpage; |
a8170e5e | 1191 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 1192 | & TARGET_PAGE_MASK; |
003a0cf2 | 1193 | MemoryRegionSection *existing = phys_page_find(d, base); |
0f0cb164 AK |
1194 | MemoryRegionSection subsection = { |
1195 | .offset_within_address_space = base, | |
052e87b0 | 1196 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 1197 | }; |
a8170e5e | 1198 | hwaddr start, end; |
0f0cb164 | 1199 | |
f3705d53 | 1200 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 1201 | |
f3705d53 | 1202 | if (!(existing->mr->subpage)) { |
16620684 AK |
1203 | subpage = subpage_init(fv, base); |
1204 | subsection.fv = fv; | |
0f0cb164 | 1205 | subsection.mr = &subpage->iomem; |
ac1970fb | 1206 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
53cb28cb | 1207 | phys_section_add(&d->map, &subsection)); |
0f0cb164 | 1208 | } else { |
f3705d53 | 1209 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
1210 | } |
1211 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 1212 | end = start + int128_get64(section->size) - 1; |
53cb28cb MA |
1213 | subpage_register(subpage, start, end, |
1214 | phys_section_add(&d->map, section)); | |
0f0cb164 AK |
1215 | } |
1216 | ||
1217 | ||
9950322a | 1218 | static void register_multipage(FlatView *fv, |
052e87b0 | 1219 | MemoryRegionSection *section) |
33417e70 | 1220 | { |
9950322a | 1221 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
a8170e5e | 1222 | hwaddr start_addr = section->offset_within_address_space; |
53cb28cb | 1223 | uint16_t section_index = phys_section_add(&d->map, section); |
052e87b0 PB |
1224 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
1225 | TARGET_PAGE_BITS)); | |
dd81124b | 1226 | |
733d5ef5 PB |
1227 | assert(num_pages); |
1228 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
1229 | } |
1230 | ||
494d1997 WY |
1231 | /* |
1232 | * The range in *section* may look like this: | |
1233 | * | |
1234 | * |s|PPPPPPP|s| | |
1235 | * | |
1236 | * where s stands for subpage and P for page. | |
1237 | */ | |
8629d3fc | 1238 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1239 | { |
494d1997 | 1240 | MemoryRegionSection remain = *section; |
052e87b0 | 1241 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 1242 | |
494d1997 WY |
1243 | /* register first subpage */ |
1244 | if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { | |
1245 | uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space) | |
1246 | - remain.offset_within_address_space; | |
733d5ef5 | 1247 | |
494d1997 | 1248 | MemoryRegionSection now = remain; |
052e87b0 | 1249 | now.size = int128_min(int128_make64(left), now.size); |
9950322a | 1250 | register_subpage(fv, &now); |
494d1997 WY |
1251 | if (int128_eq(remain.size, now.size)) { |
1252 | return; | |
1253 | } | |
052e87b0 PB |
1254 | remain.size = int128_sub(remain.size, now.size); |
1255 | remain.offset_within_address_space += int128_get64(now.size); | |
1256 | remain.offset_within_region += int128_get64(now.size); | |
494d1997 WY |
1257 | } |
1258 | ||
1259 | /* register whole pages */ | |
1260 | if (int128_ge(remain.size, page_size)) { | |
1261 | MemoryRegionSection now = remain; | |
1262 | now.size = int128_and(now.size, int128_neg(page_size)); | |
1263 | register_multipage(fv, &now); | |
1264 | if (int128_eq(remain.size, now.size)) { | |
1265 | return; | |
69b67646 | 1266 | } |
494d1997 WY |
1267 | remain.size = int128_sub(remain.size, now.size); |
1268 | remain.offset_within_address_space += int128_get64(now.size); | |
1269 | remain.offset_within_region += int128_get64(now.size); | |
0f0cb164 | 1270 | } |
494d1997 WY |
1271 | |
1272 | /* register last subpage */ | |
1273 | register_subpage(fv, &remain); | |
0f0cb164 AK |
1274 | } |
1275 | ||
62a2744c SY |
1276 | void qemu_flush_coalesced_mmio_buffer(void) |
1277 | { | |
1278 | if (kvm_enabled()) | |
1279 | kvm_flush_coalesced_mmio_buffer(); | |
1280 | } | |
1281 | ||
b2a8658e UD |
1282 | void qemu_mutex_lock_ramlist(void) |
1283 | { | |
1284 | qemu_mutex_lock(&ram_list.mutex); | |
1285 | } | |
1286 | ||
1287 | void qemu_mutex_unlock_ramlist(void) | |
1288 | { | |
1289 | qemu_mutex_unlock(&ram_list.mutex); | |
1290 | } | |
1291 | ||
be9b23c4 PX |
1292 | void ram_block_dump(Monitor *mon) |
1293 | { | |
1294 | RAMBlock *block; | |
1295 | char *psize; | |
1296 | ||
694ea274 | 1297 | RCU_READ_LOCK_GUARD(); |
be9b23c4 PX |
1298 | monitor_printf(mon, "%24s %8s %18s %18s %18s\n", |
1299 | "Block Name", "PSize", "Offset", "Used", "Total"); | |
1300 | RAMBLOCK_FOREACH(block) { | |
1301 | psize = size_to_str(block->page_size); | |
1302 | monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64 | |
1303 | " 0x%016" PRIx64 "\n", block->idstr, psize, | |
1304 | (uint64_t)block->offset, | |
1305 | (uint64_t)block->used_length, | |
1306 | (uint64_t)block->max_length); | |
1307 | g_free(psize); | |
1308 | } | |
be9b23c4 PX |
1309 | } |
1310 | ||
9c607668 AK |
1311 | #ifdef __linux__ |
1312 | /* | |
1313 | * FIXME TOCTTOU: this iterates over memory backends' mem-path, which | |
1314 | * may or may not name the same files / on the same filesystem now as | |
1315 | * when we actually open and map them. Iterate over the file | |
1316 | * descriptors instead, and use qemu_fd_getpagesize(). | |
1317 | */ | |
905b7ee4 | 1318 | static int find_min_backend_pagesize(Object *obj, void *opaque) |
9c607668 | 1319 | { |
9c607668 AK |
1320 | long *hpsize_min = opaque; |
1321 | ||
1322 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
7d5489e6 DG |
1323 | HostMemoryBackend *backend = MEMORY_BACKEND(obj); |
1324 | long hpsize = host_memory_backend_pagesize(backend); | |
2b108085 | 1325 | |
7d5489e6 | 1326 | if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) { |
0de6e2a3 | 1327 | *hpsize_min = hpsize; |
9c607668 AK |
1328 | } |
1329 | } | |
1330 | ||
1331 | return 0; | |
1332 | } | |
1333 | ||
905b7ee4 DH |
1334 | static int find_max_backend_pagesize(Object *obj, void *opaque) |
1335 | { | |
1336 | long *hpsize_max = opaque; | |
1337 | ||
1338 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
1339 | HostMemoryBackend *backend = MEMORY_BACKEND(obj); | |
1340 | long hpsize = host_memory_backend_pagesize(backend); | |
1341 | ||
1342 | if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) { | |
1343 | *hpsize_max = hpsize; | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | /* | |
1351 | * TODO: We assume right now that all mapped host memory backends are | |
1352 | * used as RAM, however some might be used for different purposes. | |
1353 | */ | |
1354 | long qemu_minrampagesize(void) | |
9c607668 AK |
1355 | { |
1356 | long hpsize = LONG_MAX; | |
ad1172d8 | 1357 | Object *memdev_root = object_resolve_path("/objects", NULL); |
9c607668 | 1358 | |
ad1172d8 | 1359 | object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize); |
9c607668 AK |
1360 | return hpsize; |
1361 | } | |
905b7ee4 DH |
1362 | |
1363 | long qemu_maxrampagesize(void) | |
1364 | { | |
ad1172d8 | 1365 | long pagesize = 0; |
905b7ee4 DH |
1366 | Object *memdev_root = object_resolve_path("/objects", NULL); |
1367 | ||
ad1172d8 | 1368 | object_child_foreach(memdev_root, find_max_backend_pagesize, &pagesize); |
905b7ee4 DH |
1369 | return pagesize; |
1370 | } | |
9c607668 | 1371 | #else |
905b7ee4 DH |
1372 | long qemu_minrampagesize(void) |
1373 | { | |
038adc2f | 1374 | return qemu_real_host_page_size; |
905b7ee4 DH |
1375 | } |
1376 | long qemu_maxrampagesize(void) | |
9c607668 | 1377 | { |
038adc2f | 1378 | return qemu_real_host_page_size; |
9c607668 AK |
1379 | } |
1380 | #endif | |
1381 | ||
d5dbde46 | 1382 | #ifdef CONFIG_POSIX |
d6af99c9 HZ |
1383 | static int64_t get_file_size(int fd) |
1384 | { | |
72d41eb4 SH |
1385 | int64_t size; |
1386 | #if defined(__linux__) | |
1387 | struct stat st; | |
1388 | ||
1389 | if (fstat(fd, &st) < 0) { | |
1390 | return -errno; | |
1391 | } | |
1392 | ||
1393 | /* Special handling for devdax character devices */ | |
1394 | if (S_ISCHR(st.st_mode)) { | |
1395 | g_autofree char *subsystem_path = NULL; | |
1396 | g_autofree char *subsystem = NULL; | |
1397 | ||
1398 | subsystem_path = g_strdup_printf("/sys/dev/char/%d:%d/subsystem", | |
1399 | major(st.st_rdev), minor(st.st_rdev)); | |
1400 | subsystem = g_file_read_link(subsystem_path, NULL); | |
1401 | ||
1402 | if (subsystem && g_str_has_suffix(subsystem, "/dax")) { | |
1403 | g_autofree char *size_path = NULL; | |
1404 | g_autofree char *size_str = NULL; | |
1405 | ||
1406 | size_path = g_strdup_printf("/sys/dev/char/%d:%d/size", | |
1407 | major(st.st_rdev), minor(st.st_rdev)); | |
1408 | ||
1409 | if (g_file_get_contents(size_path, &size_str, NULL, NULL)) { | |
1410 | return g_ascii_strtoll(size_str, NULL, 0); | |
1411 | } | |
1412 | } | |
1413 | } | |
1414 | #endif /* defined(__linux__) */ | |
1415 | ||
1416 | /* st.st_size may be zero for special files yet lseek(2) works */ | |
1417 | size = lseek(fd, 0, SEEK_END); | |
d6af99c9 HZ |
1418 | if (size < 0) { |
1419 | return -errno; | |
1420 | } | |
1421 | return size; | |
1422 | } | |
1423 | ||
ce317be9 JL |
1424 | static int64_t get_file_align(int fd) |
1425 | { | |
1426 | int64_t align = -1; | |
1427 | #if defined(__linux__) && defined(CONFIG_LIBDAXCTL) | |
1428 | struct stat st; | |
1429 | ||
1430 | if (fstat(fd, &st) < 0) { | |
1431 | return -errno; | |
1432 | } | |
1433 | ||
1434 | /* Special handling for devdax character devices */ | |
1435 | if (S_ISCHR(st.st_mode)) { | |
1436 | g_autofree char *path = NULL; | |
1437 | g_autofree char *rpath = NULL; | |
1438 | struct daxctl_ctx *ctx; | |
1439 | struct daxctl_region *region; | |
1440 | int rc = 0; | |
1441 | ||
1442 | path = g_strdup_printf("/sys/dev/char/%d:%d", | |
1443 | major(st.st_rdev), minor(st.st_rdev)); | |
1444 | rpath = realpath(path, NULL); | |
1445 | ||
1446 | rc = daxctl_new(&ctx); | |
1447 | if (rc) { | |
1448 | return -1; | |
1449 | } | |
1450 | ||
1451 | daxctl_region_foreach(ctx, region) { | |
1452 | if (strstr(rpath, daxctl_region_get_path(region))) { | |
1453 | align = daxctl_region_get_align(region); | |
1454 | break; | |
1455 | } | |
1456 | } | |
1457 | daxctl_unref(ctx); | |
1458 | } | |
1459 | #endif /* defined(__linux__) && defined(CONFIG_LIBDAXCTL) */ | |
1460 | ||
1461 | return align; | |
1462 | } | |
1463 | ||
8d37b030 MAL |
1464 | static int file_ram_open(const char *path, |
1465 | const char *region_name, | |
369d6dc4 | 1466 | bool readonly, |
8d37b030 MAL |
1467 | bool *created, |
1468 | Error **errp) | |
c902760f MT |
1469 | { |
1470 | char *filename; | |
8ca761f6 PF |
1471 | char *sanitized_name; |
1472 | char *c; | |
5c3ece79 | 1473 | int fd = -1; |
c902760f | 1474 | |
8d37b030 | 1475 | *created = false; |
fd97fd44 | 1476 | for (;;) { |
369d6dc4 | 1477 | fd = open(path, readonly ? O_RDONLY : O_RDWR); |
fd97fd44 MA |
1478 | if (fd >= 0) { |
1479 | /* @path names an existing file, use it */ | |
1480 | break; | |
8d31d6b6 | 1481 | } |
fd97fd44 MA |
1482 | if (errno == ENOENT) { |
1483 | /* @path names a file that doesn't exist, create it */ | |
1484 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1485 | if (fd >= 0) { | |
8d37b030 | 1486 | *created = true; |
fd97fd44 MA |
1487 | break; |
1488 | } | |
1489 | } else if (errno == EISDIR) { | |
1490 | /* @path names a directory, create a file there */ | |
1491 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
8d37b030 | 1492 | sanitized_name = g_strdup(region_name); |
fd97fd44 MA |
1493 | for (c = sanitized_name; *c != '\0'; c++) { |
1494 | if (*c == '/') { | |
1495 | *c = '_'; | |
1496 | } | |
1497 | } | |
8ca761f6 | 1498 | |
fd97fd44 MA |
1499 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, |
1500 | sanitized_name); | |
1501 | g_free(sanitized_name); | |
8d31d6b6 | 1502 | |
fd97fd44 MA |
1503 | fd = mkstemp(filename); |
1504 | if (fd >= 0) { | |
1505 | unlink(filename); | |
1506 | g_free(filename); | |
1507 | break; | |
1508 | } | |
1509 | g_free(filename); | |
8d31d6b6 | 1510 | } |
fd97fd44 MA |
1511 | if (errno != EEXIST && errno != EINTR) { |
1512 | error_setg_errno(errp, errno, | |
1513 | "can't open backing store %s for guest RAM", | |
1514 | path); | |
8d37b030 | 1515 | return -1; |
fd97fd44 MA |
1516 | } |
1517 | /* | |
1518 | * Try again on EINTR and EEXIST. The latter happens when | |
1519 | * something else creates the file between our two open(). | |
1520 | */ | |
8d31d6b6 | 1521 | } |
c902760f | 1522 | |
8d37b030 MAL |
1523 | return fd; |
1524 | } | |
1525 | ||
1526 | static void *file_ram_alloc(RAMBlock *block, | |
1527 | ram_addr_t memory, | |
1528 | int fd, | |
369d6dc4 | 1529 | bool readonly, |
8d37b030 | 1530 | bool truncate, |
44a4ff31 | 1531 | off_t offset, |
8d37b030 MAL |
1532 | Error **errp) |
1533 | { | |
1534 | void *area; | |
1535 | ||
863e9621 | 1536 | block->page_size = qemu_fd_getpagesize(fd); |
98376843 HZ |
1537 | if (block->mr->align % block->page_size) { |
1538 | error_setg(errp, "alignment 0x%" PRIx64 | |
1539 | " must be multiples of page size 0x%zx", | |
1540 | block->mr->align, block->page_size); | |
1541 | return NULL; | |
61362b71 DH |
1542 | } else if (block->mr->align && !is_power_of_2(block->mr->align)) { |
1543 | error_setg(errp, "alignment 0x%" PRIx64 | |
1544 | " must be a power of two", block->mr->align); | |
1545 | return NULL; | |
98376843 HZ |
1546 | } |
1547 | block->mr->align = MAX(block->page_size, block->mr->align); | |
8360668e HZ |
1548 | #if defined(__s390x__) |
1549 | if (kvm_enabled()) { | |
1550 | block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN); | |
1551 | } | |
1552 | #endif | |
fd97fd44 | 1553 | |
863e9621 | 1554 | if (memory < block->page_size) { |
fd97fd44 | 1555 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " |
863e9621 DDAG |
1556 | "or larger than page size 0x%zx", |
1557 | memory, block->page_size); | |
8d37b030 | 1558 | return NULL; |
1775f111 HZ |
1559 | } |
1560 | ||
863e9621 | 1561 | memory = ROUND_UP(memory, block->page_size); |
c902760f MT |
1562 | |
1563 | /* | |
1564 | * ftruncate is not supported by hugetlbfs in older | |
1565 | * hosts, so don't bother bailing out on errors. | |
1566 | * If anything goes wrong with it under other filesystems, | |
1567 | * mmap will fail. | |
d6af99c9 HZ |
1568 | * |
1569 | * Do not truncate the non-empty backend file to avoid corrupting | |
1570 | * the existing data in the file. Disabling shrinking is not | |
1571 | * enough. For example, the current vNVDIMM implementation stores | |
1572 | * the guest NVDIMM labels at the end of the backend file. If the | |
1573 | * backend file is later extended, QEMU will not be able to find | |
1574 | * those labels. Therefore, extending the non-empty backend file | |
1575 | * is disabled as well. | |
c902760f | 1576 | */ |
8d37b030 | 1577 | if (truncate && ftruncate(fd, memory)) { |
9742bf26 | 1578 | perror("ftruncate"); |
7f56e740 | 1579 | } |
c902760f | 1580 | |
369d6dc4 | 1581 | area = qemu_ram_mmap(fd, memory, block->mr->align, readonly, |
44a4ff31 JR |
1582 | block->flags & RAM_SHARED, block->flags & RAM_PMEM, |
1583 | offset); | |
c902760f | 1584 | if (area == MAP_FAILED) { |
7f56e740 | 1585 | error_setg_errno(errp, errno, |
fd97fd44 | 1586 | "unable to map backing store for guest RAM"); |
8d37b030 | 1587 | return NULL; |
c902760f | 1588 | } |
ef36fa14 | 1589 | |
04b16653 | 1590 | block->fd = fd; |
c902760f MT |
1591 | return area; |
1592 | } | |
1593 | #endif | |
1594 | ||
154cc9ea DDAG |
1595 | /* Allocate space within the ram_addr_t space that governs the |
1596 | * dirty bitmaps. | |
1597 | * Called with the ramlist lock held. | |
1598 | */ | |
d17b5288 | 1599 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
1600 | { |
1601 | RAMBlock *block, *next_block; | |
3e837b2c | 1602 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 1603 | |
49cd9ac6 SH |
1604 | assert(size != 0); /* it would hand out same offset multiple times */ |
1605 | ||
0dc3f44a | 1606 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { |
04b16653 | 1607 | return 0; |
0d53d9fe | 1608 | } |
04b16653 | 1609 | |
99e15582 | 1610 | RAMBLOCK_FOREACH(block) { |
154cc9ea | 1611 | ram_addr_t candidate, next = RAM_ADDR_MAX; |
04b16653 | 1612 | |
801110ab DDAG |
1613 | /* Align blocks to start on a 'long' in the bitmap |
1614 | * which makes the bitmap sync'ing take the fast path. | |
1615 | */ | |
154cc9ea | 1616 | candidate = block->offset + block->max_length; |
801110ab | 1617 | candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS); |
04b16653 | 1618 | |
154cc9ea DDAG |
1619 | /* Search for the closest following block |
1620 | * and find the gap. | |
1621 | */ | |
99e15582 | 1622 | RAMBLOCK_FOREACH(next_block) { |
154cc9ea | 1623 | if (next_block->offset >= candidate) { |
04b16653 AW |
1624 | next = MIN(next, next_block->offset); |
1625 | } | |
1626 | } | |
154cc9ea DDAG |
1627 | |
1628 | /* If it fits remember our place and remember the size | |
1629 | * of gap, but keep going so that we might find a smaller | |
1630 | * gap to fill so avoiding fragmentation. | |
1631 | */ | |
1632 | if (next - candidate >= size && next - candidate < mingap) { | |
1633 | offset = candidate; | |
1634 | mingap = next - candidate; | |
04b16653 | 1635 | } |
154cc9ea DDAG |
1636 | |
1637 | trace_find_ram_offset_loop(size, candidate, offset, next, mingap); | |
04b16653 | 1638 | } |
3e837b2c AW |
1639 | |
1640 | if (offset == RAM_ADDR_MAX) { | |
1641 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1642 | (uint64_t)size); | |
1643 | abort(); | |
1644 | } | |
1645 | ||
154cc9ea DDAG |
1646 | trace_find_ram_offset(size, offset); |
1647 | ||
04b16653 AW |
1648 | return offset; |
1649 | } | |
1650 | ||
c136180c | 1651 | static unsigned long last_ram_page(void) |
d17b5288 AW |
1652 | { |
1653 | RAMBlock *block; | |
1654 | ram_addr_t last = 0; | |
1655 | ||
694ea274 | 1656 | RCU_READ_LOCK_GUARD(); |
99e15582 | 1657 | RAMBLOCK_FOREACH(block) { |
62be4e3a | 1658 | last = MAX(last, block->offset + block->max_length); |
0d53d9fe | 1659 | } |
b8c48993 | 1660 | return last >> TARGET_PAGE_BITS; |
d17b5288 AW |
1661 | } |
1662 | ||
ddb97f1d JB |
1663 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
1664 | { | |
1665 | int ret; | |
ddb97f1d JB |
1666 | |
1667 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
47c8ca53 | 1668 | if (!machine_dump_guest_core(current_machine)) { |
ddb97f1d JB |
1669 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
1670 | if (ret) { | |
1671 | perror("qemu_madvise"); | |
1672 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1673 | "but dump_guest_core=off specified\n"); | |
1674 | } | |
1675 | } | |
1676 | } | |
1677 | ||
422148d3 DDAG |
1678 | const char *qemu_ram_get_idstr(RAMBlock *rb) |
1679 | { | |
1680 | return rb->idstr; | |
1681 | } | |
1682 | ||
754cb9c0 YK |
1683 | void *qemu_ram_get_host_addr(RAMBlock *rb) |
1684 | { | |
1685 | return rb->host; | |
1686 | } | |
1687 | ||
1688 | ram_addr_t qemu_ram_get_offset(RAMBlock *rb) | |
1689 | { | |
1690 | return rb->offset; | |
1691 | } | |
1692 | ||
1693 | ram_addr_t qemu_ram_get_used_length(RAMBlock *rb) | |
1694 | { | |
1695 | return rb->used_length; | |
1696 | } | |
1697 | ||
463a4ac2 DDAG |
1698 | bool qemu_ram_is_shared(RAMBlock *rb) |
1699 | { | |
1700 | return rb->flags & RAM_SHARED; | |
1701 | } | |
1702 | ||
2ce16640 DDAG |
1703 | /* Note: Only set at the start of postcopy */ |
1704 | bool qemu_ram_is_uf_zeroable(RAMBlock *rb) | |
1705 | { | |
1706 | return rb->flags & RAM_UF_ZEROPAGE; | |
1707 | } | |
1708 | ||
1709 | void qemu_ram_set_uf_zeroable(RAMBlock *rb) | |
1710 | { | |
1711 | rb->flags |= RAM_UF_ZEROPAGE; | |
1712 | } | |
1713 | ||
b895de50 CLG |
1714 | bool qemu_ram_is_migratable(RAMBlock *rb) |
1715 | { | |
1716 | return rb->flags & RAM_MIGRATABLE; | |
1717 | } | |
1718 | ||
1719 | void qemu_ram_set_migratable(RAMBlock *rb) | |
1720 | { | |
1721 | rb->flags |= RAM_MIGRATABLE; | |
1722 | } | |
1723 | ||
1724 | void qemu_ram_unset_migratable(RAMBlock *rb) | |
1725 | { | |
1726 | rb->flags &= ~RAM_MIGRATABLE; | |
1727 | } | |
1728 | ||
ae3a7047 | 1729 | /* Called with iothread lock held. */ |
fa53a0e5 | 1730 | void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev) |
20cfe881 | 1731 | { |
fa53a0e5 | 1732 | RAMBlock *block; |
20cfe881 | 1733 | |
c5705a77 AK |
1734 | assert(new_block); |
1735 | assert(!new_block->idstr[0]); | |
84b89d78 | 1736 | |
09e5ab63 AL |
1737 | if (dev) { |
1738 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
1739 | if (id) { |
1740 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 1741 | g_free(id); |
84b89d78 CM |
1742 | } |
1743 | } | |
1744 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1745 | ||
694ea274 | 1746 | RCU_READ_LOCK_GUARD(); |
99e15582 | 1747 | RAMBLOCK_FOREACH(block) { |
fa53a0e5 GA |
1748 | if (block != new_block && |
1749 | !strcmp(block->idstr, new_block->idstr)) { | |
84b89d78 CM |
1750 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
1751 | new_block->idstr); | |
1752 | abort(); | |
1753 | } | |
1754 | } | |
c5705a77 AK |
1755 | } |
1756 | ||
ae3a7047 | 1757 | /* Called with iothread lock held. */ |
fa53a0e5 | 1758 | void qemu_ram_unset_idstr(RAMBlock *block) |
20cfe881 | 1759 | { |
ae3a7047 MD |
1760 | /* FIXME: arch_init.c assumes that this is not called throughout |
1761 | * migration. Ignore the problem since hot-unplug during migration | |
1762 | * does not work anyway. | |
1763 | */ | |
20cfe881 HT |
1764 | if (block) { |
1765 | memset(block->idstr, 0, sizeof(block->idstr)); | |
1766 | } | |
1767 | } | |
1768 | ||
863e9621 DDAG |
1769 | size_t qemu_ram_pagesize(RAMBlock *rb) |
1770 | { | |
1771 | return rb->page_size; | |
1772 | } | |
1773 | ||
67f11b5c DDAG |
1774 | /* Returns the largest size of page in use */ |
1775 | size_t qemu_ram_pagesize_largest(void) | |
1776 | { | |
1777 | RAMBlock *block; | |
1778 | size_t largest = 0; | |
1779 | ||
99e15582 | 1780 | RAMBLOCK_FOREACH(block) { |
67f11b5c DDAG |
1781 | largest = MAX(largest, qemu_ram_pagesize(block)); |
1782 | } | |
1783 | ||
1784 | return largest; | |
1785 | } | |
1786 | ||
8490fc78 LC |
1787 | static int memory_try_enable_merging(void *addr, size_t len) |
1788 | { | |
75cc7f01 | 1789 | if (!machine_mem_merge(current_machine)) { |
8490fc78 LC |
1790 | /* disabled by the user */ |
1791 | return 0; | |
1792 | } | |
1793 | ||
1794 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1795 | } | |
1796 | ||
62be4e3a MT |
1797 | /* Only legal before guest might have detected the memory size: e.g. on |
1798 | * incoming migration, or right after reset. | |
1799 | * | |
1800 | * As memory core doesn't know how is memory accessed, it is up to | |
1801 | * resize callback to update device state and/or add assertions to detect | |
1802 | * misuse, if necessary. | |
1803 | */ | |
fa53a0e5 | 1804 | int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) |
62be4e3a | 1805 | { |
ce4adc0b DH |
1806 | const ram_addr_t unaligned_size = newsize; |
1807 | ||
62be4e3a MT |
1808 | assert(block); |
1809 | ||
4ed023ce | 1810 | newsize = HOST_PAGE_ALIGN(newsize); |
129ddaf3 | 1811 | |
62be4e3a | 1812 | if (block->used_length == newsize) { |
ce4adc0b DH |
1813 | /* |
1814 | * We don't have to resize the ram block (which only knows aligned | |
1815 | * sizes), however, we have to notify if the unaligned size changed. | |
1816 | */ | |
1817 | if (unaligned_size != memory_region_size(block->mr)) { | |
1818 | memory_region_set_size(block->mr, unaligned_size); | |
1819 | if (block->resized) { | |
1820 | block->resized(block->idstr, unaligned_size, block->host); | |
1821 | } | |
1822 | } | |
62be4e3a MT |
1823 | return 0; |
1824 | } | |
1825 | ||
1826 | if (!(block->flags & RAM_RESIZEABLE)) { | |
1827 | error_setg_errno(errp, EINVAL, | |
a3a92908 PG |
1828 | "Size mismatch: %s: 0x" RAM_ADDR_FMT |
1829 | " != 0x" RAM_ADDR_FMT, block->idstr, | |
62be4e3a MT |
1830 | newsize, block->used_length); |
1831 | return -EINVAL; | |
1832 | } | |
1833 | ||
1834 | if (block->max_length < newsize) { | |
1835 | error_setg_errno(errp, EINVAL, | |
a3a92908 | 1836 | "Size too large: %s: 0x" RAM_ADDR_FMT |
62be4e3a MT |
1837 | " > 0x" RAM_ADDR_FMT, block->idstr, |
1838 | newsize, block->max_length); | |
1839 | return -EINVAL; | |
1840 | } | |
1841 | ||
1842 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); | |
1843 | block->used_length = newsize; | |
58d2707e PB |
1844 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, |
1845 | DIRTY_CLIENTS_ALL); | |
ce4adc0b | 1846 | memory_region_set_size(block->mr, unaligned_size); |
62be4e3a | 1847 | if (block->resized) { |
ce4adc0b | 1848 | block->resized(block->idstr, unaligned_size, block->host); |
62be4e3a MT |
1849 | } |
1850 | return 0; | |
1851 | } | |
1852 | ||
61c490e2 BM |
1853 | /* |
1854 | * Trigger sync on the given ram block for range [start, start + length] | |
1855 | * with the backing store if one is available. | |
1856 | * Otherwise no-op. | |
1857 | * @Note: this is supposed to be a synchronous op. | |
1858 | */ | |
ab7e41e6 | 1859 | void qemu_ram_msync(RAMBlock *block, ram_addr_t start, ram_addr_t length) |
61c490e2 | 1860 | { |
61c490e2 BM |
1861 | /* The requested range should fit in within the block range */ |
1862 | g_assert((start + length) <= block->used_length); | |
1863 | ||
1864 | #ifdef CONFIG_LIBPMEM | |
1865 | /* The lack of support for pmem should not block the sync */ | |
1866 | if (ramblock_is_pmem(block)) { | |
5d4c9549 | 1867 | void *addr = ramblock_ptr(block, start); |
61c490e2 BM |
1868 | pmem_persist(addr, length); |
1869 | return; | |
1870 | } | |
1871 | #endif | |
1872 | if (block->fd >= 0) { | |
1873 | /** | |
1874 | * Case there is no support for PMEM or the memory has not been | |
1875 | * specified as persistent (or is not one) - use the msync. | |
1876 | * Less optimal but still achieves the same goal | |
1877 | */ | |
5d4c9549 | 1878 | void *addr = ramblock_ptr(block, start); |
61c490e2 BM |
1879 | if (qemu_msync(addr, length, block->fd)) { |
1880 | warn_report("%s: failed to sync memory range: start: " | |
1881 | RAM_ADDR_FMT " length: " RAM_ADDR_FMT, | |
1882 | __func__, start, length); | |
1883 | } | |
1884 | } | |
1885 | } | |
1886 | ||
5b82b703 SH |
1887 | /* Called with ram_list.mutex held */ |
1888 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
1889 | ram_addr_t new_ram_size) | |
1890 | { | |
1891 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
1892 | DIRTY_MEMORY_BLOCK_SIZE); | |
1893 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
1894 | DIRTY_MEMORY_BLOCK_SIZE); | |
1895 | int i; | |
1896 | ||
1897 | /* Only need to extend if block count increased */ | |
1898 | if (new_num_blocks <= old_num_blocks) { | |
1899 | return; | |
1900 | } | |
1901 | ||
1902 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
1903 | DirtyMemoryBlocks *old_blocks; | |
1904 | DirtyMemoryBlocks *new_blocks; | |
1905 | int j; | |
1906 | ||
d73415a3 | 1907 | old_blocks = qatomic_rcu_read(&ram_list.dirty_memory[i]); |
5b82b703 SH |
1908 | new_blocks = g_malloc(sizeof(*new_blocks) + |
1909 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
1910 | ||
1911 | if (old_num_blocks) { | |
1912 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
1913 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
1914 | } | |
1915 | ||
1916 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
1917 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
1918 | } | |
1919 | ||
d73415a3 | 1920 | qatomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); |
5b82b703 SH |
1921 | |
1922 | if (old_blocks) { | |
1923 | g_free_rcu(old_blocks, rcu); | |
1924 | } | |
1925 | } | |
1926 | } | |
1927 | ||
06329cce | 1928 | static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared) |
c5705a77 | 1929 | { |
e1c57ab8 | 1930 | RAMBlock *block; |
0d53d9fe | 1931 | RAMBlock *last_block = NULL; |
2152f5ca | 1932 | ram_addr_t old_ram_size, new_ram_size; |
37aa7a0e | 1933 | Error *err = NULL; |
2152f5ca | 1934 | |
b8c48993 | 1935 | old_ram_size = last_ram_page(); |
c5705a77 | 1936 | |
b2a8658e | 1937 | qemu_mutex_lock_ramlist(); |
9b8424d5 | 1938 | new_block->offset = find_ram_offset(new_block->max_length); |
e1c57ab8 PB |
1939 | |
1940 | if (!new_block->host) { | |
1941 | if (xen_enabled()) { | |
9b8424d5 | 1942 | xen_ram_alloc(new_block->offset, new_block->max_length, |
37aa7a0e MA |
1943 | new_block->mr, &err); |
1944 | if (err) { | |
1945 | error_propagate(errp, err); | |
1946 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1947 | return; |
37aa7a0e | 1948 | } |
e1c57ab8 | 1949 | } else { |
25459eb7 DH |
1950 | new_block->host = qemu_anon_ram_alloc(new_block->max_length, |
1951 | &new_block->mr->align, | |
1952 | shared); | |
39228250 | 1953 | if (!new_block->host) { |
ef701d7b HT |
1954 | error_setg_errno(errp, errno, |
1955 | "cannot set up guest memory '%s'", | |
1956 | memory_region_name(new_block->mr)); | |
1957 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1958 | return; |
39228250 | 1959 | } |
9b8424d5 | 1960 | memory_try_enable_merging(new_block->host, new_block->max_length); |
6977dfe6 | 1961 | } |
c902760f | 1962 | } |
94a6b54f | 1963 | |
dd631697 LZ |
1964 | new_ram_size = MAX(old_ram_size, |
1965 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
1966 | if (new_ram_size > old_ram_size) { | |
5b82b703 | 1967 | dirty_memory_extend(old_ram_size, new_ram_size); |
dd631697 | 1968 | } |
0d53d9fe MD |
1969 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, |
1970 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
1971 | * tail, so save the last element in last_block. | |
1972 | */ | |
99e15582 | 1973 | RAMBLOCK_FOREACH(block) { |
0d53d9fe | 1974 | last_block = block; |
9b8424d5 | 1975 | if (block->max_length < new_block->max_length) { |
abb26d63 PB |
1976 | break; |
1977 | } | |
1978 | } | |
1979 | if (block) { | |
0dc3f44a | 1980 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); |
0d53d9fe | 1981 | } else if (last_block) { |
0dc3f44a | 1982 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); |
0d53d9fe | 1983 | } else { /* list is empty */ |
0dc3f44a | 1984 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); |
abb26d63 | 1985 | } |
0d6d3c87 | 1986 | ram_list.mru_block = NULL; |
94a6b54f | 1987 | |
0dc3f44a MD |
1988 | /* Write list before version */ |
1989 | smp_wmb(); | |
f798b07f | 1990 | ram_list.version++; |
b2a8658e | 1991 | qemu_mutex_unlock_ramlist(); |
f798b07f | 1992 | |
9b8424d5 | 1993 | cpu_physical_memory_set_dirty_range(new_block->offset, |
58d2707e PB |
1994 | new_block->used_length, |
1995 | DIRTY_CLIENTS_ALL); | |
94a6b54f | 1996 | |
a904c911 PB |
1997 | if (new_block->host) { |
1998 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
1999 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
a028edea AB |
2000 | /* |
2001 | * MADV_DONTFORK is also needed by KVM in absence of synchronous MMU | |
2002 | * Configure it unless the machine is a qtest server, in which case | |
2003 | * KVM is not used and it may be forked (eg for fuzzing purposes). | |
2004 | */ | |
2005 | if (!qtest_enabled()) { | |
2006 | qemu_madvise(new_block->host, new_block->max_length, | |
2007 | QEMU_MADV_DONTFORK); | |
2008 | } | |
0987d735 | 2009 | ram_block_notify_add(new_block->host, new_block->max_length); |
e1c57ab8 | 2010 | } |
94a6b54f | 2011 | } |
e9a1ab19 | 2012 | |
d5dbde46 | 2013 | #ifdef CONFIG_POSIX |
38b3362d | 2014 | RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, |
44a4ff31 JR |
2015 | uint32_t ram_flags, int fd, off_t offset, |
2016 | bool readonly, Error **errp) | |
e1c57ab8 PB |
2017 | { |
2018 | RAMBlock *new_block; | |
ef701d7b | 2019 | Error *local_err = NULL; |
ce317be9 | 2020 | int64_t file_size, file_align; |
e1c57ab8 | 2021 | |
a4de8552 JH |
2022 | /* Just support these ram flags by now. */ |
2023 | assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0); | |
2024 | ||
e1c57ab8 | 2025 | if (xen_enabled()) { |
7f56e740 | 2026 | error_setg(errp, "-mem-path not supported with Xen"); |
528f46af | 2027 | return NULL; |
e1c57ab8 PB |
2028 | } |
2029 | ||
e45e7ae2 MAL |
2030 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
2031 | error_setg(errp, | |
2032 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
2033 | return NULL; | |
2034 | } | |
2035 | ||
4ed023ce | 2036 | size = HOST_PAGE_ALIGN(size); |
8d37b030 MAL |
2037 | file_size = get_file_size(fd); |
2038 | if (file_size > 0 && file_size < size) { | |
c001c3b3 | 2039 | error_setg(errp, "backing store size 0x%" PRIx64 |
8d37b030 | 2040 | " does not match 'size' option 0x" RAM_ADDR_FMT, |
c001c3b3 | 2041 | file_size, size); |
8d37b030 MAL |
2042 | return NULL; |
2043 | } | |
2044 | ||
ce317be9 JL |
2045 | file_align = get_file_align(fd); |
2046 | if (file_align > 0 && mr && file_align > mr->align) { | |
2047 | error_setg(errp, "backing store align 0x%" PRIx64 | |
5f509751 | 2048 | " is larger than 'align' option 0x%" PRIx64, |
ce317be9 JL |
2049 | file_align, mr->align); |
2050 | return NULL; | |
2051 | } | |
2052 | ||
e1c57ab8 PB |
2053 | new_block = g_malloc0(sizeof(*new_block)); |
2054 | new_block->mr = mr; | |
9b8424d5 MT |
2055 | new_block->used_length = size; |
2056 | new_block->max_length = size; | |
cbfc0171 | 2057 | new_block->flags = ram_flags; |
369d6dc4 | 2058 | new_block->host = file_ram_alloc(new_block, size, fd, readonly, |
44a4ff31 | 2059 | !file_size, offset, errp); |
7f56e740 PB |
2060 | if (!new_block->host) { |
2061 | g_free(new_block); | |
528f46af | 2062 | return NULL; |
7f56e740 PB |
2063 | } |
2064 | ||
cbfc0171 | 2065 | ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED); |
ef701d7b HT |
2066 | if (local_err) { |
2067 | g_free(new_block); | |
2068 | error_propagate(errp, local_err); | |
528f46af | 2069 | return NULL; |
ef701d7b | 2070 | } |
528f46af | 2071 | return new_block; |
38b3362d MAL |
2072 | |
2073 | } | |
2074 | ||
2075 | ||
2076 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, | |
cbfc0171 | 2077 | uint32_t ram_flags, const char *mem_path, |
369d6dc4 | 2078 | bool readonly, Error **errp) |
38b3362d MAL |
2079 | { |
2080 | int fd; | |
2081 | bool created; | |
2082 | RAMBlock *block; | |
2083 | ||
369d6dc4 SH |
2084 | fd = file_ram_open(mem_path, memory_region_name(mr), readonly, &created, |
2085 | errp); | |
38b3362d MAL |
2086 | if (fd < 0) { |
2087 | return NULL; | |
2088 | } | |
2089 | ||
44a4ff31 | 2090 | block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, 0, readonly, errp); |
38b3362d MAL |
2091 | if (!block) { |
2092 | if (created) { | |
2093 | unlink(mem_path); | |
2094 | } | |
2095 | close(fd); | |
2096 | return NULL; | |
2097 | } | |
2098 | ||
2099 | return block; | |
e1c57ab8 | 2100 | } |
0b183fc8 | 2101 | #endif |
e1c57ab8 | 2102 | |
62be4e3a | 2103 | static |
528f46af FZ |
2104 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, |
2105 | void (*resized)(const char*, | |
2106 | uint64_t length, | |
2107 | void *host), | |
06329cce | 2108 | void *host, bool resizeable, bool share, |
528f46af | 2109 | MemoryRegion *mr, Error **errp) |
e1c57ab8 PB |
2110 | { |
2111 | RAMBlock *new_block; | |
ef701d7b | 2112 | Error *local_err = NULL; |
e1c57ab8 | 2113 | |
4ed023ce DDAG |
2114 | size = HOST_PAGE_ALIGN(size); |
2115 | max_size = HOST_PAGE_ALIGN(max_size); | |
e1c57ab8 PB |
2116 | new_block = g_malloc0(sizeof(*new_block)); |
2117 | new_block->mr = mr; | |
62be4e3a | 2118 | new_block->resized = resized; |
9b8424d5 MT |
2119 | new_block->used_length = size; |
2120 | new_block->max_length = max_size; | |
62be4e3a | 2121 | assert(max_size >= size); |
e1c57ab8 | 2122 | new_block->fd = -1; |
038adc2f | 2123 | new_block->page_size = qemu_real_host_page_size; |
e1c57ab8 PB |
2124 | new_block->host = host; |
2125 | if (host) { | |
7bd4f430 | 2126 | new_block->flags |= RAM_PREALLOC; |
e1c57ab8 | 2127 | } |
62be4e3a MT |
2128 | if (resizeable) { |
2129 | new_block->flags |= RAM_RESIZEABLE; | |
2130 | } | |
06329cce | 2131 | ram_block_add(new_block, &local_err, share); |
ef701d7b HT |
2132 | if (local_err) { |
2133 | g_free(new_block); | |
2134 | error_propagate(errp, local_err); | |
528f46af | 2135 | return NULL; |
ef701d7b | 2136 | } |
528f46af | 2137 | return new_block; |
e1c57ab8 PB |
2138 | } |
2139 | ||
528f46af | 2140 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
62be4e3a MT |
2141 | MemoryRegion *mr, Error **errp) |
2142 | { | |
06329cce MA |
2143 | return qemu_ram_alloc_internal(size, size, NULL, host, false, |
2144 | false, mr, errp); | |
62be4e3a MT |
2145 | } |
2146 | ||
06329cce MA |
2147 | RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share, |
2148 | MemoryRegion *mr, Error **errp) | |
6977dfe6 | 2149 | { |
06329cce MA |
2150 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, |
2151 | share, mr, errp); | |
62be4e3a MT |
2152 | } |
2153 | ||
528f46af | 2154 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, |
62be4e3a MT |
2155 | void (*resized)(const char*, |
2156 | uint64_t length, | |
2157 | void *host), | |
2158 | MemoryRegion *mr, Error **errp) | |
2159 | { | |
06329cce MA |
2160 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, |
2161 | false, mr, errp); | |
6977dfe6 YT |
2162 | } |
2163 | ||
43771539 PB |
2164 | static void reclaim_ramblock(RAMBlock *block) |
2165 | { | |
2166 | if (block->flags & RAM_PREALLOC) { | |
2167 | ; | |
2168 | } else if (xen_enabled()) { | |
2169 | xen_invalidate_map_cache_entry(block->host); | |
2170 | #ifndef _WIN32 | |
2171 | } else if (block->fd >= 0) { | |
53adb9d4 | 2172 | qemu_ram_munmap(block->fd, block->host, block->max_length); |
43771539 PB |
2173 | close(block->fd); |
2174 | #endif | |
2175 | } else { | |
2176 | qemu_anon_ram_free(block->host, block->max_length); | |
2177 | } | |
2178 | g_free(block); | |
2179 | } | |
2180 | ||
f1060c55 | 2181 | void qemu_ram_free(RAMBlock *block) |
e9a1ab19 | 2182 | { |
85bc2a15 MAL |
2183 | if (!block) { |
2184 | return; | |
2185 | } | |
2186 | ||
0987d735 PB |
2187 | if (block->host) { |
2188 | ram_block_notify_remove(block->host, block->max_length); | |
2189 | } | |
2190 | ||
b2a8658e | 2191 | qemu_mutex_lock_ramlist(); |
f1060c55 FZ |
2192 | QLIST_REMOVE_RCU(block, next); |
2193 | ram_list.mru_block = NULL; | |
2194 | /* Write list before version */ | |
2195 | smp_wmb(); | |
2196 | ram_list.version++; | |
2197 | call_rcu(block, reclaim_ramblock, rcu); | |
b2a8658e | 2198 | qemu_mutex_unlock_ramlist(); |
e9a1ab19 FB |
2199 | } |
2200 | ||
cd19cfa2 HY |
2201 | #ifndef _WIN32 |
2202 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2203 | { | |
2204 | RAMBlock *block; | |
2205 | ram_addr_t offset; | |
2206 | int flags; | |
2207 | void *area, *vaddr; | |
2208 | ||
99e15582 | 2209 | RAMBLOCK_FOREACH(block) { |
cd19cfa2 | 2210 | offset = addr - block->offset; |
9b8424d5 | 2211 | if (offset < block->max_length) { |
1240be24 | 2212 | vaddr = ramblock_ptr(block, offset); |
7bd4f430 | 2213 | if (block->flags & RAM_PREALLOC) { |
cd19cfa2 | 2214 | ; |
dfeaf2ab MA |
2215 | } else if (xen_enabled()) { |
2216 | abort(); | |
cd19cfa2 HY |
2217 | } else { |
2218 | flags = MAP_FIXED; | |
3435f395 | 2219 | if (block->fd >= 0) { |
dbcb8981 PB |
2220 | flags |= (block->flags & RAM_SHARED ? |
2221 | MAP_SHARED : MAP_PRIVATE); | |
3435f395 MA |
2222 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
2223 | flags, block->fd, offset); | |
cd19cfa2 | 2224 | } else { |
cd19cfa2 HY |
2225 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
2226 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2227 | flags, -1, 0); | |
cd19cfa2 HY |
2228 | } |
2229 | if (area != vaddr) { | |
493d89bf AF |
2230 | error_report("Could not remap addr: " |
2231 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "", | |
2232 | length, addr); | |
cd19cfa2 HY |
2233 | exit(1); |
2234 | } | |
8490fc78 | 2235 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 2236 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 | 2237 | } |
cd19cfa2 HY |
2238 | } |
2239 | } | |
2240 | } | |
2241 | #endif /* !_WIN32 */ | |
2242 | ||
1b5ec234 | 2243 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
ae3a7047 MD |
2244 | * This should not be used for general purpose DMA. Use address_space_map |
2245 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
2246 | * device owns, use memory_region_get_ram_ptr. | |
0dc3f44a | 2247 | * |
49b24afc | 2248 | * Called within RCU critical section. |
1b5ec234 | 2249 | */ |
0878d0e1 | 2250 | void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) |
1b5ec234 | 2251 | { |
3655cb9c GA |
2252 | RAMBlock *block = ram_block; |
2253 | ||
2254 | if (block == NULL) { | |
2255 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2256 | addr -= block->offset; |
3655cb9c | 2257 | } |
ae3a7047 MD |
2258 | |
2259 | if (xen_enabled() && block->host == NULL) { | |
0d6d3c87 PB |
2260 | /* We need to check if the requested address is in the RAM |
2261 | * because we don't want to map the entire memory in QEMU. | |
2262 | * In that case just map until the end of the page. | |
2263 | */ | |
2264 | if (block->offset == 0) { | |
1ff7c598 | 2265 | return xen_map_cache(addr, 0, 0, false); |
0d6d3c87 | 2266 | } |
ae3a7047 | 2267 | |
1ff7c598 | 2268 | block->host = xen_map_cache(block->offset, block->max_length, 1, false); |
0d6d3c87 | 2269 | } |
0878d0e1 | 2270 | return ramblock_ptr(block, addr); |
dc828ca1 PB |
2271 | } |
2272 | ||
0878d0e1 | 2273 | /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr |
ae3a7047 | 2274 | * but takes a size argument. |
0dc3f44a | 2275 | * |
e81bcda5 | 2276 | * Called within RCU critical section. |
ae3a7047 | 2277 | */ |
3655cb9c | 2278 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, |
f5aa69bd | 2279 | hwaddr *size, bool lock) |
38bee5dc | 2280 | { |
3655cb9c | 2281 | RAMBlock *block = ram_block; |
8ab934f9 SS |
2282 | if (*size == 0) { |
2283 | return NULL; | |
2284 | } | |
e81bcda5 | 2285 | |
3655cb9c GA |
2286 | if (block == NULL) { |
2287 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2288 | addr -= block->offset; |
3655cb9c | 2289 | } |
0878d0e1 | 2290 | *size = MIN(*size, block->max_length - addr); |
e81bcda5 PB |
2291 | |
2292 | if (xen_enabled() && block->host == NULL) { | |
2293 | /* We need to check if the requested address is in the RAM | |
2294 | * because we don't want to map the entire memory in QEMU. | |
2295 | * In that case just map the requested area. | |
2296 | */ | |
2297 | if (block->offset == 0) { | |
f5aa69bd | 2298 | return xen_map_cache(addr, *size, lock, lock); |
38bee5dc SS |
2299 | } |
2300 | ||
f5aa69bd | 2301 | block->host = xen_map_cache(block->offset, block->max_length, 1, lock); |
38bee5dc | 2302 | } |
e81bcda5 | 2303 | |
0878d0e1 | 2304 | return ramblock_ptr(block, addr); |
38bee5dc SS |
2305 | } |
2306 | ||
f90bb71b DDAG |
2307 | /* Return the offset of a hostpointer within a ramblock */ |
2308 | ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host) | |
2309 | { | |
2310 | ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host; | |
2311 | assert((uintptr_t)host >= (uintptr_t)rb->host); | |
2312 | assert(res < rb->max_length); | |
2313 | ||
2314 | return res; | |
2315 | } | |
2316 | ||
422148d3 DDAG |
2317 | /* |
2318 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
2319 | * in that RAMBlock. | |
2320 | * | |
2321 | * ptr: Host pointer to look up | |
2322 | * round_offset: If true round the result offset down to a page boundary | |
2323 | * *ram_addr: set to result ram_addr | |
2324 | * *offset: set to result offset within the RAMBlock | |
2325 | * | |
2326 | * Returns: RAMBlock (or NULL if not found) | |
ae3a7047 MD |
2327 | * |
2328 | * By the time this function returns, the returned pointer is not protected | |
2329 | * by RCU anymore. If the caller is not within an RCU critical section and | |
2330 | * does not hold the iothread lock, it must have other means of protecting the | |
2331 | * pointer, such as a reference to the region that includes the incoming | |
2332 | * ram_addr_t. | |
2333 | */ | |
422148d3 | 2334 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
422148d3 | 2335 | ram_addr_t *offset) |
5579c7f3 | 2336 | { |
94a6b54f PB |
2337 | RAMBlock *block; |
2338 | uint8_t *host = ptr; | |
2339 | ||
868bb33f | 2340 | if (xen_enabled()) { |
f615f396 | 2341 | ram_addr_t ram_addr; |
694ea274 | 2342 | RCU_READ_LOCK_GUARD(); |
f615f396 PB |
2343 | ram_addr = xen_ram_addr_from_mapcache(ptr); |
2344 | block = qemu_get_ram_block(ram_addr); | |
422148d3 | 2345 | if (block) { |
d6b6aec4 | 2346 | *offset = ram_addr - block->offset; |
422148d3 | 2347 | } |
422148d3 | 2348 | return block; |
712c2b41 SS |
2349 | } |
2350 | ||
694ea274 | 2351 | RCU_READ_LOCK_GUARD(); |
d73415a3 | 2352 | block = qatomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 2353 | if (block && block->host && host - block->host < block->max_length) { |
23887b79 PB |
2354 | goto found; |
2355 | } | |
2356 | ||
99e15582 | 2357 | RAMBLOCK_FOREACH(block) { |
432d268c JN |
2358 | /* This case append when the block is not mapped. */ |
2359 | if (block->host == NULL) { | |
2360 | continue; | |
2361 | } | |
9b8424d5 | 2362 | if (host - block->host < block->max_length) { |
23887b79 | 2363 | goto found; |
f471a17e | 2364 | } |
94a6b54f | 2365 | } |
432d268c | 2366 | |
1b5ec234 | 2367 | return NULL; |
23887b79 PB |
2368 | |
2369 | found: | |
422148d3 DDAG |
2370 | *offset = (host - block->host); |
2371 | if (round_offset) { | |
2372 | *offset &= TARGET_PAGE_MASK; | |
2373 | } | |
422148d3 DDAG |
2374 | return block; |
2375 | } | |
2376 | ||
e3dd7493 DDAG |
2377 | /* |
2378 | * Finds the named RAMBlock | |
2379 | * | |
2380 | * name: The name of RAMBlock to find | |
2381 | * | |
2382 | * Returns: RAMBlock (or NULL if not found) | |
2383 | */ | |
2384 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2385 | { | |
2386 | RAMBlock *block; | |
2387 | ||
99e15582 | 2388 | RAMBLOCK_FOREACH(block) { |
e3dd7493 DDAG |
2389 | if (!strcmp(name, block->idstr)) { |
2390 | return block; | |
2391 | } | |
2392 | } | |
2393 | ||
2394 | return NULL; | |
2395 | } | |
2396 | ||
422148d3 DDAG |
2397 | /* Some of the softmmu routines need to translate from a host pointer |
2398 | (typically a TLB entry) back to a ram offset. */ | |
07bdaa41 | 2399 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
422148d3 DDAG |
2400 | { |
2401 | RAMBlock *block; | |
f615f396 | 2402 | ram_addr_t offset; |
422148d3 | 2403 | |
f615f396 | 2404 | block = qemu_ram_block_from_host(ptr, false, &offset); |
422148d3 | 2405 | if (!block) { |
07bdaa41 | 2406 | return RAM_ADDR_INVALID; |
422148d3 DDAG |
2407 | } |
2408 | ||
07bdaa41 | 2409 | return block->offset + offset; |
e890261f | 2410 | } |
f471a17e | 2411 | |
b2a44fca | 2412 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, |
a152be43 | 2413 | MemTxAttrs attrs, void *buf, hwaddr len); |
16620684 | 2414 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
a152be43 | 2415 | const void *buf, hwaddr len); |
0c249ff7 | 2416 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len, |
eace72b7 | 2417 | bool is_write, MemTxAttrs attrs); |
16620684 | 2418 | |
f25a49e0 PM |
2419 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, |
2420 | unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2421 | { |
acc9d80b | 2422 | subpage_t *subpage = opaque; |
ff6cff75 | 2423 | uint8_t buf[8]; |
5c9eb028 | 2424 | MemTxResult res; |
791af8c8 | 2425 | |
db7b5426 | 2426 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2427 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
acc9d80b | 2428 | subpage, len, addr); |
db7b5426 | 2429 | #endif |
16620684 | 2430 | res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); |
5c9eb028 PM |
2431 | if (res) { |
2432 | return res; | |
f25a49e0 | 2433 | } |
6d3ede54 PM |
2434 | *data = ldn_p(buf, len); |
2435 | return MEMTX_OK; | |
db7b5426 BS |
2436 | } |
2437 | ||
f25a49e0 PM |
2438 | static MemTxResult subpage_write(void *opaque, hwaddr addr, |
2439 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2440 | { |
acc9d80b | 2441 | subpage_t *subpage = opaque; |
ff6cff75 | 2442 | uint8_t buf[8]; |
acc9d80b | 2443 | |
db7b5426 | 2444 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2445 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx |
acc9d80b JK |
2446 | " value %"PRIx64"\n", |
2447 | __func__, subpage, len, addr, value); | |
db7b5426 | 2448 | #endif |
6d3ede54 | 2449 | stn_p(buf, len, value); |
16620684 | 2450 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); |
db7b5426 BS |
2451 | } |
2452 | ||
c353e4cc | 2453 | static bool subpage_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
2454 | unsigned len, bool is_write, |
2455 | MemTxAttrs attrs) | |
c353e4cc | 2456 | { |
acc9d80b | 2457 | subpage_t *subpage = opaque; |
c353e4cc | 2458 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2459 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
acc9d80b | 2460 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
c353e4cc PB |
2461 | #endif |
2462 | ||
16620684 | 2463 | return flatview_access_valid(subpage->fv, addr + subpage->base, |
eace72b7 | 2464 | len, is_write, attrs); |
c353e4cc PB |
2465 | } |
2466 | ||
70c68e44 | 2467 | static const MemoryRegionOps subpage_ops = { |
f25a49e0 PM |
2468 | .read_with_attrs = subpage_read, |
2469 | .write_with_attrs = subpage_write, | |
ff6cff75 PB |
2470 | .impl.min_access_size = 1, |
2471 | .impl.max_access_size = 8, | |
2472 | .valid.min_access_size = 1, | |
2473 | .valid.max_access_size = 8, | |
c353e4cc | 2474 | .valid.accepts = subpage_accepts, |
70c68e44 | 2475 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
2476 | }; |
2477 | ||
b797ab1a WY |
2478 | static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end, |
2479 | uint16_t section) | |
db7b5426 BS |
2480 | { |
2481 | int idx, eidx; | |
2482 | ||
2483 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2484 | return -1; | |
2485 | idx = SUBPAGE_IDX(start); | |
2486 | eidx = SUBPAGE_IDX(end); | |
2487 | #if defined(DEBUG_SUBPAGE) | |
016e9d62 AK |
2488 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
2489 | __func__, mmio, start, end, idx, eidx, section); | |
db7b5426 | 2490 | #endif |
db7b5426 | 2491 | for (; idx <= eidx; idx++) { |
5312bd8b | 2492 | mmio->sub_section[idx] = section; |
db7b5426 BS |
2493 | } |
2494 | ||
2495 | return 0; | |
2496 | } | |
2497 | ||
16620684 | 2498 | static subpage_t *subpage_init(FlatView *fv, hwaddr base) |
db7b5426 | 2499 | { |
c227f099 | 2500 | subpage_t *mmio; |
db7b5426 | 2501 | |
b797ab1a | 2502 | /* mmio->sub_section is set to PHYS_SECTION_UNASSIGNED with g_malloc0 */ |
2615fabd | 2503 | mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); |
16620684 | 2504 | mmio->fv = fv; |
1eec614b | 2505 | mmio->base = base; |
2c9b15ca | 2506 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
b4fefef9 | 2507 | NULL, TARGET_PAGE_SIZE); |
b3b00c78 | 2508 | mmio->iomem.subpage = true; |
db7b5426 | 2509 | #if defined(DEBUG_SUBPAGE) |
016e9d62 AK |
2510 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
2511 | mmio, base, TARGET_PAGE_SIZE); | |
db7b5426 | 2512 | #endif |
db7b5426 BS |
2513 | |
2514 | return mmio; | |
2515 | } | |
2516 | ||
16620684 | 2517 | static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) |
5312bd8b | 2518 | { |
16620684 | 2519 | assert(fv); |
5312bd8b | 2520 | MemoryRegionSection section = { |
16620684 | 2521 | .fv = fv, |
5312bd8b AK |
2522 | .mr = mr, |
2523 | .offset_within_address_space = 0, | |
2524 | .offset_within_region = 0, | |
052e87b0 | 2525 | .size = int128_2_64(), |
5312bd8b AK |
2526 | }; |
2527 | ||
53cb28cb | 2528 | return phys_section_add(map, §ion); |
5312bd8b AK |
2529 | } |
2530 | ||
2d54f194 PM |
2531 | MemoryRegionSection *iotlb_to_section(CPUState *cpu, |
2532 | hwaddr index, MemTxAttrs attrs) | |
aa102231 | 2533 | { |
a54c87b6 PM |
2534 | int asidx = cpu_asidx_from_attrs(cpu, attrs); |
2535 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
d73415a3 | 2536 | AddressSpaceDispatch *d = qatomic_rcu_read(&cpuas->memory_dispatch); |
79e2b9ae | 2537 | MemoryRegionSection *sections = d->map.sections; |
9d82b5a7 | 2538 | |
2d54f194 | 2539 | return §ions[index & ~TARGET_PAGE_MASK]; |
aa102231 AK |
2540 | } |
2541 | ||
e9179ce1 AK |
2542 | static void io_mem_init(void) |
2543 | { | |
2c9b15ca | 2544 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
1f6245e5 | 2545 | NULL, UINT64_MAX); |
e9179ce1 AK |
2546 | } |
2547 | ||
8629d3fc | 2548 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) |
00752703 | 2549 | { |
53cb28cb MA |
2550 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
2551 | uint16_t n; | |
2552 | ||
16620684 | 2553 | n = dummy_section(&d->map, fv, &io_mem_unassigned); |
53cb28cb | 2554 | assert(n == PHYS_SECTION_UNASSIGNED); |
00752703 | 2555 | |
9736e55b | 2556 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
66a6df1d AK |
2557 | |
2558 | return d; | |
00752703 PB |
2559 | } |
2560 | ||
66a6df1d | 2561 | void address_space_dispatch_free(AddressSpaceDispatch *d) |
79e2b9ae PB |
2562 | { |
2563 | phys_sections_free(&d->map); | |
2564 | g_free(d); | |
2565 | } | |
2566 | ||
9458a9a1 PB |
2567 | static void do_nothing(CPUState *cpu, run_on_cpu_data d) |
2568 | { | |
2569 | } | |
2570 | ||
2571 | static void tcg_log_global_after_sync(MemoryListener *listener) | |
2572 | { | |
2573 | CPUAddressSpace *cpuas; | |
2574 | ||
2575 | /* Wait for the CPU to end the current TB. This avoids the following | |
2576 | * incorrect race: | |
2577 | * | |
2578 | * vCPU migration | |
2579 | * ---------------------- ------------------------- | |
2580 | * TLB check -> slow path | |
2581 | * notdirty_mem_write | |
2582 | * write to RAM | |
2583 | * mark dirty | |
2584 | * clear dirty flag | |
2585 | * TLB check -> fast path | |
2586 | * read memory | |
2587 | * write to RAM | |
2588 | * | |
2589 | * by pushing the migration thread's memory read after the vCPU thread has | |
2590 | * written the memory. | |
2591 | */ | |
86cf9e15 PD |
2592 | if (replay_mode == REPLAY_MODE_NONE) { |
2593 | /* | |
2594 | * VGA can make calls to this function while updating the screen. | |
2595 | * In record/replay mode this causes a deadlock, because | |
2596 | * run_on_cpu waits for rr mutex. Therefore no races are possible | |
2597 | * in this case and no need for making run_on_cpu when | |
2598 | * record/replay is not enabled. | |
2599 | */ | |
2600 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); | |
2601 | run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL); | |
2602 | } | |
9458a9a1 PB |
2603 | } |
2604 | ||
1d71148e | 2605 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 2606 | { |
32857f4d PM |
2607 | CPUAddressSpace *cpuas; |
2608 | AddressSpaceDispatch *d; | |
117712c3 | 2609 | |
f28d0dfd | 2610 | assert(tcg_enabled()); |
117712c3 AK |
2611 | /* since each CPU stores ram addresses in its TLB cache, we must |
2612 | reset the modified entries */ | |
32857f4d PM |
2613 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); |
2614 | cpu_reloading_memory_map(); | |
2615 | /* The CPU and TLB are protected by the iothread lock. | |
2616 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
2617 | * may have split the RCU critical section. | |
2618 | */ | |
66a6df1d | 2619 | d = address_space_to_dispatch(cpuas->as); |
d73415a3 | 2620 | qatomic_rcu_set(&cpuas->memory_dispatch, d); |
d10eb08f | 2621 | tlb_flush(cpuas->cpu); |
50c1e149 AK |
2622 | } |
2623 | ||
62152b8a AK |
2624 | static void memory_map_init(void) |
2625 | { | |
7267c094 | 2626 | system_memory = g_malloc(sizeof(*system_memory)); |
03f49957 | 2627 | |
57271d63 | 2628 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
7dca8043 | 2629 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 2630 | |
7267c094 | 2631 | system_io = g_malloc(sizeof(*system_io)); |
3bb28b72 JK |
2632 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
2633 | 65536); | |
7dca8043 | 2634 | address_space_init(&address_space_io, system_io, "I/O"); |
62152b8a AK |
2635 | } |
2636 | ||
2637 | MemoryRegion *get_system_memory(void) | |
2638 | { | |
2639 | return system_memory; | |
2640 | } | |
2641 | ||
309cb471 AK |
2642 | MemoryRegion *get_system_io(void) |
2643 | { | |
2644 | return system_io; | |
2645 | } | |
2646 | ||
845b6214 | 2647 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, |
a8170e5e | 2648 | hwaddr length) |
51d7a9eb | 2649 | { |
e87f7778 | 2650 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
0878d0e1 PB |
2651 | addr += memory_region_get_ram_addr(mr); |
2652 | ||
e87f7778 PB |
2653 | /* No early return if dirty_log_mask is or becomes 0, because |
2654 | * cpu_physical_memory_set_dirty_range will still call | |
2655 | * xen_modified_memory. | |
2656 | */ | |
2657 | if (dirty_log_mask) { | |
2658 | dirty_log_mask = | |
2659 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
2660 | } | |
2661 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
5aa1ef71 | 2662 | assert(tcg_enabled()); |
e87f7778 PB |
2663 | tb_invalidate_phys_range(addr, addr + length); |
2664 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); | |
51d7a9eb | 2665 | } |
e87f7778 | 2666 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); |
51d7a9eb AP |
2667 | } |
2668 | ||
047be4ed SH |
2669 | void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size) |
2670 | { | |
2671 | /* | |
2672 | * In principle this function would work on other memory region types too, | |
2673 | * but the ROM device use case is the only one where this operation is | |
2674 | * necessary. Other memory regions should use the | |
2675 | * address_space_read/write() APIs. | |
2676 | */ | |
2677 | assert(memory_region_is_romd(mr)); | |
2678 | ||
2679 | invalidate_and_set_dirty(mr, addr, size); | |
2680 | } | |
2681 | ||
23326164 | 2682 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
82f2563f | 2683 | { |
e1622f4b | 2684 | unsigned access_size_max = mr->ops->valid.max_access_size; |
23326164 RH |
2685 | |
2686 | /* Regions are assumed to support 1-4 byte accesses unless | |
2687 | otherwise specified. */ | |
23326164 RH |
2688 | if (access_size_max == 0) { |
2689 | access_size_max = 4; | |
2690 | } | |
2691 | ||
2692 | /* Bound the maximum access by the alignment of the address. */ | |
2693 | if (!mr->ops->impl.unaligned) { | |
2694 | unsigned align_size_max = addr & -addr; | |
2695 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
2696 | access_size_max = align_size_max; | |
2697 | } | |
82f2563f | 2698 | } |
23326164 RH |
2699 | |
2700 | /* Don't attempt accesses larger than the maximum. */ | |
2701 | if (l > access_size_max) { | |
2702 | l = access_size_max; | |
82f2563f | 2703 | } |
6554f5c0 | 2704 | l = pow2floor(l); |
23326164 RH |
2705 | |
2706 | return l; | |
82f2563f PB |
2707 | } |
2708 | ||
4840f10e | 2709 | static bool prepare_mmio_access(MemoryRegion *mr) |
125b3806 | 2710 | { |
4840f10e JK |
2711 | bool release_lock = false; |
2712 | ||
37921851 | 2713 | if (!qemu_mutex_iothread_locked()) { |
4840f10e | 2714 | qemu_mutex_lock_iothread(); |
4840f10e JK |
2715 | release_lock = true; |
2716 | } | |
125b3806 PB |
2717 | if (mr->flush_coalesced_mmio) { |
2718 | qemu_flush_coalesced_mmio_buffer(); | |
2719 | } | |
4840f10e JK |
2720 | |
2721 | return release_lock; | |
125b3806 PB |
2722 | } |
2723 | ||
a203ac70 | 2724 | /* Called within RCU critical section. */ |
16620684 AK |
2725 | static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, |
2726 | MemTxAttrs attrs, | |
a152be43 | 2727 | const void *ptr, |
0c249ff7 | 2728 | hwaddr len, hwaddr addr1, |
16620684 | 2729 | hwaddr l, MemoryRegion *mr) |
13eb76e0 | 2730 | { |
20804676 | 2731 | uint8_t *ram_ptr; |
791af8c8 | 2732 | uint64_t val; |
3b643495 | 2733 | MemTxResult result = MEMTX_OK; |
4840f10e | 2734 | bool release_lock = false; |
a152be43 | 2735 | const uint8_t *buf = ptr; |
3b46e624 | 2736 | |
a203ac70 | 2737 | for (;;) { |
eb7eeb88 PB |
2738 | if (!memory_access_is_direct(mr, true)) { |
2739 | release_lock |= prepare_mmio_access(mr); | |
2740 | l = memory_access_size(mr, l, addr1); | |
2741 | /* XXX: could force current_cpu to NULL to avoid | |
2742 | potential bugs */ | |
9bf825bf | 2743 | val = ldn_he_p(buf, l); |
3d9e7c3e | 2744 | result |= memory_region_dispatch_write(mr, addr1, val, |
9bf825bf | 2745 | size_memop(l), attrs); |
13eb76e0 | 2746 | } else { |
eb7eeb88 | 2747 | /* RAM case */ |
20804676 PMD |
2748 | ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
2749 | memcpy(ram_ptr, buf, l); | |
eb7eeb88 | 2750 | invalidate_and_set_dirty(mr, addr1, l); |
13eb76e0 | 2751 | } |
4840f10e JK |
2752 | |
2753 | if (release_lock) { | |
2754 | qemu_mutex_unlock_iothread(); | |
2755 | release_lock = false; | |
2756 | } | |
2757 | ||
13eb76e0 FB |
2758 | len -= l; |
2759 | buf += l; | |
2760 | addr += l; | |
a203ac70 PB |
2761 | |
2762 | if (!len) { | |
2763 | break; | |
2764 | } | |
2765 | ||
2766 | l = len; | |
efa99a2f | 2767 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); |
13eb76e0 | 2768 | } |
fd8aaa76 | 2769 | |
3b643495 | 2770 | return result; |
13eb76e0 | 2771 | } |
8df1cd07 | 2772 | |
4c6ebbb3 | 2773 | /* Called from RCU critical section. */ |
16620684 | 2774 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
a152be43 | 2775 | const void *buf, hwaddr len) |
ac1970fb | 2776 | { |
eb7eeb88 | 2777 | hwaddr l; |
eb7eeb88 PB |
2778 | hwaddr addr1; |
2779 | MemoryRegion *mr; | |
2780 | MemTxResult result = MEMTX_OK; | |
eb7eeb88 | 2781 | |
4c6ebbb3 | 2782 | l = len; |
efa99a2f | 2783 | mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); |
4c6ebbb3 PB |
2784 | result = flatview_write_continue(fv, addr, attrs, buf, len, |
2785 | addr1, l, mr); | |
a203ac70 PB |
2786 | |
2787 | return result; | |
2788 | } | |
2789 | ||
2790 | /* Called within RCU critical section. */ | |
16620684 | 2791 | MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, |
a152be43 | 2792 | MemTxAttrs attrs, void *ptr, |
0c249ff7 | 2793 | hwaddr len, hwaddr addr1, hwaddr l, |
16620684 | 2794 | MemoryRegion *mr) |
a203ac70 | 2795 | { |
20804676 | 2796 | uint8_t *ram_ptr; |
a203ac70 PB |
2797 | uint64_t val; |
2798 | MemTxResult result = MEMTX_OK; | |
2799 | bool release_lock = false; | |
a152be43 | 2800 | uint8_t *buf = ptr; |
eb7eeb88 | 2801 | |
7cac7fea | 2802 | fuzz_dma_read_cb(addr, len, mr); |
a203ac70 | 2803 | for (;;) { |
eb7eeb88 PB |
2804 | if (!memory_access_is_direct(mr, false)) { |
2805 | /* I/O case */ | |
2806 | release_lock |= prepare_mmio_access(mr); | |
2807 | l = memory_access_size(mr, l, addr1); | |
3d9e7c3e | 2808 | result |= memory_region_dispatch_read(mr, addr1, &val, |
9bf825bf TN |
2809 | size_memop(l), attrs); |
2810 | stn_he_p(buf, l, val); | |
eb7eeb88 PB |
2811 | } else { |
2812 | /* RAM case */ | |
20804676 PMD |
2813 | ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
2814 | memcpy(buf, ram_ptr, l); | |
eb7eeb88 PB |
2815 | } |
2816 | ||
2817 | if (release_lock) { | |
2818 | qemu_mutex_unlock_iothread(); | |
2819 | release_lock = false; | |
2820 | } | |
2821 | ||
2822 | len -= l; | |
2823 | buf += l; | |
2824 | addr += l; | |
a203ac70 PB |
2825 | |
2826 | if (!len) { | |
2827 | break; | |
2828 | } | |
2829 | ||
2830 | l = len; | |
efa99a2f | 2831 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); |
a203ac70 PB |
2832 | } |
2833 | ||
2834 | return result; | |
2835 | } | |
2836 | ||
b2a44fca PB |
2837 | /* Called from RCU critical section. */ |
2838 | static MemTxResult flatview_read(FlatView *fv, hwaddr addr, | |
a152be43 | 2839 | MemTxAttrs attrs, void *buf, hwaddr len) |
a203ac70 PB |
2840 | { |
2841 | hwaddr l; | |
2842 | hwaddr addr1; | |
2843 | MemoryRegion *mr; | |
eb7eeb88 | 2844 | |
b2a44fca | 2845 | l = len; |
efa99a2f | 2846 | mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); |
b2a44fca PB |
2847 | return flatview_read_continue(fv, addr, attrs, buf, len, |
2848 | addr1, l, mr); | |
ac1970fb AK |
2849 | } |
2850 | ||
b2a44fca | 2851 | MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, |
daa3dda4 | 2852 | MemTxAttrs attrs, void *buf, hwaddr len) |
b2a44fca PB |
2853 | { |
2854 | MemTxResult result = MEMTX_OK; | |
2855 | FlatView *fv; | |
2856 | ||
2857 | if (len > 0) { | |
694ea274 | 2858 | RCU_READ_LOCK_GUARD(); |
b2a44fca PB |
2859 | fv = address_space_to_flatview(as); |
2860 | result = flatview_read(fv, addr, attrs, buf, len); | |
b2a44fca PB |
2861 | } |
2862 | ||
2863 | return result; | |
2864 | } | |
2865 | ||
4c6ebbb3 PB |
2866 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, |
2867 | MemTxAttrs attrs, | |
daa3dda4 | 2868 | const void *buf, hwaddr len) |
4c6ebbb3 PB |
2869 | { |
2870 | MemTxResult result = MEMTX_OK; | |
2871 | FlatView *fv; | |
2872 | ||
2873 | if (len > 0) { | |
694ea274 | 2874 | RCU_READ_LOCK_GUARD(); |
4c6ebbb3 PB |
2875 | fv = address_space_to_flatview(as); |
2876 | result = flatview_write(fv, addr, attrs, buf, len); | |
4c6ebbb3 PB |
2877 | } |
2878 | ||
2879 | return result; | |
2880 | } | |
2881 | ||
db84fd97 | 2882 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
daa3dda4 | 2883 | void *buf, hwaddr len, bool is_write) |
db84fd97 PB |
2884 | { |
2885 | if (is_write) { | |
2886 | return address_space_write(as, addr, attrs, buf, len); | |
2887 | } else { | |
2888 | return address_space_read_full(as, addr, attrs, buf, len); | |
2889 | } | |
2890 | } | |
2891 | ||
d7ef71ef | 2892 | void cpu_physical_memory_rw(hwaddr addr, void *buf, |
28c80bfe | 2893 | hwaddr len, bool is_write) |
ac1970fb | 2894 | { |
5c9eb028 PM |
2895 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, |
2896 | buf, len, is_write); | |
ac1970fb AK |
2897 | } |
2898 | ||
582b55a9 AG |
2899 | enum write_rom_type { |
2900 | WRITE_DATA, | |
2901 | FLUSH_CACHE, | |
2902 | }; | |
2903 | ||
75693e14 PM |
2904 | static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, |
2905 | hwaddr addr, | |
2906 | MemTxAttrs attrs, | |
daa3dda4 | 2907 | const void *ptr, |
0c249ff7 | 2908 | hwaddr len, |
75693e14 | 2909 | enum write_rom_type type) |
d0ecd2aa | 2910 | { |
149f54b5 | 2911 | hwaddr l; |
20804676 | 2912 | uint8_t *ram_ptr; |
149f54b5 | 2913 | hwaddr addr1; |
5c8a00ce | 2914 | MemoryRegion *mr; |
daa3dda4 | 2915 | const uint8_t *buf = ptr; |
3b46e624 | 2916 | |
694ea274 | 2917 | RCU_READ_LOCK_GUARD(); |
d0ecd2aa | 2918 | while (len > 0) { |
149f54b5 | 2919 | l = len; |
75693e14 | 2920 | mr = address_space_translate(as, addr, &addr1, &l, true, attrs); |
3b46e624 | 2921 | |
5c8a00ce PB |
2922 | if (!(memory_region_is_ram(mr) || |
2923 | memory_region_is_romd(mr))) { | |
b242e0e0 | 2924 | l = memory_access_size(mr, l, addr1); |
d0ecd2aa | 2925 | } else { |
d0ecd2aa | 2926 | /* ROM/RAM case */ |
20804676 | 2927 | ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1); |
582b55a9 AG |
2928 | switch (type) { |
2929 | case WRITE_DATA: | |
20804676 | 2930 | memcpy(ram_ptr, buf, l); |
845b6214 | 2931 | invalidate_and_set_dirty(mr, addr1, l); |
582b55a9 AG |
2932 | break; |
2933 | case FLUSH_CACHE: | |
1da8de39 | 2934 | flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr, l); |
582b55a9 AG |
2935 | break; |
2936 | } | |
d0ecd2aa FB |
2937 | } |
2938 | len -= l; | |
2939 | buf += l; | |
2940 | addr += l; | |
2941 | } | |
75693e14 | 2942 | return MEMTX_OK; |
d0ecd2aa FB |
2943 | } |
2944 | ||
582b55a9 | 2945 | /* used for ROM loading : can write in RAM and ROM */ |
3c8133f9 PM |
2946 | MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, |
2947 | MemTxAttrs attrs, | |
daa3dda4 | 2948 | const void *buf, hwaddr len) |
582b55a9 | 2949 | { |
3c8133f9 PM |
2950 | return address_space_write_rom_internal(as, addr, attrs, |
2951 | buf, len, WRITE_DATA); | |
582b55a9 AG |
2952 | } |
2953 | ||
0c249ff7 | 2954 | void cpu_flush_icache_range(hwaddr start, hwaddr len) |
582b55a9 AG |
2955 | { |
2956 | /* | |
2957 | * This function should do the same thing as an icache flush that was | |
2958 | * triggered from within the guest. For TCG we are always cache coherent, | |
2959 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
2960 | * the host's instruction cache at least. | |
2961 | */ | |
2962 | if (tcg_enabled()) { | |
2963 | return; | |
2964 | } | |
2965 | ||
75693e14 PM |
2966 | address_space_write_rom_internal(&address_space_memory, |
2967 | start, MEMTXATTRS_UNSPECIFIED, | |
2968 | NULL, len, FLUSH_CACHE); | |
582b55a9 AG |
2969 | } |
2970 | ||
6d16c2f8 | 2971 | typedef struct { |
d3e71559 | 2972 | MemoryRegion *mr; |
6d16c2f8 | 2973 | void *buffer; |
a8170e5e AK |
2974 | hwaddr addr; |
2975 | hwaddr len; | |
c2cba0ff | 2976 | bool in_use; |
6d16c2f8 AL |
2977 | } BounceBuffer; |
2978 | ||
2979 | static BounceBuffer bounce; | |
2980 | ||
ba223c29 | 2981 | typedef struct MapClient { |
e95205e1 | 2982 | QEMUBH *bh; |
72cf2d4f | 2983 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
2984 | } MapClient; |
2985 | ||
38e047b5 | 2986 | QemuMutex map_client_list_lock; |
b58deb34 | 2987 | static QLIST_HEAD(, MapClient) map_client_list |
72cf2d4f | 2988 | = QLIST_HEAD_INITIALIZER(map_client_list); |
ba223c29 | 2989 | |
e95205e1 FZ |
2990 | static void cpu_unregister_map_client_do(MapClient *client) |
2991 | { | |
2992 | QLIST_REMOVE(client, link); | |
2993 | g_free(client); | |
2994 | } | |
2995 | ||
33b6c2ed FZ |
2996 | static void cpu_notify_map_clients_locked(void) |
2997 | { | |
2998 | MapClient *client; | |
2999 | ||
3000 | while (!QLIST_EMPTY(&map_client_list)) { | |
3001 | client = QLIST_FIRST(&map_client_list); | |
e95205e1 FZ |
3002 | qemu_bh_schedule(client->bh); |
3003 | cpu_unregister_map_client_do(client); | |
33b6c2ed FZ |
3004 | } |
3005 | } | |
3006 | ||
e95205e1 | 3007 | void cpu_register_map_client(QEMUBH *bh) |
ba223c29 | 3008 | { |
7267c094 | 3009 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 | 3010 | |
38e047b5 | 3011 | qemu_mutex_lock(&map_client_list_lock); |
e95205e1 | 3012 | client->bh = bh; |
72cf2d4f | 3013 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
d73415a3 | 3014 | if (!qatomic_read(&bounce.in_use)) { |
33b6c2ed FZ |
3015 | cpu_notify_map_clients_locked(); |
3016 | } | |
38e047b5 | 3017 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3018 | } |
3019 | ||
38e047b5 | 3020 | void cpu_exec_init_all(void) |
ba223c29 | 3021 | { |
38e047b5 | 3022 | qemu_mutex_init(&ram_list.mutex); |
20bccb82 PM |
3023 | /* The data structures we set up here depend on knowing the page size, |
3024 | * so no more changes can be made after this point. | |
3025 | * In an ideal world, nothing we did before we had finished the | |
3026 | * machine setup would care about the target page size, and we could | |
3027 | * do this much later, rather than requiring board models to state | |
3028 | * up front what their requirements are. | |
3029 | */ | |
3030 | finalize_target_page_bits(); | |
38e047b5 | 3031 | io_mem_init(); |
680a4783 | 3032 | memory_map_init(); |
38e047b5 | 3033 | qemu_mutex_init(&map_client_list_lock); |
ba223c29 AL |
3034 | } |
3035 | ||
e95205e1 | 3036 | void cpu_unregister_map_client(QEMUBH *bh) |
ba223c29 AL |
3037 | { |
3038 | MapClient *client; | |
3039 | ||
e95205e1 FZ |
3040 | qemu_mutex_lock(&map_client_list_lock); |
3041 | QLIST_FOREACH(client, &map_client_list, link) { | |
3042 | if (client->bh == bh) { | |
3043 | cpu_unregister_map_client_do(client); | |
3044 | break; | |
3045 | } | |
ba223c29 | 3046 | } |
e95205e1 | 3047 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3048 | } |
3049 | ||
3050 | static void cpu_notify_map_clients(void) | |
3051 | { | |
38e047b5 | 3052 | qemu_mutex_lock(&map_client_list_lock); |
33b6c2ed | 3053 | cpu_notify_map_clients_locked(); |
38e047b5 | 3054 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3055 | } |
3056 | ||
0c249ff7 | 3057 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len, |
eace72b7 | 3058 | bool is_write, MemTxAttrs attrs) |
51644ab7 | 3059 | { |
5c8a00ce | 3060 | MemoryRegion *mr; |
51644ab7 PB |
3061 | hwaddr l, xlat; |
3062 | ||
3063 | while (len > 0) { | |
3064 | l = len; | |
efa99a2f | 3065 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); |
5c8a00ce PB |
3066 | if (!memory_access_is_direct(mr, is_write)) { |
3067 | l = memory_access_size(mr, l, addr); | |
eace72b7 | 3068 | if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) { |
51644ab7 PB |
3069 | return false; |
3070 | } | |
3071 | } | |
3072 | ||
3073 | len -= l; | |
3074 | addr += l; | |
3075 | } | |
3076 | return true; | |
3077 | } | |
3078 | ||
16620684 | 3079 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, |
0c249ff7 | 3080 | hwaddr len, bool is_write, |
fddffa42 | 3081 | MemTxAttrs attrs) |
16620684 | 3082 | { |
11e732a5 PB |
3083 | FlatView *fv; |
3084 | bool result; | |
3085 | ||
694ea274 | 3086 | RCU_READ_LOCK_GUARD(); |
11e732a5 | 3087 | fv = address_space_to_flatview(as); |
eace72b7 | 3088 | result = flatview_access_valid(fv, addr, len, is_write, attrs); |
11e732a5 | 3089 | return result; |
16620684 AK |
3090 | } |
3091 | ||
715c31ec | 3092 | static hwaddr |
16620684 | 3093 | flatview_extend_translation(FlatView *fv, hwaddr addr, |
53d0790d PM |
3094 | hwaddr target_len, |
3095 | MemoryRegion *mr, hwaddr base, hwaddr len, | |
3096 | bool is_write, MemTxAttrs attrs) | |
715c31ec PB |
3097 | { |
3098 | hwaddr done = 0; | |
3099 | hwaddr xlat; | |
3100 | MemoryRegion *this_mr; | |
3101 | ||
3102 | for (;;) { | |
3103 | target_len -= len; | |
3104 | addr += len; | |
3105 | done += len; | |
3106 | if (target_len == 0) { | |
3107 | return done; | |
3108 | } | |
3109 | ||
3110 | len = target_len; | |
16620684 | 3111 | this_mr = flatview_translate(fv, addr, &xlat, |
efa99a2f | 3112 | &len, is_write, attrs); |
715c31ec PB |
3113 | if (this_mr != mr || xlat != base + done) { |
3114 | return done; | |
3115 | } | |
3116 | } | |
3117 | } | |
3118 | ||
6d16c2f8 AL |
3119 | /* Map a physical memory region into a host virtual address. |
3120 | * May map a subset of the requested range, given by and returned in *plen. | |
3121 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3122 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3123 | * Use cpu_register_map_client() to know when retrying the map operation is |
3124 | * likely to succeed. | |
6d16c2f8 | 3125 | */ |
ac1970fb | 3126 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
3127 | hwaddr addr, |
3128 | hwaddr *plen, | |
f26404fb PM |
3129 | bool is_write, |
3130 | MemTxAttrs attrs) | |
6d16c2f8 | 3131 | { |
a8170e5e | 3132 | hwaddr len = *plen; |
715c31ec PB |
3133 | hwaddr l, xlat; |
3134 | MemoryRegion *mr; | |
e81bcda5 | 3135 | void *ptr; |
ad0c60fa | 3136 | FlatView *fv; |
6d16c2f8 | 3137 | |
e3127ae0 PB |
3138 | if (len == 0) { |
3139 | return NULL; | |
3140 | } | |
38bee5dc | 3141 | |
e3127ae0 | 3142 | l = len; |
694ea274 | 3143 | RCU_READ_LOCK_GUARD(); |
ad0c60fa | 3144 | fv = address_space_to_flatview(as); |
efa99a2f | 3145 | mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); |
41063e1e | 3146 | |
e3127ae0 | 3147 | if (!memory_access_is_direct(mr, is_write)) { |
d73415a3 | 3148 | if (qatomic_xchg(&bounce.in_use, true)) { |
77f55eac | 3149 | *plen = 0; |
e3127ae0 | 3150 | return NULL; |
6d16c2f8 | 3151 | } |
e85d9db5 KW |
3152 | /* Avoid unbounded allocations */ |
3153 | l = MIN(l, TARGET_PAGE_SIZE); | |
3154 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
e3127ae0 PB |
3155 | bounce.addr = addr; |
3156 | bounce.len = l; | |
d3e71559 PB |
3157 | |
3158 | memory_region_ref(mr); | |
3159 | bounce.mr = mr; | |
e3127ae0 | 3160 | if (!is_write) { |
16620684 | 3161 | flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED, |
5c9eb028 | 3162 | bounce.buffer, l); |
8ab934f9 | 3163 | } |
6d16c2f8 | 3164 | |
e3127ae0 PB |
3165 | *plen = l; |
3166 | return bounce.buffer; | |
3167 | } | |
3168 | ||
e3127ae0 | 3169 | |
d3e71559 | 3170 | memory_region_ref(mr); |
16620684 | 3171 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, |
53d0790d | 3172 | l, is_write, attrs); |
fc1c8344 | 3173 | fuzz_dma_read_cb(addr, *plen, mr); |
f5aa69bd | 3174 | ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); |
e81bcda5 PB |
3175 | |
3176 | return ptr; | |
6d16c2f8 AL |
3177 | } |
3178 | ||
ac1970fb | 3179 | /* Unmaps a memory region previously mapped by address_space_map(). |
ae5883ab | 3180 | * Will also mark the memory as dirty if is_write is true. access_len gives |
6d16c2f8 AL |
3181 | * the amount of memory that was actually read or written by the caller. |
3182 | */ | |
a8170e5e | 3183 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
ae5883ab | 3184 | bool is_write, hwaddr access_len) |
6d16c2f8 AL |
3185 | { |
3186 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
3187 | MemoryRegion *mr; |
3188 | ram_addr_t addr1; | |
3189 | ||
07bdaa41 | 3190 | mr = memory_region_from_host(buffer, &addr1); |
d3e71559 | 3191 | assert(mr != NULL); |
6d16c2f8 | 3192 | if (is_write) { |
845b6214 | 3193 | invalidate_and_set_dirty(mr, addr1, access_len); |
6d16c2f8 | 3194 | } |
868bb33f | 3195 | if (xen_enabled()) { |
e41d7c69 | 3196 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 3197 | } |
d3e71559 | 3198 | memory_region_unref(mr); |
6d16c2f8 AL |
3199 | return; |
3200 | } | |
3201 | if (is_write) { | |
5c9eb028 PM |
3202 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, |
3203 | bounce.buffer, access_len); | |
6d16c2f8 | 3204 | } |
f8a83245 | 3205 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3206 | bounce.buffer = NULL; |
d3e71559 | 3207 | memory_region_unref(bounce.mr); |
d73415a3 | 3208 | qatomic_mb_set(&bounce.in_use, false); |
ba223c29 | 3209 | cpu_notify_map_clients(); |
6d16c2f8 | 3210 | } |
d0ecd2aa | 3211 | |
a8170e5e AK |
3212 | void *cpu_physical_memory_map(hwaddr addr, |
3213 | hwaddr *plen, | |
28c80bfe | 3214 | bool is_write) |
ac1970fb | 3215 | { |
f26404fb PM |
3216 | return address_space_map(&address_space_memory, addr, plen, is_write, |
3217 | MEMTXATTRS_UNSPECIFIED); | |
ac1970fb AK |
3218 | } |
3219 | ||
a8170e5e | 3220 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
28c80bfe | 3221 | bool is_write, hwaddr access_len) |
ac1970fb AK |
3222 | { |
3223 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3224 | } | |
3225 | ||
0ce265ff PB |
3226 | #define ARG1_DECL AddressSpace *as |
3227 | #define ARG1 as | |
3228 | #define SUFFIX | |
3229 | #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) | |
0ce265ff PB |
3230 | #define RCU_READ_LOCK(...) rcu_read_lock() |
3231 | #define RCU_READ_UNLOCK(...) rcu_read_unlock() | |
139c1837 | 3232 | #include "memory_ldst.c.inc" |
1e78bcc1 | 3233 | |
1f4e496e PB |
3234 | int64_t address_space_cache_init(MemoryRegionCache *cache, |
3235 | AddressSpace *as, | |
3236 | hwaddr addr, | |
3237 | hwaddr len, | |
3238 | bool is_write) | |
3239 | { | |
48564041 PB |
3240 | AddressSpaceDispatch *d; |
3241 | hwaddr l; | |
3242 | MemoryRegion *mr; | |
4bfb024b | 3243 | Int128 diff; |
48564041 PB |
3244 | |
3245 | assert(len > 0); | |
3246 | ||
3247 | l = len; | |
3248 | cache->fv = address_space_get_flatview(as); | |
3249 | d = flatview_to_dispatch(cache->fv); | |
3250 | cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true); | |
3251 | ||
4bfb024b PB |
3252 | /* |
3253 | * cache->xlat is now relative to cache->mrs.mr, not to the section itself. | |
3254 | * Take that into account to compute how many bytes are there between | |
3255 | * cache->xlat and the end of the section. | |
3256 | */ | |
3257 | diff = int128_sub(cache->mrs.size, | |
3258 | int128_make64(cache->xlat - cache->mrs.offset_within_region)); | |
3259 | l = int128_get64(int128_min(diff, int128_make64(l))); | |
3260 | ||
48564041 PB |
3261 | mr = cache->mrs.mr; |
3262 | memory_region_ref(mr); | |
3263 | if (memory_access_is_direct(mr, is_write)) { | |
53d0790d PM |
3264 | /* We don't care about the memory attributes here as we're only |
3265 | * doing this if we found actual RAM, which behaves the same | |
3266 | * regardless of attributes; so UNSPECIFIED is fine. | |
3267 | */ | |
48564041 | 3268 | l = flatview_extend_translation(cache->fv, addr, len, mr, |
53d0790d PM |
3269 | cache->xlat, l, is_write, |
3270 | MEMTXATTRS_UNSPECIFIED); | |
48564041 PB |
3271 | cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true); |
3272 | } else { | |
3273 | cache->ptr = NULL; | |
3274 | } | |
3275 | ||
3276 | cache->len = l; | |
3277 | cache->is_write = is_write; | |
3278 | return l; | |
1f4e496e PB |
3279 | } |
3280 | ||
3281 | void address_space_cache_invalidate(MemoryRegionCache *cache, | |
3282 | hwaddr addr, | |
3283 | hwaddr access_len) | |
3284 | { | |
48564041 PB |
3285 | assert(cache->is_write); |
3286 | if (likely(cache->ptr)) { | |
3287 | invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len); | |
3288 | } | |
1f4e496e PB |
3289 | } |
3290 | ||
3291 | void address_space_cache_destroy(MemoryRegionCache *cache) | |
3292 | { | |
48564041 PB |
3293 | if (!cache->mrs.mr) { |
3294 | return; | |
3295 | } | |
3296 | ||
3297 | if (xen_enabled()) { | |
3298 | xen_invalidate_map_cache_entry(cache->ptr); | |
3299 | } | |
3300 | memory_region_unref(cache->mrs.mr); | |
3301 | flatview_unref(cache->fv); | |
3302 | cache->mrs.mr = NULL; | |
3303 | cache->fv = NULL; | |
3304 | } | |
3305 | ||
3306 | /* Called from RCU critical section. This function has the same | |
3307 | * semantics as address_space_translate, but it only works on a | |
3308 | * predefined range of a MemoryRegion that was mapped with | |
3309 | * address_space_cache_init. | |
3310 | */ | |
3311 | static inline MemoryRegion *address_space_translate_cached( | |
3312 | MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat, | |
bc6b1cec | 3313 | hwaddr *plen, bool is_write, MemTxAttrs attrs) |
48564041 PB |
3314 | { |
3315 | MemoryRegionSection section; | |
3316 | MemoryRegion *mr; | |
3317 | IOMMUMemoryRegion *iommu_mr; | |
3318 | AddressSpace *target_as; | |
3319 | ||
3320 | assert(!cache->ptr); | |
3321 | *xlat = addr + cache->xlat; | |
3322 | ||
3323 | mr = cache->mrs.mr; | |
3324 | iommu_mr = memory_region_get_iommu(mr); | |
3325 | if (!iommu_mr) { | |
3326 | /* MMIO region. */ | |
3327 | return mr; | |
3328 | } | |
3329 | ||
3330 | section = address_space_translate_iommu(iommu_mr, xlat, plen, | |
3331 | NULL, is_write, true, | |
2f7b009c | 3332 | &target_as, attrs); |
48564041 PB |
3333 | return section.mr; |
3334 | } | |
3335 | ||
3336 | /* Called from RCU critical section. address_space_read_cached uses this | |
3337 | * out of line function when the target is an MMIO or IOMMU region. | |
3338 | */ | |
38df19fa | 3339 | MemTxResult |
48564041 | 3340 | address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr, |
0c249ff7 | 3341 | void *buf, hwaddr len) |
48564041 PB |
3342 | { |
3343 | hwaddr addr1, l; | |
3344 | MemoryRegion *mr; | |
3345 | ||
3346 | l = len; | |
bc6b1cec PM |
3347 | mr = address_space_translate_cached(cache, addr, &addr1, &l, false, |
3348 | MEMTXATTRS_UNSPECIFIED); | |
38df19fa PMD |
3349 | return flatview_read_continue(cache->fv, |
3350 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3351 | addr1, l, mr); | |
48564041 PB |
3352 | } |
3353 | ||
3354 | /* Called from RCU critical section. address_space_write_cached uses this | |
3355 | * out of line function when the target is an MMIO or IOMMU region. | |
3356 | */ | |
38df19fa | 3357 | MemTxResult |
48564041 | 3358 | address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, |
0c249ff7 | 3359 | const void *buf, hwaddr len) |
48564041 PB |
3360 | { |
3361 | hwaddr addr1, l; | |
3362 | MemoryRegion *mr; | |
3363 | ||
3364 | l = len; | |
bc6b1cec PM |
3365 | mr = address_space_translate_cached(cache, addr, &addr1, &l, true, |
3366 | MEMTXATTRS_UNSPECIFIED); | |
38df19fa PMD |
3367 | return flatview_write_continue(cache->fv, |
3368 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | |
3369 | addr1, l, mr); | |
1f4e496e PB |
3370 | } |
3371 | ||
3372 | #define ARG1_DECL MemoryRegionCache *cache | |
3373 | #define ARG1 cache | |
48564041 PB |
3374 | #define SUFFIX _cached_slow |
3375 | #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__) | |
48564041 PB |
3376 | #define RCU_READ_LOCK() ((void)0) |
3377 | #define RCU_READ_UNLOCK() ((void)0) | |
139c1837 | 3378 | #include "memory_ldst.c.inc" |
1f4e496e | 3379 | |
5e2972fd | 3380 | /* virtual memory access for debug (includes writing to ROM) */ |
f17ec444 | 3381 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
28c80bfe | 3382 | void *ptr, target_ulong len, bool is_write) |
13eb76e0 | 3383 | { |
a8170e5e | 3384 | hwaddr phys_addr; |
0c249ff7 | 3385 | target_ulong l, page; |
d7ef71ef | 3386 | uint8_t *buf = ptr; |
13eb76e0 | 3387 | |
79ca7a1b | 3388 | cpu_synchronize_state(cpu); |
13eb76e0 | 3389 | while (len > 0) { |
5232e4c7 PM |
3390 | int asidx; |
3391 | MemTxAttrs attrs; | |
ddfc8b96 | 3392 | MemTxResult res; |
5232e4c7 | 3393 | |
13eb76e0 | 3394 | page = addr & TARGET_PAGE_MASK; |
5232e4c7 PM |
3395 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); |
3396 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
13eb76e0 FB |
3397 | /* if no physical page mapped, return an error */ |
3398 | if (phys_addr == -1) | |
3399 | return -1; | |
3400 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3401 | if (l > len) | |
3402 | l = len; | |
5e2972fd | 3403 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
2e38847b | 3404 | if (is_write) { |
ddfc8b96 PMD |
3405 | res = address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, |
3406 | attrs, buf, l); | |
2e38847b | 3407 | } else { |
ddfc8b96 PMD |
3408 | res = address_space_read(cpu->cpu_ases[asidx].as, phys_addr, |
3409 | attrs, buf, l); | |
3410 | } | |
3411 | if (res != MEMTX_OK) { | |
3412 | return -1; | |
2e38847b | 3413 | } |
13eb76e0 FB |
3414 | len -= l; |
3415 | buf += l; | |
3416 | addr += l; | |
3417 | } | |
3418 | return 0; | |
3419 | } | |
038629a6 DDAG |
3420 | |
3421 | /* | |
3422 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
3423 | * target independent. | |
3424 | */ | |
20afaed9 | 3425 | size_t qemu_target_page_size(void) |
038629a6 | 3426 | { |
20afaed9 | 3427 | return TARGET_PAGE_SIZE; |
038629a6 DDAG |
3428 | } |
3429 | ||
46d702b1 JQ |
3430 | int qemu_target_page_bits(void) |
3431 | { | |
3432 | return TARGET_PAGE_BITS; | |
3433 | } | |
3434 | ||
3435 | int qemu_target_page_bits_min(void) | |
3436 | { | |
3437 | return TARGET_PAGE_BITS_MIN; | |
3438 | } | |
8e4a424b | 3439 | |
a8170e5e | 3440 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 3441 | { |
5c8a00ce | 3442 | MemoryRegion*mr; |
149f54b5 | 3443 | hwaddr l = 1; |
41063e1e | 3444 | bool res; |
76f35538 | 3445 | |
694ea274 | 3446 | RCU_READ_LOCK_GUARD(); |
5c8a00ce | 3447 | mr = address_space_translate(&address_space_memory, |
bc6b1cec PM |
3448 | phys_addr, &phys_addr, &l, false, |
3449 | MEMTXATTRS_UNSPECIFIED); | |
76f35538 | 3450 | |
41063e1e | 3451 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); |
41063e1e | 3452 | return res; |
76f35538 | 3453 | } |
bd2fa51f | 3454 | |
e3807054 | 3455 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
bd2fa51f MH |
3456 | { |
3457 | RAMBlock *block; | |
e3807054 | 3458 | int ret = 0; |
bd2fa51f | 3459 | |
694ea274 | 3460 | RCU_READ_LOCK_GUARD(); |
99e15582 | 3461 | RAMBLOCK_FOREACH(block) { |
754cb9c0 | 3462 | ret = func(block, opaque); |
e3807054 DDAG |
3463 | if (ret) { |
3464 | break; | |
3465 | } | |
bd2fa51f | 3466 | } |
e3807054 | 3467 | return ret; |
bd2fa51f | 3468 | } |
d3a5038c DDAG |
3469 | |
3470 | /* | |
3471 | * Unmap pages of memory from start to start+length such that | |
3472 | * they a) read as 0, b) Trigger whatever fault mechanism | |
3473 | * the OS provides for postcopy. | |
3474 | * The pages must be unmapped by the end of the function. | |
3475 | * Returns: 0 on success, none-0 on failure | |
3476 | * | |
3477 | */ | |
3478 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length) | |
3479 | { | |
3480 | int ret = -1; | |
3481 | ||
3482 | uint8_t *host_startaddr = rb->host + start; | |
3483 | ||
619bd31d | 3484 | if (!QEMU_PTR_IS_ALIGNED(host_startaddr, rb->page_size)) { |
d3a5038c DDAG |
3485 | error_report("ram_block_discard_range: Unaligned start address: %p", |
3486 | host_startaddr); | |
3487 | goto err; | |
3488 | } | |
3489 | ||
3490 | if ((start + length) <= rb->used_length) { | |
db144f70 | 3491 | bool need_madvise, need_fallocate; |
619bd31d | 3492 | if (!QEMU_IS_ALIGNED(length, rb->page_size)) { |
72821d93 WY |
3493 | error_report("ram_block_discard_range: Unaligned length: %zx", |
3494 | length); | |
d3a5038c DDAG |
3495 | goto err; |
3496 | } | |
3497 | ||
3498 | errno = ENOTSUP; /* If we are missing MADVISE etc */ | |
3499 | ||
db144f70 DDAG |
3500 | /* The logic here is messy; |
3501 | * madvise DONTNEED fails for hugepages | |
3502 | * fallocate works on hugepages and shmem | |
3503 | */ | |
3504 | need_madvise = (rb->page_size == qemu_host_page_size); | |
3505 | need_fallocate = rb->fd != -1; | |
3506 | if (need_fallocate) { | |
3507 | /* For a file, this causes the area of the file to be zero'd | |
3508 | * if read, and for hugetlbfs also causes it to be unmapped | |
3509 | * so a userfault will trigger. | |
e2fa71f5 DDAG |
3510 | */ |
3511 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
3512 | ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, | |
3513 | start, length); | |
db144f70 DDAG |
3514 | if (ret) { |
3515 | ret = -errno; | |
3516 | error_report("ram_block_discard_range: Failed to fallocate " | |
3517 | "%s:%" PRIx64 " +%zx (%d)", | |
3518 | rb->idstr, start, length, ret); | |
3519 | goto err; | |
3520 | } | |
3521 | #else | |
3522 | ret = -ENOSYS; | |
3523 | error_report("ram_block_discard_range: fallocate not available/file" | |
3524 | "%s:%" PRIx64 " +%zx (%d)", | |
3525 | rb->idstr, start, length, ret); | |
3526 | goto err; | |
e2fa71f5 DDAG |
3527 | #endif |
3528 | } | |
db144f70 DDAG |
3529 | if (need_madvise) { |
3530 | /* For normal RAM this causes it to be unmapped, | |
3531 | * for shared memory it causes the local mapping to disappear | |
3532 | * and to fall back on the file contents (which we just | |
3533 | * fallocate'd away). | |
3534 | */ | |
3535 | #if defined(CONFIG_MADVISE) | |
3536 | ret = madvise(host_startaddr, length, MADV_DONTNEED); | |
3537 | if (ret) { | |
3538 | ret = -errno; | |
3539 | error_report("ram_block_discard_range: Failed to discard range " | |
3540 | "%s:%" PRIx64 " +%zx (%d)", | |
3541 | rb->idstr, start, length, ret); | |
3542 | goto err; | |
3543 | } | |
3544 | #else | |
3545 | ret = -ENOSYS; | |
3546 | error_report("ram_block_discard_range: MADVISE not available" | |
d3a5038c DDAG |
3547 | "%s:%" PRIx64 " +%zx (%d)", |
3548 | rb->idstr, start, length, ret); | |
db144f70 DDAG |
3549 | goto err; |
3550 | #endif | |
d3a5038c | 3551 | } |
db144f70 DDAG |
3552 | trace_ram_block_discard_range(rb->idstr, host_startaddr, length, |
3553 | need_madvise, need_fallocate, ret); | |
d3a5038c DDAG |
3554 | } else { |
3555 | error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64 | |
3556 | "/%zx/" RAM_ADDR_FMT")", | |
3557 | rb->idstr, start, length, rb->used_length); | |
3558 | } | |
3559 | ||
3560 | err: | |
3561 | return ret; | |
3562 | } | |
3563 | ||
a4de8552 JH |
3564 | bool ramblock_is_pmem(RAMBlock *rb) |
3565 | { | |
3566 | return rb->flags & RAM_PMEM; | |
3567 | } | |
3568 | ||
b6b71cb5 | 3569 | static void mtree_print_phys_entries(int start, int end, int skip, int ptr) |
5e8fd947 AK |
3570 | { |
3571 | if (start == end - 1) { | |
b6b71cb5 | 3572 | qemu_printf("\t%3d ", start); |
5e8fd947 | 3573 | } else { |
b6b71cb5 | 3574 | qemu_printf("\t%3d..%-3d ", start, end - 1); |
5e8fd947 | 3575 | } |
b6b71cb5 | 3576 | qemu_printf(" skip=%d ", skip); |
5e8fd947 | 3577 | if (ptr == PHYS_MAP_NODE_NIL) { |
b6b71cb5 | 3578 | qemu_printf(" ptr=NIL"); |
5e8fd947 | 3579 | } else if (!skip) { |
b6b71cb5 | 3580 | qemu_printf(" ptr=#%d", ptr); |
5e8fd947 | 3581 | } else { |
b6b71cb5 | 3582 | qemu_printf(" ptr=[%d]", ptr); |
5e8fd947 | 3583 | } |
b6b71cb5 | 3584 | qemu_printf("\n"); |
5e8fd947 AK |
3585 | } |
3586 | ||
3587 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ | |
3588 | int128_sub((size), int128_one())) : 0) | |
3589 | ||
b6b71cb5 | 3590 | void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root) |
5e8fd947 AK |
3591 | { |
3592 | int i; | |
3593 | ||
b6b71cb5 MA |
3594 | qemu_printf(" Dispatch\n"); |
3595 | qemu_printf(" Physical sections\n"); | |
5e8fd947 AK |
3596 | |
3597 | for (i = 0; i < d->map.sections_nb; ++i) { | |
3598 | MemoryRegionSection *s = d->map.sections + i; | |
3599 | const char *names[] = { " [unassigned]", " [not dirty]", | |
3600 | " [ROM]", " [watch]" }; | |
3601 | ||
b6b71cb5 MA |
3602 | qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx |
3603 | " %s%s%s%s%s", | |
5e8fd947 AK |
3604 | i, |
3605 | s->offset_within_address_space, | |
3606 | s->offset_within_address_space + MR_SIZE(s->mr->size), | |
3607 | s->mr->name ? s->mr->name : "(noname)", | |
3608 | i < ARRAY_SIZE(names) ? names[i] : "", | |
3609 | s->mr == root ? " [ROOT]" : "", | |
3610 | s == d->mru_section ? " [MRU]" : "", | |
3611 | s->mr->is_iommu ? " [iommu]" : ""); | |
3612 | ||
3613 | if (s->mr->alias) { | |
b6b71cb5 | 3614 | qemu_printf(" alias=%s", s->mr->alias->name ? |
5e8fd947 AK |
3615 | s->mr->alias->name : "noname"); |
3616 | } | |
b6b71cb5 | 3617 | qemu_printf("\n"); |
5e8fd947 AK |
3618 | } |
3619 | ||
b6b71cb5 | 3620 | qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n", |
5e8fd947 AK |
3621 | P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip); |
3622 | for (i = 0; i < d->map.nodes_nb; ++i) { | |
3623 | int j, jprev; | |
3624 | PhysPageEntry prev; | |
3625 | Node *n = d->map.nodes + i; | |
3626 | ||
b6b71cb5 | 3627 | qemu_printf(" [%d]\n", i); |
5e8fd947 AK |
3628 | |
3629 | for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) { | |
3630 | PhysPageEntry *pe = *n + j; | |
3631 | ||
3632 | if (pe->ptr == prev.ptr && pe->skip == prev.skip) { | |
3633 | continue; | |
3634 | } | |
3635 | ||
b6b71cb5 | 3636 | mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr); |
5e8fd947 AK |
3637 | |
3638 | jprev = j; | |
3639 | prev = *pe; | |
3640 | } | |
3641 | ||
3642 | if (jprev != ARRAY_SIZE(*n)) { | |
b6b71cb5 | 3643 | mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr); |
5e8fd947 AK |
3644 | } |
3645 | } | |
3646 | } | |
3647 | ||
d24f31db DH |
3648 | /* |
3649 | * If positive, discarding RAM is disabled. If negative, discarding RAM is | |
3650 | * required to work and cannot be disabled. | |
3651 | */ | |
3652 | static int ram_block_discard_disabled; | |
3653 | ||
3654 | int ram_block_discard_disable(bool state) | |
3655 | { | |
3656 | int old; | |
3657 | ||
3658 | if (!state) { | |
d73415a3 | 3659 | qatomic_dec(&ram_block_discard_disabled); |
d24f31db DH |
3660 | return 0; |
3661 | } | |
3662 | ||
3663 | do { | |
d73415a3 | 3664 | old = qatomic_read(&ram_block_discard_disabled); |
d24f31db DH |
3665 | if (old < 0) { |
3666 | return -EBUSY; | |
3667 | } | |
d73415a3 SH |
3668 | } while (qatomic_cmpxchg(&ram_block_discard_disabled, |
3669 | old, old + 1) != old); | |
d24f31db DH |
3670 | return 0; |
3671 | } | |
3672 | ||
3673 | int ram_block_discard_require(bool state) | |
3674 | { | |
3675 | int old; | |
3676 | ||
3677 | if (!state) { | |
d73415a3 | 3678 | qatomic_inc(&ram_block_discard_disabled); |
d24f31db DH |
3679 | return 0; |
3680 | } | |
3681 | ||
3682 | do { | |
d73415a3 | 3683 | old = qatomic_read(&ram_block_discard_disabled); |
d24f31db DH |
3684 | if (old > 0) { |
3685 | return -EBUSY; | |
3686 | } | |
d73415a3 SH |
3687 | } while (qatomic_cmpxchg(&ram_block_discard_disabled, |
3688 | old, old - 1) != old); | |
d24f31db DH |
3689 | return 0; |
3690 | } | |
3691 | ||
3692 | bool ram_block_discard_is_disabled(void) | |
3693 | { | |
d73415a3 | 3694 | return qatomic_read(&ram_block_discard_disabled) > 0; |
d24f31db DH |
3695 | } |
3696 | ||
3697 | bool ram_block_discard_is_required(void) | |
3698 | { | |
d73415a3 | 3699 | return qatomic_read(&ram_block_discard_disabled) < 0; |
d24f31db | 3700 | } |