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target-i386: Introduce x86_cpuid_version_set_family()
[mirror_qemu.git] / target-i386 / cpuid.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
28f52cc0
VR		 30#include "hyperv.h"
31
c6dc6f63
AP		 32/* feature flags taken from "Intel Processor Identification and the CPUID
33 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
34 * between feature naming conventions, aliases may be added.
35 */
36static const char *feature_name[] = {
37 "fpu", "vme", "de", "pse",
38 "tsc", "msr", "pae", "mce",
39 "cx8", "apic", NULL, "sep",
40 "mtrr", "pge", "mca", "cmov",
41 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
42 NULL, "ds" /* Intel dts */, "acpi", "mmx",
43 "fxsr", "sse", "sse2", "ss",
44 "ht" /* Intel htt */, "tm", "ia64", "pbe",
45};
46static const char *ext_feature_name[] = {
f370be3c 47 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 48 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 49 "tm2", "ssse3", "cid", NULL,
e117f772 50 "fma", "cx16", "xtpr", "pdcm",
c6dc6f63 51 NULL, NULL, "dca", "sse4.1|sse4_1",
e117f772
AP		 52 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
53 NULL, "aes", "xsave", "osxsave",
54 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 55};
56static const char *ext2_feature_name[] = {
57 "fpu", "vme", "de", "pse",
58 "tsc", "msr", "pae", "mce",
59 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
60 "mtrr", "pge", "mca", "cmov",
61 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 62 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 63 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 64 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 65};
66static const char *ext3_feature_name[] = {
67 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
68 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 69 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 70 "skinit", "wdt", NULL, NULL,
e117f772 71 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 72 NULL, NULL, NULL, NULL,
73 NULL, NULL, NULL, NULL,
74 NULL, NULL, NULL, NULL,
75};
76
77static const char *kvm_feature_name[] = {
642258c6 78 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL,
c6dc6f63
AP		 79 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
80 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
81 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
82};
83
296acb64
JR		 84static const char *svm_feature_name[] = {
85 "npt", "lbrv", "svm_lock", "nrip_save",
86 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
87 NULL, NULL, "pause_filter", NULL,
88 "pfthreshold", NULL, NULL, NULL,
89 NULL, NULL, NULL, NULL,
90 NULL, NULL, NULL, NULL,
91 NULL, NULL, NULL, NULL,
92 NULL, NULL, NULL, NULL,
93};
94
c6dc6f63
AP		 95/* collects per-function cpuid data
96 */
97typedef struct model_features_t {
98 uint32_t *guest_feat;
99 uint32_t *host_feat;
100 uint32_t check_feat;
101 const char **flag_names;
102 uint32_t cpuid;
103 } model_features_t;
104
105int check_cpuid = 0;
106int enforce_cpuid = 0;
107
bb44e0d1
JK		 108void host_cpuid(uint32_t function, uint32_t count,
109 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 110{
111#if defined(CONFIG_KVM)
a1fd24af
AL		 112 uint32_t vec[4];
113
114#ifdef __x86_64__
115 asm volatile("cpuid"
116 : "=a"(vec[0]), "=b"(vec[1]),
117 "=c"(vec[2]), "=d"(vec[3])
118 : "0"(function), "c"(count) : "cc");
119#else
120 asm volatile("pusha \n\t"
121 "cpuid \n\t"
122 "mov %%eax, 0(%2) \n\t"
123 "mov %%ebx, 4(%2) \n\t"
124 "mov %%ecx, 8(%2) \n\t"
125 "mov %%edx, 12(%2) \n\t"
126 "popa"
127 : : "a"(function), "c"(count), "S"(vec)
128 : "memory", "cc");
129#endif
130
bdde476a 131 if (eax)
a1fd24af 132 *eax = vec[0];
bdde476a 133 if (ebx)
a1fd24af 134 *ebx = vec[1];
bdde476a 135 if (ecx)
a1fd24af 136 *ecx = vec[2];
bdde476a 137 if (edx)
a1fd24af 138 *edx = vec[3];
bdde476a
AP		 139#endif
140}
c6dc6f63
AP		 141
142#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
143
144/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
145 * a substring. ex if !NULL points to the first char after a substring,
146 * otherwise the string is assumed to sized by a terminating nul.
147 * Return lexical ordering of *s1:*s2.
148 */
149static int sstrcmp(const char *s1, const char *e1, const char *s2,
150 const char *e2)
151{
152 for (;;) {
153 if (!*s1 || !*s2 || *s1 != *s2)
154 return (*s1 - *s2);
155 ++s1, ++s2;
156 if (s1 == e1 && s2 == e2)
157 return (0);
158 else if (s1 == e1)
159 return (*s2);
160 else if (s2 == e2)
161 return (*s1);
162 }
163}
164
165/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
166 * '|' delimited (possibly empty) strings in which case search for a match
167 * within the alternatives proceeds left to right. Return 0 for success,
168 * non-zero otherwise.
169 */
170static int altcmp(const char *s, const char *e, const char *altstr)
171{
172 const char *p, *q;
173
174 for (q = p = altstr; ; ) {
175 while (*p && *p != '|')
176 ++p;
177 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
178 return (0);
179 if (!*p)
180 return (1);
181 else
182 q = ++p;
183 }
184}
185
186/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 187 * *pval and return true, otherwise return false
c6dc6f63 188 */
e41e0fc6
JK		 189static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
190 const char **featureset)
c6dc6f63
AP		 191{
192 uint32_t mask;
193 const char **ppc;
e41e0fc6 194 bool found = false;
c6dc6f63 195
e41e0fc6 196 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 197 if (*ppc && !altcmp(s, e, *ppc)) {
198 *pval |= mask;
e41e0fc6 199 found = true;
c6dc6f63 200 }
e41e0fc6
JK		 201 }
202 return found;
c6dc6f63
AP		 203}
204
205static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
206 uint32_t *ext_features,
207 uint32_t *ext2_features,
208 uint32_t *ext3_features,
296acb64
JR		 209 uint32_t *kvm_features,
210 uint32_t *svm_features)
c6dc6f63
AP		 211{
212 if (!lookup_feature(features, flagname, NULL, feature_name) &&
213 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
214 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
215 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 216 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
217 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 218 fprintf(stderr, "CPU feature %s not found\n", flagname);
219}
220
221typedef struct x86_def_t {
222 struct x86_def_t *next;
223 const char *name;
224 uint32_t level;
225 uint32_t vendor1, vendor2, vendor3;
226 int family;
227 int model;
228 int stepping;
b862d1fe 229 int tsc_khz;
296acb64
JR		 230 uint32_t features, ext_features, ext2_features, ext3_features;
231 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 232 uint32_t xlevel;
233 char model_id[48];
234 int vendor_override;
235 uint32_t flags;
b3baa152
BW		 236 /* Store the results of Centaur's CPUID instructions */
237 uint32_t ext4_features;
238 uint32_t xlevel2;
c6dc6f63
AP		 239} x86_def_t;
240
241#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
242#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
243 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
244#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
245 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
246 CPUID_PSE36 | CPUID_FXSR)
247#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
248#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
249 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
250 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
251 CPUID_PAE | CPUID_SEP | CPUID_APIC)
42673936 252#define EXT2_FEATURE_MASK 0x0183F3FF
c6dc6f63 253
551a2dec
AP		 254#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
255 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
256 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
257 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
258 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 259 /* partly implemented:
260 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
261 CPUID_PSE36 (needed for Solaris) */
262 /* missing:
263 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 264#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 265 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 266 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 267 /* missing:
268 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 269 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
551a2dec
AP		 270#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
271 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
272 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 273 /* missing:
274 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 275#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
276 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 277#define TCG_SVM_FEATURES 0
551a2dec 278
c6dc6f63
AP		 279/* maintains list of cpu model definitions
280 */
281static x86_def_t *x86_defs = {NULL};
282
283/* built-in cpu model definitions (deprecated)
284 */
285static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 286 {
287 .name = "qemu64",
288 .level = 4,
289 .vendor1 = CPUID_VENDOR_AMD_1,
290 .vendor2 = CPUID_VENDOR_AMD_2,
291 .vendor3 = CPUID_VENDOR_AMD_3,
292 .family = 6,
293 .model = 2,
294 .stepping = 3,
295 .features = PPRO_FEATURES |
c6dc6f63 296 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 297 CPUID_PSE36,
298 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
42673936 299 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 300 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
301 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
302 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
303 .xlevel = 0x8000000A,
304 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
305 },
306 {
307 .name = "phenom",
308 .level = 5,
309 .vendor1 = CPUID_VENDOR_AMD_1,
310 .vendor2 = CPUID_VENDOR_AMD_2,
311 .vendor3 = CPUID_VENDOR_AMD_3,
312 .family = 16,
313 .model = 2,
314 .stepping = 3,
c6dc6f63
AP		 315 .features = PPRO_FEATURES |
316 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 317 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 318 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
319 CPUID_EXT_POPCNT,
42673936 320 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 321 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
322 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 323 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 324 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
325 CPUID_EXT3_CR8LEG,
326 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
327 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
328 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
329 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 330 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 331 .xlevel = 0x8000001A,
332 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
333 },
334 {
335 .name = "core2duo",
336 .level = 10,
337 .family = 6,
338 .model = 15,
339 .stepping = 11,
c6dc6f63
AP		 340 .features = PPRO_FEATURES |
341 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 342 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
343 CPUID_HT | CPUID_TM | CPUID_PBE,
344 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
345 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
346 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 347 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
348 .ext3_features = CPUID_EXT3_LAHF_LM,
349 .xlevel = 0x80000008,
350 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
351 },
352 {
353 .name = "kvm64",
354 .level = 5,
355 .vendor1 = CPUID_VENDOR_INTEL_1,
356 .vendor2 = CPUID_VENDOR_INTEL_2,
357 .vendor3 = CPUID_VENDOR_INTEL_3,
358 .family = 15,
359 .model = 6,
360 .stepping = 1,
361 /* Missing: CPUID_VME, CPUID_HT */
362 .features = PPRO_FEATURES |
363 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
364 CPUID_PSE36,
365 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
366 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
367 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
42673936 368 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 369 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
370 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
371 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
372 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
373 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
374 .ext3_features = 0,
375 .xlevel = 0x80000008,
376 .model_id = "Common KVM processor"
377 },
c6dc6f63
AP		 378 {
379 .name = "qemu32",
380 .level = 4,
381 .family = 6,
382 .model = 3,
383 .stepping = 3,
384 .features = PPRO_FEATURES,
385 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 386 .xlevel = 0x80000004,
c6dc6f63
AP		 387 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
388 },
eafaf1e5
AP		 389 {
390 .name = "kvm32",
391 .level = 5,
392 .family = 15,
393 .model = 6,
394 .stepping = 1,
395 .features = PPRO_FEATURES |
396 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
397 .ext_features = CPUID_EXT_SSE3,
398 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
399 .ext3_features = 0,
400 .xlevel = 0x80000008,
401 .model_id = "Common 32-bit KVM processor"
402 },
c6dc6f63
AP		 403 {
404 .name = "coreduo",
405 .level = 10,
406 .family = 6,
407 .model = 14,
408 .stepping = 8,
c6dc6f63 409 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 410 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
411 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
412 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
413 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 414 .ext2_features = CPUID_EXT2_NX,
415 .xlevel = 0x80000008,
416 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
417 },
418 {
419 .name = "486",
58012d66 420 .level = 1,
c6dc6f63
AP		 421 .family = 4,
422 .model = 0,
423 .stepping = 0,
424 .features = I486_FEATURES,
425 .xlevel = 0,
426 },
427 {
428 .name = "pentium",
429 .level = 1,
430 .family = 5,
431 .model = 4,
432 .stepping = 3,
433 .features = PENTIUM_FEATURES,
434 .xlevel = 0,
435 },
436 {
437 .name = "pentium2",
438 .level = 2,
439 .family = 6,
440 .model = 5,
441 .stepping = 2,
442 .features = PENTIUM2_FEATURES,
443 .xlevel = 0,
444 },
445 {
446 .name = "pentium3",
447 .level = 2,
448 .family = 6,
449 .model = 7,
450 .stepping = 3,
451 .features = PENTIUM3_FEATURES,
452 .xlevel = 0,
453 },
454 {
455 .name = "athlon",
456 .level = 2,
457 .vendor1 = CPUID_VENDOR_AMD_1,
458 .vendor2 = CPUID_VENDOR_AMD_2,
459 .vendor3 = CPUID_VENDOR_AMD_3,
460 .family = 6,
461 .model = 2,
462 .stepping = 3,
463 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
42673936 464 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63
AP		 465 .xlevel = 0x80000008,
466 /* XXX: put another string ? */
467 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
468 },
469 {
470 .name = "n270",
471 /* original is on level 10 */
472 .level = 5,
473 .family = 6,
474 .model = 28,
475 .stepping = 2,
476 .features = PPRO_FEATURES |
8560efed
AJ		 477 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
478 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 479 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 480 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
481 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
42673936 482 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
8560efed 483 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 484 .xlevel = 0x8000000A,
485 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
486 },
487};
488
489static int cpu_x86_fill_model_id(char *str)
490{
491 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
492 int i;
493
494 for (i = 0; i < 3; i++) {
495 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
496 memcpy(str + i * 16 + 0, &eax, 4);
497 memcpy(str + i * 16 + 4, &ebx, 4);
498 memcpy(str + i * 16 + 8, &ecx, 4);
499 memcpy(str + i * 16 + 12, &edx, 4);
500 }
501 return 0;
502}
503
504static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
505{
506 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
507
508 x86_cpu_def->name = "host";
509 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
510 x86_cpu_def->level = eax;
511 x86_cpu_def->vendor1 = ebx;
512 x86_cpu_def->vendor2 = edx;
513 x86_cpu_def->vendor3 = ecx;
514
515 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
516 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
517 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
518 x86_cpu_def->stepping = eax & 0x0F;
519 x86_cpu_def->ext_features = ecx;
520 x86_cpu_def->features = edx;
521
522 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
523 x86_cpu_def->xlevel = eax;
524
525 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
526 x86_cpu_def->ext2_features = edx;
527 x86_cpu_def->ext3_features = ecx;
528 cpu_x86_fill_model_id(x86_cpu_def->model_id);
529 x86_cpu_def->vendor_override = 0;
530
b3baa152
BW		 531 /* Call Centaur's CPUID instruction. */
532 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
533 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
534 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
535 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
536 if (eax >= 0xC0000001) {
537 /* Support VIA max extended level */
538 x86_cpu_def->xlevel2 = eax;
539 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
540 x86_cpu_def->ext4_features = edx;
541 }
542 }
296acb64
JR		 543
544 /*
545 * Every SVM feature requires emulation support in KVM - so we can't just
546 * read the host features here. KVM might even support SVM features not
547 * available on the host hardware. Just set all bits and mask out the
548 * unsupported ones later.
549 */
550 x86_cpu_def->svm_features = -1;
551
c6dc6f63
AP		 552 return 0;
553}
554
555static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
556{
557 int i;
558
559 for (i = 0; i < 32; ++i)
560 if (1 << i & mask) {
561 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
562 " flag '%s' [0x%08x]\n",
563 f->cpuid >> 16, f->cpuid & 0xffff,
564 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
565 break;
566 }
567 return 0;
568}
569
570/* best effort attempt to inform user requested cpu flags aren't making
571 * their way to the guest. Note: ft[].check_feat ideally should be
572 * specified via a guest_def field to suppress report of extraneous flags.
573 */
574static int check_features_against_host(x86_def_t *guest_def)
575{
576 x86_def_t host_def;
577 uint32_t mask;
578 int rv, i;
579 struct model_features_t ft[] = {
580 {&guest_def->features, &host_def.features,
581 ~0, feature_name, 0x00000000},
582 {&guest_def->ext_features, &host_def.ext_features,
583 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
584 {&guest_def->ext2_features, &host_def.ext2_features,
585 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
586 {&guest_def->ext3_features, &host_def.ext3_features,
587 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
588
589 cpu_x86_fill_host(&host_def);
66fe09ee 590 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 591 for (mask = 1; mask; mask <<= 1)
592 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
593 !(*ft[i].host_feat & mask)) {
594 unavailable_host_feature(&ft[i], mask);
595 rv = 1;
596 }
597 return rv;
598}
599
ed5e1ec3
AF		 600static void x86_cpuid_version_set_family(CPUX86State *env, int family)
601{
602 env->cpuid_version &= ~0xff00f00;
603 if (family > 0x0f) {
604 env->cpuid_version |= 0xf00 | ((family - 0x0f) << 20);
605 } else {
606 env->cpuid_version |= family << 8;
607 }
608}
609
c6dc6f63
AP		 610static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
611{
612 unsigned int i;
613 x86_def_t *def;
614
d3c481b3 615 char *s = g_strdup(cpu_model);
c6dc6f63 616 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 617 /* Features to be added*/
618 uint32_t plus_features = 0, plus_ext_features = 0;
619 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
620 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
621 /* Features to be removed */
622 uint32_t minus_features = 0, minus_ext_features = 0;
623 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
624 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 625 uint32_t numvalue;
626
627 for (def = x86_defs; def; def = def->next)
04c5b17a 628 if (name && !strcmp(name, def->name))
c6dc6f63 629 break;
04c5b17a 630 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 631 cpu_x86_fill_host(x86_cpu_def);
632 } else if (!def) {
633 goto error;
634 } else {
635 memcpy(x86_cpu_def, def, sizeof(*def));
636 }
637
638 plus_kvm_features = ~0; /* not supported bits will be filtered out later */
639
640 add_flagname_to_bitmaps("hypervisor", &plus_features,
641 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 642 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 643
644 featurestr = strtok(NULL, ",");
645
646 while (featurestr) {
647 char *val;
648 if (featurestr[0] == '+') {
296acb64
JR		 649 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
650 &plus_ext_features, &plus_ext2_features,
651 &plus_ext3_features, &plus_kvm_features,
652 &plus_svm_features);
c6dc6f63 653 } else if (featurestr[0] == '-') {
296acb64
JR		 654 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
655 &minus_ext_features, &minus_ext2_features,
656 &minus_ext3_features, &minus_kvm_features,
657 &minus_svm_features);
c6dc6f63
AP		 658 } else if ((val = strchr(featurestr, '='))) {
659 *val = 0; val++;
660 if (!strcmp(featurestr, "family")) {
661 char *err;
662 numvalue = strtoul(val, &err, 0);
663 if (!*val || *err) {
664 fprintf(stderr, "bad numerical value %s\n", val);
665 goto error;
666 }
667 x86_cpu_def->family = numvalue;
668 } else if (!strcmp(featurestr, "model")) {
669 char *err;
670 numvalue = strtoul(val, &err, 0);
671 if (!*val || *err || numvalue > 0xff) {
672 fprintf(stderr, "bad numerical value %s\n", val);
673 goto error;
674 }
675 x86_cpu_def->model = numvalue;
676 } else if (!strcmp(featurestr, "stepping")) {
677 char *err;
678 numvalue = strtoul(val, &err, 0);
679 if (!*val || *err || numvalue > 0xf) {
680 fprintf(stderr, "bad numerical value %s\n", val);
681 goto error;
682 }
683 x86_cpu_def->stepping = numvalue ;
684 } else if (!strcmp(featurestr, "level")) {
685 char *err;
686 numvalue = strtoul(val, &err, 0);
687 if (!*val || *err) {
688 fprintf(stderr, "bad numerical value %s\n", val);
689 goto error;
690 }
691 x86_cpu_def->level = numvalue;
692 } else if (!strcmp(featurestr, "xlevel")) {
693 char *err;
694 numvalue = strtoul(val, &err, 0);
695 if (!*val || *err) {
696 fprintf(stderr, "bad numerical value %s\n", val);
697 goto error;
698 }
699 if (numvalue < 0x80000000) {
2f7a21c4 700 numvalue += 0x80000000;
c6dc6f63
AP		 701 }
702 x86_cpu_def->xlevel = numvalue;
703 } else if (!strcmp(featurestr, "vendor")) {
704 if (strlen(val) != 12) {
705 fprintf(stderr, "vendor string must be 12 chars long\n");
706 goto error;
707 }
708 x86_cpu_def->vendor1 = 0;
709 x86_cpu_def->vendor2 = 0;
710 x86_cpu_def->vendor3 = 0;
711 for(i = 0; i < 4; i++) {
712 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
713 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
714 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
715 }
716 x86_cpu_def->vendor_override = 1;
717 } else if (!strcmp(featurestr, "model_id")) {
718 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
719 val);
b862d1fe
JR		 720 } else if (!strcmp(featurestr, "tsc_freq")) {
721 int64_t tsc_freq;
722 char *err;
723
724 tsc_freq = strtosz_suffix_unit(val, &err,
725 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 726 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 727 fprintf(stderr, "bad numerical value %s\n", val);
728 goto error;
729 }
730 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 731 } else if (!strcmp(featurestr, "hv_spinlocks")) {
732 char *err;
733 numvalue = strtoul(val, &err, 0);
734 if (!*val || *err) {
735 fprintf(stderr, "bad numerical value %s\n", val);
736 goto error;
737 }
738 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 739 } else {
740 fprintf(stderr, "unrecognized feature %s\n", featurestr);
741 goto error;
742 }
743 } else if (!strcmp(featurestr, "check")) {
744 check_cpuid = 1;
745 } else if (!strcmp(featurestr, "enforce")) {
746 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 747 } else if (!strcmp(featurestr, "hv_relaxed")) {
748 hyperv_enable_relaxed_timing(true);
749 } else if (!strcmp(featurestr, "hv_vapic")) {
750 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 751 } else {
752 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
753 goto error;
754 }
755 featurestr = strtok(NULL, ",");
756 }
757 x86_cpu_def->features |= plus_features;
758 x86_cpu_def->ext_features |= plus_ext_features;
759 x86_cpu_def->ext2_features |= plus_ext2_features;
760 x86_cpu_def->ext3_features |= plus_ext3_features;
761 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 762 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 763 x86_cpu_def->features &= ~minus_features;
764 x86_cpu_def->ext_features &= ~minus_ext_features;
765 x86_cpu_def->ext2_features &= ~minus_ext2_features;
766 x86_cpu_def->ext3_features &= ~minus_ext3_features;
767 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 768 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 769 if (check_cpuid) {
770 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
771 goto error;
772 }
d3c481b3 773 g_free(s);
c6dc6f63
AP		 774 return 0;
775
776error:
d3c481b3 777 g_free(s);
c6dc6f63
AP		 778 return -1;
779}
780
781/* generate a composite string into buf of all cpuid names in featureset
782 * selected by fbits. indicate truncation at bufsize in the event of overflow.
783 * if flags, suppress names undefined in featureset.
784 */
785static void listflags(char *buf, int bufsize, uint32_t fbits,
786 const char **featureset, uint32_t flags)
787{
788 const char **p = &featureset[31];
789 char *q, *b, bit;
790 int nc;
791
792 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
793 *buf = '\0';
794 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
795 if (fbits & 1 << bit && (*p || !flags)) {
796 if (*p)
797 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
798 else
799 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
800 if (bufsize <= nc) {
801 if (b) {
802 memcpy(b, "...", sizeof("..."));
803 }
804 return;
805 }
806 q += nc;
807 bufsize -= nc;
808 }
809}
810
811/* generate CPU information:
812 * -? list model names
813 * -?model list model names/IDs
814 * -?dump output all model (x86_def_t) data
815 * -?cpuid list all recognized cpuid flag names
816 */
9a78eead 817void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
c6dc6f63
AP		 818{
819 unsigned char model = !strcmp("?model", optarg);
820 unsigned char dump = !strcmp("?dump", optarg);
821 unsigned char cpuid = !strcmp("?cpuid", optarg);
822 x86_def_t *def;
823 char buf[256];
824
825 if (cpuid) {
826 (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
827 listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
828 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
829 listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
830 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
831 listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
832 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
833 listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
834 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
835 return;
836 }
837 for (def = x86_defs; def; def = def->next) {
838 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
839 if (model || dump) {
840 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
841 } else {
842 (*cpu_fprintf)(f, "x86 %16s\n", buf);
843 }
844 if (dump) {
845 memcpy(buf, &def->vendor1, sizeof (def->vendor1));
846 memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
847 memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
848 buf[12] = '\0';
849 (*cpu_fprintf)(f,
850 " family %d model %d stepping %d level %d xlevel 0x%x"
851 " vendor \"%s\"\n",
852 def->family, def->model, def->stepping, def->level,
853 def->xlevel, buf);
854 listflags(buf, sizeof (buf), def->features, feature_name, 0);
855 (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
856 buf);
857 listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
858 0);
859 (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
860 buf);
861 listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
862 0);
863 (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
864 def->ext2_features, buf);
865 listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
866 0);
867 (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
868 def->ext3_features, buf);
869 (*cpu_fprintf)(f, "\n");
870 }
871 }
ed2c54d4
AP		 872 if (kvm_enabled()) {
873 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
874 }
c6dc6f63
AP		 875}
876
877int cpu_x86_register (CPUX86State *env, const char *cpu_model)
878{
879 x86_def_t def1, *def = &def1;
880
db0ad1ba
JR		 881 memset(def, 0, sizeof(*def));
882
c6dc6f63
AP		 883 if (cpu_x86_find_by_name(def, cpu_model) < 0)
884 return -1;
885 if (def->vendor1) {
886 env->cpuid_vendor1 = def->vendor1;
887 env->cpuid_vendor2 = def->vendor2;
888 env->cpuid_vendor3 = def->vendor3;
889 } else {
890 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
891 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
892 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
893 }
894 env->cpuid_vendor_override = def->vendor_override;
895 env->cpuid_level = def->level;
ed5e1ec3 896 x86_cpuid_version_set_family(env, def->family);
c6dc6f63
AP		 897 env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16);
898 env->cpuid_version |= def->stepping;
899 env->cpuid_features = def->features;
c6dc6f63
AP		 900 env->cpuid_ext_features = def->ext_features;
901 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 902 env->cpuid_ext3_features = def->ext3_features;
c6dc6f63
AP		 903 env->cpuid_xlevel = def->xlevel;
904 env->cpuid_kvm_features = def->kvm_features;
296acb64 905 env->cpuid_svm_features = def->svm_features;
b3baa152
BW		 906 env->cpuid_ext4_features = def->ext4_features;
907 env->cpuid_xlevel2 = def->xlevel2;
b862d1fe 908 env->tsc_khz = def->tsc_khz;
551a2dec
AP		 909 if (!kvm_enabled()) {
910 env->cpuid_features &= TCG_FEATURES;
911 env->cpuid_ext_features &= TCG_EXT_FEATURES;
912 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
913#ifdef TARGET_X86_64
914 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
915#endif
916 );
917 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 918 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 919 }
c6dc6f63
AP		 920 {
921 const char *model_id = def->model_id;
922 int c, len, i;
923 if (!model_id)
924 model_id = "";
925 len = strlen(model_id);
926 for(i = 0; i < 48; i++) {
927 if (i >= len)
928 c = '\0';
929 else
930 c = (uint8_t)model_id[i];
931 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
932 }
933 }
934 return 0;
935}
936
937#if !defined(CONFIG_USER_ONLY)
938/* copy vendor id string to 32 bit register, nul pad as needed
939 */
940static void cpyid(const char *s, uint32_t *id)
941{
942 char *d = (char *)id;
943 char i;
944
945 for (i = sizeof (*id); i--; )
946 *d++ = *s ? *s++ : '\0';
947}
948
949/* interpret radix and convert from string to arbitrary scalar,
950 * otherwise flag failure
951 */
952#define setscalar(pval, str, perr) \
953{ \
954 char *pend; \
955 unsigned long ul; \
956 \
957 ul = strtoul(str, &pend, 0); \
958 *str && !*pend ? (*pval = ul) : (*perr = 1); \
959}
960
961/* map cpuid options to feature bits, otherwise return failure
962 * (option tags in *str are delimited by whitespace)
963 */
964static void setfeatures(uint32_t *pval, const char *str,
965 const char **featureset, int *perr)
966{
967 const char *p, *q;
968
969 for (q = p = str; *p || *q; q = p) {
970 while (iswhite(*p))
971 q = ++p;
972 while (*p && !iswhite(*p))
973 ++p;
974 if (!*q && !*p)
975 return;
976 if (!lookup_feature(pval, q, p, featureset)) {
977 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
978 (int)(p - q), q);
979 *perr = 1;
980 return;
981 }
982 }
983}
984
985/* map config file options to x86_def_t form
986 */
987static int cpudef_setfield(const char *name, const char *str, void *opaque)
988{
989 x86_def_t *def = opaque;
990 int err = 0;
991
992 if (!strcmp(name, "name")) {
99e1dec0 993 g_free((void *)def->name);
d3c481b3 994 def->name = g_strdup(str);
c6dc6f63
AP		 995 } else if (!strcmp(name, "model_id")) {
996 strncpy(def->model_id, str, sizeof (def->model_id));
997 } else if (!strcmp(name, "level")) {
998 setscalar(&def->level, str, &err)
999 } else if (!strcmp(name, "vendor")) {
1000 cpyid(&str[0], &def->vendor1);
1001 cpyid(&str[4], &def->vendor2);
1002 cpyid(&str[8], &def->vendor3);
1003 } else if (!strcmp(name, "family")) {
1004 setscalar(&def->family, str, &err)
1005 } else if (!strcmp(name, "model")) {
1006 setscalar(&def->model, str, &err)
1007 } else if (!strcmp(name, "stepping")) {
1008 setscalar(&def->stepping, str, &err)
1009 } else if (!strcmp(name, "feature_edx")) {
1010 setfeatures(&def->features, str, feature_name, &err);
1011 } else if (!strcmp(name, "feature_ecx")) {
1012 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1013 } else if (!strcmp(name, "extfeature_edx")) {
1014 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1015 } else if (!strcmp(name, "extfeature_ecx")) {
1016 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1017 } else if (!strcmp(name, "xlevel")) {
1018 setscalar(&def->xlevel, str, &err)
1019 } else {
1020 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1021 return (1);
1022 }
1023 if (err) {
1024 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1025 return (1);
1026 }
1027 return (0);
1028}
1029
1030/* register config file entry as x86_def_t
1031 */
1032static int cpudef_register(QemuOpts *opts, void *opaque)
1033{
7267c094 1034 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
c6dc6f63
AP		 1035
1036 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1037 def->next = x86_defs;
1038 x86_defs = def;
1039 return (0);
1040}
0e26b7b8
BS		 1041
1042void cpu_clear_apic_feature(CPUX86State *env)
1043{
1044 env->cpuid_features &= ~CPUID_APIC;
1045}
1046
c6dc6f63
AP		 1047#endif /* !CONFIG_USER_ONLY */
1048
1049/* register "cpudef" models defined in configuration file. Here we first
1050 * preload any built-in definitions
1051 */
1052void x86_cpudef_setup(void)
1053{
1054 int i;
1055
1056 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1057 builtin_x86_defs[i].next = x86_defs;
1058 builtin_x86_defs[i].flags = 1;
1059 x86_defs = &builtin_x86_defs[i];
1060 }
1061#if !defined(CONFIG_USER_ONLY)
3329f07b 1062 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
c6dc6f63
AP		 1063#endif
1064}
1065
c6dc6f63
AP		 1066static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1067 uint32_t *ecx, uint32_t *edx)
1068{
1069 *ebx = env->cpuid_vendor1;
1070 *edx = env->cpuid_vendor2;
1071 *ecx = env->cpuid_vendor3;
1072
1073 /* sysenter isn't supported on compatibility mode on AMD, syscall
1074 * isn't supported in compatibility mode on Intel.
1075 * Normally we advertise the actual cpu vendor, but you can override
1076 * this if you want to use KVM's sysenter/syscall emulation
1077 * in compatibility mode and when doing cross vendor migration
1078 */
89354998 1079 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1080 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1081 }
1082}
1083
1084void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1085 uint32_t *eax, uint32_t *ebx,
1086 uint32_t *ecx, uint32_t *edx)
1087{
1088 /* test if maximum index reached */
1089 if (index & 0x80000000) {
b3baa152
BW		 1090 if (index > env->cpuid_xlevel) {
1091 if (env->cpuid_xlevel2 > 0) {
1092 /* Handle the Centaur's CPUID instruction. */
1093 if (index > env->cpuid_xlevel2) {
1094 index = env->cpuid_xlevel2;
1095 } else if (index < 0xC0000000) {
1096 index = env->cpuid_xlevel;
1097 }
1098 } else {
1099 index = env->cpuid_xlevel;
1100 }
1101 }
c6dc6f63
AP		 1102 } else {
1103 if (index > env->cpuid_level)
1104 index = env->cpuid_level;
1105 }
1106
1107 switch(index) {
1108 case 0:
1109 *eax = env->cpuid_level;
1110 get_cpuid_vendor(env, ebx, ecx, edx);
1111 break;
1112 case 1:
1113 *eax = env->cpuid_version;
1114 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1115 *ecx = env->cpuid_ext_features;
1116 *edx = env->cpuid_features;
1117 if (env->nr_cores * env->nr_threads > 1) {
1118 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1119 *edx |= 1 << 28; /* HTT bit */
1120 }
1121 break;
1122 case 2:
1123 /* cache info: needed for Pentium Pro compatibility */
1124 *eax = 1;
1125 *ebx = 0;
1126 *ecx = 0;
1127 *edx = 0x2c307d;
1128 break;
1129 case 4:
1130 /* cache info: needed for Core compatibility */
1131 if (env->nr_cores > 1) {
2f7a21c4 1132 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1133 } else {
2f7a21c4 1134 *eax = 0;
c6dc6f63
AP		 1135 }
1136 switch (count) {
1137 case 0: /* L1 dcache info */
1138 *eax |= 0x0000121;
1139 *ebx = 0x1c0003f;
1140 *ecx = 0x000003f;
1141 *edx = 0x0000001;
1142 break;
1143 case 1: /* L1 icache info */
1144 *eax |= 0x0000122;
1145 *ebx = 0x1c0003f;
1146 *ecx = 0x000003f;
1147 *edx = 0x0000001;
1148 break;
1149 case 2: /* L2 cache info */
1150 *eax |= 0x0000143;
1151 if (env->nr_threads > 1) {
1152 *eax |= (env->nr_threads - 1) << 14;
1153 }
1154 *ebx = 0x3c0003f;
1155 *ecx = 0x0000fff;
1156 *edx = 0x0000001;
1157 break;
1158 default: /* end of info */
1159 *eax = 0;
1160 *ebx = 0;
1161 *ecx = 0;
1162 *edx = 0;
1163 break;
1164 }
1165 break;
1166 case 5:
1167 /* mwait info: needed for Core compatibility */
1168 *eax = 0; /* Smallest monitor-line size in bytes */
1169 *ebx = 0; /* Largest monitor-line size in bytes */
1170 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1171 *edx = 0;
1172 break;
1173 case 6:
1174 /* Thermal and Power Leaf */
1175 *eax = 0;
1176 *ebx = 0;
1177 *ecx = 0;
1178 *edx = 0;
1179 break;
f7911686
YW		 1180 case 7:
1181 if (kvm_enabled()) {
ba9bc59e
JK		 1182 KVMState *s = env->kvm_state;
1183
1184 *eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX);
1185 *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
1186 *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
1187 *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
f7911686
YW		 1188 } else {
1189 *eax = 0;
1190 *ebx = 0;
1191 *ecx = 0;
1192 *edx = 0;
1193 }
1194 break;
c6dc6f63
AP		 1195 case 9:
1196 /* Direct Cache Access Information Leaf */
1197 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1198 *ebx = 0;
1199 *ecx = 0;
1200 *edx = 0;
1201 break;
1202 case 0xA:
1203 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1204 if (kvm_enabled()) {
1205 KVMState *s = env->kvm_state;
1206
1207 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1208 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1209 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1210 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1211 } else {
1212 *eax = 0;
1213 *ebx = 0;
1214 *ecx = 0;
1215 *edx = 0;
1216 }
c6dc6f63 1217 break;
51e49430
SY		 1218 case 0xD:
1219 /* Processor Extended State */
1220 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1221 *eax = 0;
1222 *ebx = 0;
1223 *ecx = 0;
1224 *edx = 0;
1225 break;
1226 }
1227 if (kvm_enabled()) {
ba9bc59e
JK		 1228 KVMState *s = env->kvm_state;
1229
1230 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1231 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1232 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1233 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1234 } else {
1235 *eax = 0;
1236 *ebx = 0;
1237 *ecx = 0;
1238 *edx = 0;
1239 }
1240 break;
c6dc6f63
AP		 1241 case 0x80000000:
1242 *eax = env->cpuid_xlevel;
1243 *ebx = env->cpuid_vendor1;
1244 *edx = env->cpuid_vendor2;
1245 *ecx = env->cpuid_vendor3;
1246 break;
1247 case 0x80000001:
1248 *eax = env->cpuid_version;
1249 *ebx = 0;
1250 *ecx = env->cpuid_ext3_features;
1251 *edx = env->cpuid_ext2_features;
1252
1253 /* The Linux kernel checks for the CMPLegacy bit and
1254 * discards multiple thread information if it is set.
1255 * So dont set it here for Intel to make Linux guests happy.
1256 */
1257 if (env->nr_cores * env->nr_threads > 1) {
1258 uint32_t tebx, tecx, tedx;
1259 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1260 if (tebx != CPUID_VENDOR_INTEL_1 ||
1261 tedx != CPUID_VENDOR_INTEL_2 ||
1262 tecx != CPUID_VENDOR_INTEL_3) {
1263 *ecx |= 1 << 1; /* CmpLegacy bit */
1264 }
1265 }
c6dc6f63
AP		 1266 break;
1267 case 0x80000002:
1268 case 0x80000003:
1269 case 0x80000004:
1270 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1271 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1272 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1273 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1274 break;
1275 case 0x80000005:
1276 /* cache info (L1 cache) */
1277 *eax = 0x01ff01ff;
1278 *ebx = 0x01ff01ff;
1279 *ecx = 0x40020140;
1280 *edx = 0x40020140;
1281 break;
1282 case 0x80000006:
1283 /* cache info (L2 cache) */
1284 *eax = 0;
1285 *ebx = 0x42004200;
1286 *ecx = 0x02008140;
1287 *edx = 0;
1288 break;
1289 case 0x80000008:
1290 /* virtual & phys address size in low 2 bytes. */
1291/* XXX: This value must match the one used in the MMU code. */
1292 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1293 /* 64 bit processor */
1294/* XXX: The physical address space is limited to 42 bits in exec.c. */
1295 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1296 } else {
1297 if (env->cpuid_features & CPUID_PSE36)
1298 *eax = 0x00000024; /* 36 bits physical */
1299 else
1300 *eax = 0x00000020; /* 32 bits physical */
1301 }
1302 *ebx = 0;
1303 *ecx = 0;
1304 *edx = 0;
1305 if (env->nr_cores * env->nr_threads > 1) {
1306 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1307 }
1308 break;
1309 case 0x8000000A:
296acb64
JR		 1310 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1311 *eax = 0x00000001; /* SVM Revision */
1312 *ebx = 0x00000010; /* nr of ASIDs */
1313 *ecx = 0;
1314 *edx = env->cpuid_svm_features; /* optional features */
1315 } else {
1316 *eax = 0;
1317 *ebx = 0;
1318 *ecx = 0;
1319 *edx = 0;
1320 }
c6dc6f63 1321 break;
b3baa152
BW		 1322 case 0xC0000000:
1323 *eax = env->cpuid_xlevel2;
1324 *ebx = 0;
1325 *ecx = 0;
1326 *edx = 0;
1327 break;
1328 case 0xC0000001:
1329 /* Support for VIA CPU's CPUID instruction */
1330 *eax = env->cpuid_version;
1331 *ebx = 0;
1332 *ecx = 0;
1333 *edx = env->cpuid_ext4_features;
1334 break;
1335 case 0xC0000002:
1336 case 0xC0000003:
1337 case 0xC0000004:
1338 /* Reserved for the future, and now filled with zero */
1339 *eax = 0;
1340 *ebx = 0;
1341 *ecx = 0;
1342 *edx = 0;
1343 break;
c6dc6f63
AP		 1344 default:
1345 /* reserved values: zero */
1346 *eax = 0;
1347 *ebx = 0;
1348 *ecx = 0;
1349 *edx = 0;
1350 break;
1351 }
1352}
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