2 * User emulator execution
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "hw/core/tcg-cpu-ops.h"
21 #include "disas/disas.h"
22 #include "exec/exec-all.h"
24 #include "qemu/bitops.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/translate-all.h"
27 #include "exec/helper-proto.h"
28 #include "qemu/atomic128.h"
29 #include "trace/trace-root.h"
30 #include "trace/mem.h"
42 #include <sys/ucontext.h>
45 __thread
uintptr_t helper_retaddr
;
47 //#define DEBUG_SIGNAL
49 /* exit the current TB from a signal handler. The host registers are
50 restored in a state compatible with the CPU emulator
52 static void QEMU_NORETURN
cpu_exit_tb_from_sighandler(CPUState
*cpu
,
55 /* XXX: use siglongjmp ? */
56 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
57 cpu_loop_exit_noexc(cpu
);
60 /* 'pc' is the host PC at which the exception was raised. 'address' is
61 the effective address of the memory exception. 'is_write' is 1 if a
62 write caused the exception and otherwise 0'. 'old_set' is the
63 signal set which should be restored */
64 static inline int handle_cpu_signal(uintptr_t pc
, siginfo_t
*info
,
65 int is_write
, sigset_t
*old_set
)
67 CPUState
*cpu
= current_cpu
;
69 unsigned long address
= (unsigned long)info
->si_addr
;
70 MMUAccessType access_type
= is_write
? MMU_DATA_STORE
: MMU_DATA_LOAD
;
72 switch (helper_retaddr
) {
75 * Fault during host memory operation within a helper function.
76 * The helper's host return address, saved here, gives us a
77 * pointer into the generated code that will unwind to the
85 * Fault during host memory operation within generated code.
86 * (Or, a unrelated bug within qemu, but we can't tell from here).
88 * We take the host pc from the signal frame. However, we cannot
89 * use that value directly. Within cpu_restore_state_from_tb, we
90 * assume PC comes from GETPC(), as used by the helper functions,
91 * so we adjust the address by -GETPC_ADJ to form an address that
92 * is within the call insn, so that the address does not accidentally
93 * match the beginning of the next guest insn. However, when the
94 * pc comes from the signal frame it points to the actual faulting
95 * host memory insn and not the return from a call insn.
97 * Therefore, adjust to compensate for what will be done later
98 * by cpu_restore_state_from_tb.
105 * Fault during host read for translation, or loosely, "execution".
107 * The guest pc is already pointing to the start of the TB for which
108 * code is being generated. If the guest translator manages the
109 * page crossings correctly, this is exactly the correct address
110 * (and if the translator doesn't handle page boundaries correctly
111 * there's little we can do about that here). Therefore, do not
112 * trigger the unwinder.
114 * Like tb_gen_code, release the memory lock before cpu_loop_exit.
117 access_type
= MMU_INST_FETCH
;
122 /* For synchronous signals we expect to be coming from the vCPU
123 * thread (so current_cpu should be valid) and either from running
124 * code or during translation which can fault as we cross pages.
126 * If neither is true then something has gone wrong and we should
127 * abort rather than try and restart the vCPU execution.
129 if (!cpu
|| !cpu
->running
) {
130 printf("qemu:%s received signal outside vCPU context @ pc=0x%"
131 PRIxPTR
"\n", __func__
, pc
);
135 #if defined(DEBUG_SIGNAL)
136 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
137 pc
, address
, is_write
, *(unsigned long *)old_set
);
139 /* XXX: locking issue */
140 /* Note that it is important that we don't call page_unprotect() unless
141 * this is really a "write to nonwriteable page" fault, because
142 * page_unprotect() assumes that if it is called for an access to
143 * a page that's writeable this means we had two threads racing and
144 * another thread got there first and already made the page writeable;
145 * so we will retry the access. If we were to call page_unprotect()
146 * for some other kind of fault that should really be passed to the
147 * guest, we'd end up in an infinite loop of retrying the faulting
150 if (is_write
&& info
->si_signo
== SIGSEGV
&& info
->si_code
== SEGV_ACCERR
&&
151 h2g_valid(address
)) {
152 switch (page_unprotect(h2g(address
), pc
)) {
154 /* Fault not caused by a page marked unwritable to protect
155 * cached translations, must be the guest binary's problem.
159 /* Fault caused by protection of cached translation; TBs
160 * invalidated, so resume execution. Retain helper_retaddr
161 * for a possible second fault.
165 /* Fault caused by protection of cached translation, and the
166 * currently executing TB was modified and must be exited
167 * immediately. Clear helper_retaddr for next execution.
169 clear_helper_retaddr();
170 cpu_exit_tb_from_sighandler(cpu
, old_set
);
174 g_assert_not_reached();
178 /* Convert forcefully to guest address space, invalid addresses
179 are still valid segv ones */
180 address
= h2g_nocheck(address
);
183 * There is no way the target can handle this other than raising
184 * an exception. Undo signal and retaddr state prior to longjmp.
186 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
187 clear_helper_retaddr();
189 cc
= CPU_GET_CLASS(cpu
);
190 cc
->tcg_ops
->tlb_fill(cpu
, address
, 0, access_type
,
191 MMU_USER_IDX
, false, pc
);
192 g_assert_not_reached();
195 static int probe_access_internal(CPUArchState
*env
, target_ulong addr
,
196 int fault_size
, MMUAccessType access_type
,
197 bool nonfault
, uintptr_t ra
)
201 switch (access_type
) {
212 g_assert_not_reached();
215 if (!guest_addr_valid_untagged(addr
) ||
216 page_check_range(addr
, 1, flags
) < 0) {
218 return TLB_INVALID_MASK
;
220 CPUState
*cpu
= env_cpu(env
);
221 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
222 cc
->tcg_ops
->tlb_fill(cpu
, addr
, fault_size
, access_type
,
223 MMU_USER_IDX
, false, ra
);
224 g_assert_not_reached();
230 int probe_access_flags(CPUArchState
*env
, target_ulong addr
,
231 MMUAccessType access_type
, int mmu_idx
,
232 bool nonfault
, void **phost
, uintptr_t ra
)
236 flags
= probe_access_internal(env
, addr
, 0, access_type
, nonfault
, ra
);
237 *phost
= flags
? NULL
: g2h(env_cpu(env
), addr
);
241 void *probe_access(CPUArchState
*env
, target_ulong addr
, int size
,
242 MMUAccessType access_type
, int mmu_idx
, uintptr_t ra
)
246 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
247 flags
= probe_access_internal(env
, addr
, size
, access_type
, false, ra
);
248 g_assert(flags
== 0);
250 return size
? g2h(env_cpu(env
), addr
) : NULL
;
253 #if defined(__i386__)
255 #if defined(__NetBSD__)
256 #include <ucontext.h>
257 #include <machine/trap.h>
259 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
260 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
261 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
262 #define MASK_sig(context) ((context)->uc_sigmask)
263 #define PAGE_FAULT_TRAP T_PAGEFLT
264 #elif defined(__FreeBSD__) || defined(__DragonFly__)
265 #include <ucontext.h>
266 #include <machine/trap.h>
268 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
269 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
270 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
271 #define MASK_sig(context) ((context)->uc_sigmask)
272 #define PAGE_FAULT_TRAP T_PAGEFLT
273 #elif defined(__OpenBSD__)
274 #include <machine/trap.h>
275 #define EIP_sig(context) ((context)->sc_eip)
276 #define TRAP_sig(context) ((context)->sc_trapno)
277 #define ERROR_sig(context) ((context)->sc_err)
278 #define MASK_sig(context) ((context)->sc_mask)
279 #define PAGE_FAULT_TRAP T_PAGEFLT
281 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
282 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
283 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
284 #define MASK_sig(context) ((context)->uc_sigmask)
285 #define PAGE_FAULT_TRAP 0xe
288 int cpu_signal_handler(int host_signum
, void *pinfo
,
291 siginfo_t
*info
= pinfo
;
292 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
293 ucontext_t
*uc
= puc
;
294 #elif defined(__OpenBSD__)
295 struct sigcontext
*uc
= puc
;
297 ucontext_t
*uc
= puc
;
306 #define REG_TRAPNO TRAPNO
309 trapno
= TRAP_sig(uc
);
310 return handle_cpu_signal(pc
, info
,
311 trapno
== PAGE_FAULT_TRAP
?
312 (ERROR_sig(uc
) >> 1) & 1 : 0,
316 #elif defined(__x86_64__)
319 #include <machine/trap.h>
320 #define PC_sig(context) _UC_MACHINE_PC(context)
321 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
322 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
323 #define MASK_sig(context) ((context)->uc_sigmask)
324 #define PAGE_FAULT_TRAP T_PAGEFLT
325 #elif defined(__OpenBSD__)
326 #include <machine/trap.h>
327 #define PC_sig(context) ((context)->sc_rip)
328 #define TRAP_sig(context) ((context)->sc_trapno)
329 #define ERROR_sig(context) ((context)->sc_err)
330 #define MASK_sig(context) ((context)->sc_mask)
331 #define PAGE_FAULT_TRAP T_PAGEFLT
332 #elif defined(__FreeBSD__) || defined(__DragonFly__)
333 #include <ucontext.h>
334 #include <machine/trap.h>
336 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
337 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
338 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
339 #define MASK_sig(context) ((context)->uc_sigmask)
340 #define PAGE_FAULT_TRAP T_PAGEFLT
342 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
343 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
344 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
345 #define MASK_sig(context) ((context)->uc_sigmask)
346 #define PAGE_FAULT_TRAP 0xe
349 int cpu_signal_handler(int host_signum
, void *pinfo
,
352 siginfo_t
*info
= pinfo
;
354 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
355 ucontext_t
*uc
= puc
;
356 #elif defined(__OpenBSD__)
357 struct sigcontext
*uc
= puc
;
359 ucontext_t
*uc
= puc
;
363 return handle_cpu_signal(pc
, info
,
364 TRAP_sig(uc
) == PAGE_FAULT_TRAP
?
365 (ERROR_sig(uc
) >> 1) & 1 : 0,
369 #elif defined(_ARCH_PPC)
371 /***********************************************************************
372 * signal context platform-specific definitions
376 /* All Registers access - only for local access */
377 #define REG_sig(reg_name, context) \
378 ((context)->uc_mcontext.regs->reg_name)
379 /* Gpr Registers access */
380 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
381 /* Program counter */
382 #define IAR_sig(context) REG_sig(nip, context)
383 /* Machine State Register (Supervisor) */
384 #define MSR_sig(context) REG_sig(msr, context)
386 #define CTR_sig(context) REG_sig(ctr, context)
387 /* User's integer exception register */
388 #define XER_sig(context) REG_sig(xer, context)
390 #define LR_sig(context) REG_sig(link, context)
391 /* Condition register */
392 #define CR_sig(context) REG_sig(ccr, context)
394 /* Float Registers access */
395 #define FLOAT_sig(reg_num, context) \
396 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
397 #define FPSCR_sig(context) \
398 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
399 /* Exception Registers access */
400 #define DAR_sig(context) REG_sig(dar, context)
401 #define DSISR_sig(context) REG_sig(dsisr, context)
402 #define TRAP_sig(context) REG_sig(trap, context)
405 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
406 #include <ucontext.h>
407 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
408 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
409 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
410 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
411 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
412 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
413 /* Exception Registers access */
414 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
415 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
416 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
417 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
419 int cpu_signal_handler(int host_signum
, void *pinfo
,
422 siginfo_t
*info
= pinfo
;
423 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
424 ucontext_t
*uc
= puc
;
426 ucontext_t
*uc
= puc
;
435 if (DSISR_sig(uc
) & 0x00800000) {
439 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000)) {
443 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
446 #elif defined(__alpha__)
448 int cpu_signal_handler(int host_signum
, void *pinfo
,
451 siginfo_t
*info
= pinfo
;
452 ucontext_t
*uc
= puc
;
453 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
457 /* XXX: need kernel patch to get write flag faster */
458 switch (insn
>> 26) {
461 case 0x0f: /* stq_u */
468 case 0x2e: /* stl_c */
469 case 0x2f: /* stq_c */
473 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
475 #elif defined(__sparc__)
477 int cpu_signal_handler(int host_signum
, void *pinfo
,
480 siginfo_t
*info
= pinfo
;
483 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
484 uint32_t *regs
= (uint32_t *)(info
+ 1);
485 void *sigmask
= (regs
+ 20);
486 /* XXX: is there a standard glibc define ? */
487 unsigned long pc
= regs
[1];
490 struct sigcontext
*sc
= puc
;
491 unsigned long pc
= sc
->sigc_regs
.tpc
;
492 void *sigmask
= (void *)sc
->sigc_mask
;
493 #elif defined(__OpenBSD__)
494 struct sigcontext
*uc
= puc
;
495 unsigned long pc
= uc
->sc_pc
;
496 void *sigmask
= (void *)(long)uc
->sc_mask
;
497 #elif defined(__NetBSD__)
498 ucontext_t
*uc
= puc
;
499 unsigned long pc
= _UC_MACHINE_PC(uc
);
500 void *sigmask
= (void *)&uc
->uc_sigmask
;
504 /* XXX: need kernel patch to get write flag faster */
506 insn
= *(uint32_t *)pc
;
507 if ((insn
>> 30) == 3) {
508 switch ((insn
>> 19) & 0x3f) {
510 case 0x15: /* stba */
512 case 0x16: /* stha */
516 case 0x17: /* stda */
518 case 0x1e: /* stxa */
520 case 0x34: /* stfa */
521 case 0x27: /* stdf */
522 case 0x37: /* stdfa */
523 case 0x26: /* stqf */
524 case 0x36: /* stqfa */
525 case 0x25: /* stfsr */
526 case 0x3c: /* casa */
527 case 0x3e: /* casxa */
532 return handle_cpu_signal(pc
, info
, is_write
, sigmask
);
535 #elif defined(__arm__)
537 #if defined(__NetBSD__)
538 #include <ucontext.h>
539 #include <sys/siginfo.h>
542 int cpu_signal_handler(int host_signum
, void *pinfo
,
545 siginfo_t
*info
= pinfo
;
546 #if defined(__NetBSD__)
547 ucontext_t
*uc
= puc
;
548 siginfo_t
*si
= pinfo
;
550 ucontext_t
*uc
= puc
;
556 #if defined(__NetBSD__)
557 pc
= uc
->uc_mcontext
.__gregs
[_REG_R15
];
558 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
559 pc
= uc
->uc_mcontext
.gregs
[R15
];
561 pc
= uc
->uc_mcontext
.arm_pc
;
567 fsr
= uc
->uc_mcontext
.error_code
;
570 * In the FSR, bit 11 is WnR, assuming a v6 or
571 * later processor. On v5 we will always report
572 * this as a read, which will fail later.
574 is_write
= extract32(fsr
, 11, 1);
575 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
578 #elif defined(__aarch64__)
580 #if defined(__NetBSD__)
582 #include <ucontext.h>
583 #include <sys/siginfo.h>
585 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
587 ucontext_t
*uc
= puc
;
588 siginfo_t
*si
= pinfo
;
593 pc
= uc
->uc_mcontext
.__gregs
[_REG_PC
];
597 * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
598 * is 0b10010x: then bit 6 is the WnR bit
600 is_write
= extract32(esr
, 27, 5) == 0x12 && extract32(esr
, 6, 1) == 1;
601 return handle_cpu_signal(pc
, si
, is_write
, &uc
->uc_sigmask
);
607 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
608 #define ESR_MAGIC 0x45535201
610 struct _aarch64_ctx head
;
615 static inline struct _aarch64_ctx
*first_ctx(ucontext_t
*uc
)
617 return (struct _aarch64_ctx
*)&uc
->uc_mcontext
.__reserved
;
620 static inline struct _aarch64_ctx
*next_ctx(struct _aarch64_ctx
*hdr
)
622 return (struct _aarch64_ctx
*)((char *)hdr
+ hdr
->size
);
625 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
627 siginfo_t
*info
= pinfo
;
628 ucontext_t
*uc
= puc
;
629 uintptr_t pc
= uc
->uc_mcontext
.pc
;
631 struct _aarch64_ctx
*hdr
;
632 struct esr_context
const *esrctx
= NULL
;
634 /* Find the esr_context, which has the WnR bit in it */
635 for (hdr
= first_ctx(uc
); hdr
->magic
; hdr
= next_ctx(hdr
)) {
636 if (hdr
->magic
== ESR_MAGIC
) {
637 esrctx
= (struct esr_context
const *)hdr
;
643 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
644 uint64_t esr
= esrctx
->esr
;
645 is_write
= extract32(esr
, 27, 5) == 0x12 && extract32(esr
, 6, 1) == 1;
648 * Fall back to parsing instructions; will only be needed
649 * for really ancient (pre-3.16) kernels.
651 uint32_t insn
= *(uint32_t *)pc
;
653 is_write
= ((insn
& 0xbfff0000) == 0x0c000000 /* C3.3.1 */
654 || (insn
& 0xbfe00000) == 0x0c800000 /* C3.3.2 */
655 || (insn
& 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
656 || (insn
& 0xbfc00000) == 0x0d800000 /* C3.3.4 */
657 || (insn
& 0x3f400000) == 0x08000000 /* C3.3.6 */
658 || (insn
& 0x3bc00000) == 0x39000000 /* C3.3.13 */
659 || (insn
& 0x3fc00000) == 0x3d800000 /* ... 128bit */
660 /* Ignore bits 10, 11 & 21, controlling indexing. */
661 || (insn
& 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
662 || (insn
& 0x3fe00000) == 0x3c800000 /* ... 128bit */
663 /* Ignore bits 23 & 24, controlling indexing. */
664 || (insn
& 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
666 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
670 #elif defined(__s390__)
672 int cpu_signal_handler(int host_signum
, void *pinfo
,
675 siginfo_t
*info
= pinfo
;
676 ucontext_t
*uc
= puc
;
681 pc
= uc
->uc_mcontext
.psw
.addr
;
684 * ??? On linux, the non-rt signal handler has 4 (!) arguments instead
685 * of the normal 2 arguments. The 4th argument contains the "Translation-
686 * Exception Identification for DAT Exceptions" from the hardware (aka
687 * "int_parm_long"), which does in fact contain the is_write value.
688 * The rt signal handler, as far as I can tell, does not give this value
689 * at all. Not that we could get to it from here even if it were.
690 * So fall back to parsing instructions. Treat read-modify-write ones as
691 * writes, which is not fully correct, but for tracking self-modifying code
692 * this is better than treating them as reads. Checking si_addr page flags
693 * might be a viable improvement, albeit a racy one.
695 /* ??? This is not even close to complete. */
696 pinsn
= (uint16_t *)pc
;
697 switch (pinsn
[0] >> 8) {
705 case 0xc4: /* RIL format insns */
706 switch (pinsn
[0] & 0xf) {
708 case 0xb: /* STGRL */
709 case 0x7: /* STHRL */
713 case 0xc8: /* SSF format insns */
714 switch (pinsn
[0] & 0xf) {
719 case 0xe3: /* RXY format insns */
720 switch (pinsn
[2] & 0xff) {
723 case 0x72: /* STCY */
724 case 0x70: /* STHY */
725 case 0x8e: /* STPQ */
726 case 0x3f: /* STRVH */
727 case 0x3e: /* STRV */
728 case 0x2f: /* STRVG */
732 case 0xeb: /* RSY format insns */
733 switch (pinsn
[2] & 0xff) {
736 case 0x31: /* CDSY */
737 case 0x3e: /* CDSG */
738 case 0xe4: /* LANG */
739 case 0xe6: /* LAOG */
740 case 0xe7: /* LAXG */
741 case 0xe8: /* LAAG */
742 case 0xea: /* LAALG */
746 case 0xfa: /* LAAL */
753 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
756 #elif defined(__mips__)
758 #if defined(__misp16) || defined(__mips_micromips)
759 #error "Unsupported encoding"
762 int cpu_signal_handler(int host_signum
, void *pinfo
,
765 siginfo_t
*info
= pinfo
;
766 ucontext_t
*uc
= puc
;
767 uintptr_t pc
= uc
->uc_mcontext
.pc
;
768 uint32_t insn
= *(uint32_t *)pc
;
771 /* Detect all store instructions at program counter. */
772 switch((insn
>> 26) & 077) {
785 #if !defined(__mips_isa_rev) || __mips_isa_rev < 6
791 case 023: /* COP1X */
792 /* Required in all versions of MIPS64 since
793 MIPS64r1 and subsequent versions of MIPS32r2. */
794 switch (insn
& 077) {
795 case 010: /* SWXC1 */
796 case 011: /* SDXC1 */
797 case 015: /* SUXC1 */
803 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
806 #elif defined(__riscv)
808 int cpu_signal_handler(int host_signum
, void *pinfo
,
811 siginfo_t
*info
= pinfo
;
812 ucontext_t
*uc
= puc
;
813 greg_t pc
= uc
->uc_mcontext
.__gregs
[REG_PC
];
814 uint32_t insn
= *(uint32_t *)pc
;
817 /* Detect store by reading the instruction at the program
818 counter. Note: we currently only generate 32-bit
819 instructions so we thus only detect 32-bit stores */
820 switch (((insn
>> 0) & 0b11)) {
822 switch (((insn
>> 2) & 0b11111)) {
824 switch (((insn
>> 12) & 0b111)) {
837 switch (((insn
>> 12) & 0b111)) {
852 /* Check for compressed instructions */
853 switch (((insn
>> 13) & 0b111)) {
855 switch (insn
& 0b11) {
865 switch (insn
& 0b11) {
878 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
883 #error host CPU specific signal handler needed
887 /* The softmmu versions of these helpers are in cputlb.c. */
889 uint32_t cpu_ldub_data(CPUArchState
*env
, abi_ptr ptr
)
891 MemOpIdx oi
= make_memop_idx(MO_UB
, MMU_USER_IDX
);
892 uint16_t meminfo
= trace_mem_get_info(oi
, false);
895 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
896 ret
= ldub_p(g2h(env_cpu(env
), ptr
));
897 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
901 int cpu_ldsb_data(CPUArchState
*env
, abi_ptr ptr
)
903 return (int8_t)cpu_ldub_data(env
, ptr
);
906 uint32_t cpu_lduw_be_data(CPUArchState
*env
, abi_ptr ptr
)
908 MemOpIdx oi
= make_memop_idx(MO_BEUW
, MMU_USER_IDX
);
909 uint16_t meminfo
= trace_mem_get_info(oi
, false);
912 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
913 ret
= lduw_be_p(g2h(env_cpu(env
), ptr
));
914 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
918 int cpu_ldsw_be_data(CPUArchState
*env
, abi_ptr ptr
)
920 return (int16_t)cpu_lduw_be_data(env
, ptr
);
923 uint32_t cpu_ldl_be_data(CPUArchState
*env
, abi_ptr ptr
)
925 MemOpIdx oi
= make_memop_idx(MO_BEUL
, MMU_USER_IDX
);
926 uint16_t meminfo
= trace_mem_get_info(oi
, false);
929 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
930 ret
= ldl_be_p(g2h(env_cpu(env
), ptr
));
931 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
935 uint64_t cpu_ldq_be_data(CPUArchState
*env
, abi_ptr ptr
)
937 MemOpIdx oi
= make_memop_idx(MO_BEQ
, MMU_USER_IDX
);
938 uint16_t meminfo
= trace_mem_get_info(oi
, false);
941 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
942 ret
= ldq_be_p(g2h(env_cpu(env
), ptr
));
943 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
947 uint32_t cpu_lduw_le_data(CPUArchState
*env
, abi_ptr ptr
)
949 MemOpIdx oi
= make_memop_idx(MO_LEUW
, MMU_USER_IDX
);
950 uint16_t meminfo
= trace_mem_get_info(oi
, false);
953 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
954 ret
= lduw_le_p(g2h(env_cpu(env
), ptr
));
955 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
959 int cpu_ldsw_le_data(CPUArchState
*env
, abi_ptr ptr
)
961 return (int16_t)cpu_lduw_le_data(env
, ptr
);
964 uint32_t cpu_ldl_le_data(CPUArchState
*env
, abi_ptr ptr
)
966 MemOpIdx oi
= make_memop_idx(MO_LEUL
, MMU_USER_IDX
);
967 uint16_t meminfo
= trace_mem_get_info(oi
, false);
970 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
971 ret
= ldl_le_p(g2h(env_cpu(env
), ptr
));
972 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
976 uint64_t cpu_ldq_le_data(CPUArchState
*env
, abi_ptr ptr
)
978 MemOpIdx oi
= make_memop_idx(MO_LEQ
, MMU_USER_IDX
);
979 uint16_t meminfo
= trace_mem_get_info(oi
, false);
982 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
983 ret
= ldq_le_p(g2h(env_cpu(env
), ptr
));
984 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
988 uint32_t cpu_ldub_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
992 set_helper_retaddr(retaddr
);
993 ret
= cpu_ldub_data(env
, ptr
);
994 clear_helper_retaddr();
998 int cpu_ldsb_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1000 return (int8_t)cpu_ldub_data_ra(env
, ptr
, retaddr
);
1003 uint32_t cpu_lduw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1007 set_helper_retaddr(retaddr
);
1008 ret
= cpu_lduw_be_data(env
, ptr
);
1009 clear_helper_retaddr();
1013 int cpu_ldsw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1015 return (int16_t)cpu_lduw_be_data_ra(env
, ptr
, retaddr
);
1018 uint32_t cpu_ldl_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1022 set_helper_retaddr(retaddr
);
1023 ret
= cpu_ldl_be_data(env
, ptr
);
1024 clear_helper_retaddr();
1028 uint64_t cpu_ldq_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1032 set_helper_retaddr(retaddr
);
1033 ret
= cpu_ldq_be_data(env
, ptr
);
1034 clear_helper_retaddr();
1038 uint32_t cpu_lduw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1042 set_helper_retaddr(retaddr
);
1043 ret
= cpu_lduw_le_data(env
, ptr
);
1044 clear_helper_retaddr();
1048 int cpu_ldsw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1050 return (int16_t)cpu_lduw_le_data_ra(env
, ptr
, retaddr
);
1053 uint32_t cpu_ldl_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1057 set_helper_retaddr(retaddr
);
1058 ret
= cpu_ldl_le_data(env
, ptr
);
1059 clear_helper_retaddr();
1063 uint64_t cpu_ldq_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1067 set_helper_retaddr(retaddr
);
1068 ret
= cpu_ldq_le_data(env
, ptr
);
1069 clear_helper_retaddr();
1073 void cpu_stb_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1075 MemOpIdx oi
= make_memop_idx(MO_UB
, MMU_USER_IDX
);
1076 uint16_t meminfo
= trace_mem_get_info(oi
, true);
1078 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1079 stb_p(g2h(env_cpu(env
), ptr
), val
);
1080 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1083 void cpu_stw_be_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1085 MemOpIdx oi
= make_memop_idx(MO_BEUW
, MMU_USER_IDX
);
1086 uint16_t meminfo
= trace_mem_get_info(oi
, true);
1088 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1089 stw_be_p(g2h(env_cpu(env
), ptr
), val
);
1090 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1093 void cpu_stl_be_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1095 MemOpIdx oi
= make_memop_idx(MO_BEUL
, MMU_USER_IDX
);
1096 uint16_t meminfo
= trace_mem_get_info(oi
, true);
1098 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1099 stl_be_p(g2h(env_cpu(env
), ptr
), val
);
1100 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1103 void cpu_stq_be_data(CPUArchState
*env
, abi_ptr ptr
, uint64_t val
)
1105 MemOpIdx oi
= make_memop_idx(MO_BEQ
, MMU_USER_IDX
);
1106 uint16_t meminfo
= trace_mem_get_info(oi
, true);
1108 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1109 stq_be_p(g2h(env_cpu(env
), ptr
), val
);
1110 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1113 void cpu_stw_le_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1115 MemOpIdx oi
= make_memop_idx(MO_LEUW
, MMU_USER_IDX
);
1116 uint16_t meminfo
= trace_mem_get_info(oi
, true);
1118 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1119 stw_le_p(g2h(env_cpu(env
), ptr
), val
);
1120 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1123 void cpu_stl_le_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1125 MemOpIdx oi
= make_memop_idx(MO_LEUL
, MMU_USER_IDX
);
1126 uint16_t meminfo
= trace_mem_get_info(oi
, true);
1128 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1129 stl_le_p(g2h(env_cpu(env
), ptr
), val
);
1130 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1133 void cpu_stq_le_data(CPUArchState
*env
, abi_ptr ptr
, uint64_t val
)
1135 MemOpIdx oi
= make_memop_idx(MO_LEQ
, MMU_USER_IDX
);
1136 uint16_t meminfo
= trace_mem_get_info(oi
, true);
1138 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1139 stq_le_p(g2h(env_cpu(env
), ptr
), val
);
1140 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1143 void cpu_stb_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1144 uint32_t val
, uintptr_t retaddr
)
1146 set_helper_retaddr(retaddr
);
1147 cpu_stb_data(env
, ptr
, val
);
1148 clear_helper_retaddr();
1151 void cpu_stw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1152 uint32_t val
, uintptr_t retaddr
)
1154 set_helper_retaddr(retaddr
);
1155 cpu_stw_be_data(env
, ptr
, val
);
1156 clear_helper_retaddr();
1159 void cpu_stl_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1160 uint32_t val
, uintptr_t retaddr
)
1162 set_helper_retaddr(retaddr
);
1163 cpu_stl_be_data(env
, ptr
, val
);
1164 clear_helper_retaddr();
1167 void cpu_stq_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1168 uint64_t val
, uintptr_t retaddr
)
1170 set_helper_retaddr(retaddr
);
1171 cpu_stq_be_data(env
, ptr
, val
);
1172 clear_helper_retaddr();
1175 void cpu_stw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1176 uint32_t val
, uintptr_t retaddr
)
1178 set_helper_retaddr(retaddr
);
1179 cpu_stw_le_data(env
, ptr
, val
);
1180 clear_helper_retaddr();
1183 void cpu_stl_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1184 uint32_t val
, uintptr_t retaddr
)
1186 set_helper_retaddr(retaddr
);
1187 cpu_stl_le_data(env
, ptr
, val
);
1188 clear_helper_retaddr();
1191 void cpu_stq_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1192 uint64_t val
, uintptr_t retaddr
)
1194 set_helper_retaddr(retaddr
);
1195 cpu_stq_le_data(env
, ptr
, val
);
1196 clear_helper_retaddr();
1199 uint32_t cpu_ldub_code(CPUArchState
*env
, abi_ptr ptr
)
1203 set_helper_retaddr(1);
1204 ret
= ldub_p(g2h_untagged(ptr
));
1205 clear_helper_retaddr();
1209 uint32_t cpu_lduw_code(CPUArchState
*env
, abi_ptr ptr
)
1213 set_helper_retaddr(1);
1214 ret
= lduw_p(g2h_untagged(ptr
));
1215 clear_helper_retaddr();
1219 uint32_t cpu_ldl_code(CPUArchState
*env
, abi_ptr ptr
)
1223 set_helper_retaddr(1);
1224 ret
= ldl_p(g2h_untagged(ptr
));
1225 clear_helper_retaddr();
1229 uint64_t cpu_ldq_code(CPUArchState
*env
, abi_ptr ptr
)
1233 set_helper_retaddr(1);
1234 ret
= ldq_p(g2h_untagged(ptr
));
1235 clear_helper_retaddr();
1240 * Do not allow unaligned operations to proceed. Return the host address.
1242 * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
1244 static void *atomic_mmu_lookup(CPUArchState
*env
, target_ulong addr
,
1245 MemOpIdx oi
, int size
, int prot
,
1248 /* Enforce qemu required alignment. */
1249 if (unlikely(addr
& (size
- 1))) {
1250 cpu_loop_exit_atomic(env_cpu(env
), retaddr
);
1252 void *ret
= g2h(env_cpu(env
), addr
);
1253 set_helper_retaddr(retaddr
);
1257 #include "atomic_common.c.inc"
1260 * First set of functions passes in OI and RETADDR.
1261 * This makes them callable from other helpers.
1264 #define ATOMIC_NAME(X) \
1265 glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
1266 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
1267 #define ATOMIC_MMU_IDX MMU_USER_IDX
1270 #include "atomic_template.h"
1273 #include "atomic_template.h"
1276 #include "atomic_template.h"
1278 #ifdef CONFIG_ATOMIC64
1280 #include "atomic_template.h"
1283 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128
1284 #define DATA_SIZE 16
1285 #include "atomic_template.h"