4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
24 #include "qemu/cutils.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "qemu/timer.h"
39 #include "qemu/config-file.h"
40 #include "qemu/error-report.h"
41 #include "qemu/qemu-print.h"
42 #if defined(CONFIG_USER_ONLY)
44 #else /* !CONFIG_USER_ONLY */
45 #include "exec/memory.h"
46 #include "exec/ioport.h"
47 #include "sysemu/dma.h"
48 #include "sysemu/hostmem.h"
49 #include "sysemu/hw_accel.h"
50 #include "exec/address-spaces.h"
51 #include "sysemu/xen-mapcache.h"
52 #include "trace-root.h"
54 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
55 #include <linux/falloc.h>
59 #include "qemu/rcu_queue.h"
60 #include "qemu/main-loop.h"
61 #include "translate-all.h"
62 #include "sysemu/replay.h"
64 #include "exec/memory-internal.h"
65 #include "exec/ram_addr.h"
68 #include "migration/vmstate.h"
70 #include "qemu/range.h"
72 #include "qemu/mmap-alloc.h"
75 #include "monitor/monitor.h"
77 //#define DEBUG_SUBPAGE
79 #if !defined(CONFIG_USER_ONLY)
80 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
81 * are protected by the ramlist lock.
83 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
85 static MemoryRegion
*system_memory
;
86 static MemoryRegion
*system_io
;
88 AddressSpace address_space_io
;
89 AddressSpace address_space_memory
;
91 MemoryRegion io_mem_rom
, io_mem_notdirty
;
92 static MemoryRegion io_mem_unassigned
;
95 #ifdef TARGET_PAGE_BITS_VARY
97 bool target_page_bits_decided
;
100 CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
102 /* current CPU in the current thread. It is only valid inside
104 __thread CPUState
*current_cpu
;
105 /* 0 = Do not count executed instructions.
106 1 = Precise instruction counting.
107 2 = Adaptive rate instruction counting. */
110 uintptr_t qemu_host_page_size
;
111 intptr_t qemu_host_page_mask
;
113 bool set_preferred_target_page_bits(int bits
)
115 /* The target page size is the lowest common denominator for all
116 * the CPUs in the system, so we can only make it smaller, never
117 * larger. And we can't make it smaller once we've committed to
120 #ifdef TARGET_PAGE_BITS_VARY
121 assert(bits
>= TARGET_PAGE_BITS_MIN
);
122 if (target_page_bits
== 0 || target_page_bits
> bits
) {
123 if (target_page_bits_decided
) {
126 target_page_bits
= bits
;
132 #if !defined(CONFIG_USER_ONLY)
134 static void finalize_target_page_bits(void)
136 #ifdef TARGET_PAGE_BITS_VARY
137 if (target_page_bits
== 0) {
138 target_page_bits
= TARGET_PAGE_BITS_MIN
;
140 target_page_bits_decided
= true;
144 typedef struct PhysPageEntry PhysPageEntry
;
146 struct PhysPageEntry
{
147 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
149 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
153 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
155 /* Size of the L2 (and L3, etc) page tables. */
156 #define ADDR_SPACE_BITS 64
159 #define P_L2_SIZE (1 << P_L2_BITS)
161 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
163 typedef PhysPageEntry Node
[P_L2_SIZE
];
165 typedef struct PhysPageMap
{
168 unsigned sections_nb
;
169 unsigned sections_nb_alloc
;
171 unsigned nodes_nb_alloc
;
173 MemoryRegionSection
*sections
;
176 struct AddressSpaceDispatch
{
177 MemoryRegionSection
*mru_section
;
178 /* This is a multi-level map on the physical address space.
179 * The bottom level has pointers to MemoryRegionSections.
181 PhysPageEntry phys_map
;
185 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
186 typedef struct subpage_t
{
190 uint16_t sub_section
[];
193 #define PHYS_SECTION_UNASSIGNED 0
194 #define PHYS_SECTION_NOTDIRTY 1
195 #define PHYS_SECTION_ROM 2
196 #define PHYS_SECTION_WATCH 3
198 static void io_mem_init(void);
199 static void memory_map_init(void);
200 static void tcg_log_global_after_sync(MemoryListener
*listener
);
201 static void tcg_commit(MemoryListener
*listener
);
203 static MemoryRegion io_mem_watch
;
206 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
207 * @cpu: the CPU whose AddressSpace this is
208 * @as: the AddressSpace itself
209 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
210 * @tcg_as_listener: listener for tracking changes to the AddressSpace
212 struct CPUAddressSpace
{
215 struct AddressSpaceDispatch
*memory_dispatch
;
216 MemoryListener tcg_as_listener
;
219 struct DirtyBitmapSnapshot
{
222 unsigned long dirty
[];
227 #if !defined(CONFIG_USER_ONLY)
229 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
231 static unsigned alloc_hint
= 16;
232 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
233 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
234 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
235 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
236 alloc_hint
= map
->nodes_nb_alloc
;
240 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
247 ret
= map
->nodes_nb
++;
249 assert(ret
!= PHYS_MAP_NODE_NIL
);
250 assert(ret
!= map
->nodes_nb_alloc
);
252 e
.skip
= leaf
? 0 : 1;
253 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
254 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
255 memcpy(&p
[i
], &e
, sizeof(e
));
260 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
261 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
265 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
267 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
268 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
270 p
= map
->nodes
[lp
->ptr
];
271 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
273 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
274 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
280 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
286 static void phys_page_set(AddressSpaceDispatch
*d
,
287 hwaddr index
, hwaddr nb
,
290 /* Wildly overreserve - it doesn't matter much. */
291 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
293 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
296 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
297 * and update our entry so we can skip it and go directly to the destination.
299 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
301 unsigned valid_ptr
= P_L2_SIZE
;
306 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
311 for (i
= 0; i
< P_L2_SIZE
; i
++) {
312 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
319 phys_page_compact(&p
[i
], nodes
);
323 /* We can only compress if there's only one child. */
328 assert(valid_ptr
< P_L2_SIZE
);
330 /* Don't compress if it won't fit in the # of bits we have. */
331 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
335 lp
->ptr
= p
[valid_ptr
].ptr
;
336 if (!p
[valid_ptr
].skip
) {
337 /* If our only child is a leaf, make this a leaf. */
338 /* By design, we should have made this node a leaf to begin with so we
339 * should never reach here.
340 * But since it's so simple to handle this, let's do it just in case we
345 lp
->skip
+= p
[valid_ptr
].skip
;
349 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
351 if (d
->phys_map
.skip
) {
352 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
356 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
359 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
360 * the section must cover the entire address space.
362 return int128_gethi(section
->size
) ||
363 range_covers_byte(section
->offset_within_address_space
,
364 int128_getlo(section
->size
), addr
);
367 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
369 PhysPageEntry lp
= d
->phys_map
, *p
;
370 Node
*nodes
= d
->map
.nodes
;
371 MemoryRegionSection
*sections
= d
->map
.sections
;
372 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
375 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
376 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
377 return §ions
[PHYS_SECTION_UNASSIGNED
];
380 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
383 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
384 return §ions
[lp
.ptr
];
386 return §ions
[PHYS_SECTION_UNASSIGNED
];
390 /* Called from RCU critical section */
391 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
393 bool resolve_subpage
)
395 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
398 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
399 !section_covers_addr(section
, addr
)) {
400 section
= phys_page_find(d
, addr
);
401 atomic_set(&d
->mru_section
, section
);
403 if (resolve_subpage
&& section
->mr
->subpage
) {
404 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
405 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
410 /* Called from RCU critical section */
411 static MemoryRegionSection
*
412 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
413 hwaddr
*plen
, bool resolve_subpage
)
415 MemoryRegionSection
*section
;
419 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
420 /* Compute offset within MemoryRegionSection */
421 addr
-= section
->offset_within_address_space
;
423 /* Compute offset within MemoryRegion */
424 *xlat
= addr
+ section
->offset_within_region
;
428 /* MMIO registers can be expected to perform full-width accesses based only
429 * on their address, without considering adjacent registers that could
430 * decode to completely different MemoryRegions. When such registers
431 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
432 * regions overlap wildly. For this reason we cannot clamp the accesses
435 * If the length is small (as is the case for address_space_ldl/stl),
436 * everything works fine. If the incoming length is large, however,
437 * the caller really has to do the clamping through memory_access_size.
439 if (memory_region_is_ram(mr
)) {
440 diff
= int128_sub(section
->size
, int128_make64(addr
));
441 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
447 * address_space_translate_iommu - translate an address through an IOMMU
448 * memory region and then through the target address space.
450 * @iommu_mr: the IOMMU memory region that we start the translation from
451 * @addr: the address to be translated through the MMU
452 * @xlat: the translated address offset within the destination memory region.
453 * It cannot be %NULL.
454 * @plen_out: valid read/write length of the translated address. It
456 * @page_mask_out: page mask for the translated address. This
457 * should only be meaningful for IOMMU translated
458 * addresses, since there may be huge pages that this bit
459 * would tell. It can be %NULL if we don't care about it.
460 * @is_write: whether the translation operation is for write
461 * @is_mmio: whether this can be MMIO, set true if it can
462 * @target_as: the address space targeted by the IOMMU
463 * @attrs: transaction attributes
465 * This function is called from RCU critical section. It is the common
466 * part of flatview_do_translate and address_space_translate_cached.
468 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
471 hwaddr
*page_mask_out
,
474 AddressSpace
**target_as
,
477 MemoryRegionSection
*section
;
478 hwaddr page_mask
= (hwaddr
)-1;
482 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
486 if (imrc
->attrs_to_index
) {
487 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
490 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
491 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
493 if (!(iotlb
.perm
& (1 << is_write
))) {
497 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
498 | (addr
& iotlb
.addr_mask
));
499 page_mask
&= iotlb
.addr_mask
;
500 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
501 *target_as
= iotlb
.target_as
;
503 section
= address_space_translate_internal(
504 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
507 iommu_mr
= memory_region_get_iommu(section
->mr
);
508 } while (unlikely(iommu_mr
));
511 *page_mask_out
= page_mask
;
516 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
520 * flatview_do_translate - translate an address in FlatView
522 * @fv: the flat view that we want to translate on
523 * @addr: the address to be translated in above address space
524 * @xlat: the translated address offset within memory region. It
526 * @plen_out: valid read/write length of the translated address. It
527 * can be @NULL when we don't care about it.
528 * @page_mask_out: page mask for the translated address. This
529 * should only be meaningful for IOMMU translated
530 * addresses, since there may be huge pages that this bit
531 * would tell. It can be @NULL if we don't care about it.
532 * @is_write: whether the translation operation is for write
533 * @is_mmio: whether this can be MMIO, set true if it can
534 * @target_as: the address space targeted by the IOMMU
535 * @attrs: memory transaction attributes
537 * This function is called from RCU critical section
539 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
543 hwaddr
*page_mask_out
,
546 AddressSpace
**target_as
,
549 MemoryRegionSection
*section
;
550 IOMMUMemoryRegion
*iommu_mr
;
551 hwaddr plen
= (hwaddr
)(-1);
557 section
= address_space_translate_internal(
558 flatview_to_dispatch(fv
), addr
, xlat
,
561 iommu_mr
= memory_region_get_iommu(section
->mr
);
562 if (unlikely(iommu_mr
)) {
563 return address_space_translate_iommu(iommu_mr
, xlat
,
564 plen_out
, page_mask_out
,
569 /* Not behind an IOMMU, use default page size. */
570 *page_mask_out
= ~TARGET_PAGE_MASK
;
576 /* Called from RCU critical section */
577 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
578 bool is_write
, MemTxAttrs attrs
)
580 MemoryRegionSection section
;
581 hwaddr xlat
, page_mask
;
584 * This can never be MMIO, and we don't really care about plen,
587 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
588 NULL
, &page_mask
, is_write
, false, &as
,
591 /* Illegal translation */
592 if (section
.mr
== &io_mem_unassigned
) {
596 /* Convert memory region offset into address space offset */
597 xlat
+= section
.offset_within_address_space
-
598 section
.offset_within_region
;
600 return (IOMMUTLBEntry
) {
602 .iova
= addr
& ~page_mask
,
603 .translated_addr
= xlat
& ~page_mask
,
604 .addr_mask
= page_mask
,
605 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
610 return (IOMMUTLBEntry
) {0};
613 /* Called from RCU critical section */
614 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
615 hwaddr
*plen
, bool is_write
,
619 MemoryRegionSection section
;
620 AddressSpace
*as
= NULL
;
622 /* This can be MMIO, so setup MMIO bit. */
623 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
624 is_write
, true, &as
, attrs
);
627 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
628 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
629 *plen
= MIN(page
, *plen
);
635 typedef struct TCGIOMMUNotifier
{
643 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
645 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
647 if (!notifier
->active
) {
650 tlb_flush(notifier
->cpu
);
651 notifier
->active
= false;
652 /* We leave the notifier struct on the list to avoid reallocating it later.
653 * Generally the number of IOMMUs a CPU deals with will be small.
654 * In any case we can't unregister the iommu notifier from a notify
659 static void tcg_register_iommu_notifier(CPUState
*cpu
,
660 IOMMUMemoryRegion
*iommu_mr
,
663 /* Make sure this CPU has an IOMMU notifier registered for this
664 * IOMMU/IOMMU index combination, so that we can flush its TLB
665 * when the IOMMU tells us the mappings we've cached have changed.
667 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
668 TCGIOMMUNotifier
*notifier
;
671 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
672 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
673 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
677 if (i
== cpu
->iommu_notifiers
->len
) {
678 /* Not found, add a new entry at the end of the array */
679 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
680 notifier
= g_new0(TCGIOMMUNotifier
, 1);
681 g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
) = notifier
;
684 notifier
->iommu_idx
= iommu_idx
;
686 /* Rather than trying to register interest in the specific part
687 * of the iommu's address space that we've accessed and then
688 * expand it later as subsequent accesses touch more of it, we
689 * just register interest in the whole thing, on the assumption
690 * that iommu reconfiguration will be rare.
692 iommu_notifier_init(¬ifier
->n
,
693 tcg_iommu_unmap_notify
,
694 IOMMU_NOTIFIER_UNMAP
,
698 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
701 if (!notifier
->active
) {
702 notifier
->active
= true;
706 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
708 /* Destroy the CPU's notifier list */
710 TCGIOMMUNotifier
*notifier
;
712 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
713 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
714 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
717 g_array_free(cpu
->iommu_notifiers
, true);
720 /* Called from RCU critical section */
721 MemoryRegionSection
*
722 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
723 hwaddr
*xlat
, hwaddr
*plen
,
724 MemTxAttrs attrs
, int *prot
)
726 MemoryRegionSection
*section
;
727 IOMMUMemoryRegion
*iommu_mr
;
728 IOMMUMemoryRegionClass
*imrc
;
731 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
734 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
736 iommu_mr
= memory_region_get_iommu(section
->mr
);
741 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
743 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
744 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
745 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
746 * doesn't short-cut its translation table walk.
748 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
749 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
750 | (addr
& iotlb
.addr_mask
));
751 /* Update the caller's prot bits to remove permissions the IOMMU
752 * is giving us a failure response for. If we get down to no
753 * permissions left at all we can give up now.
755 if (!(iotlb
.perm
& IOMMU_RO
)) {
756 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
758 if (!(iotlb
.perm
& IOMMU_WO
)) {
759 *prot
&= ~PAGE_WRITE
;
766 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
769 assert(!memory_region_is_iommu(section
->mr
));
774 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
778 #if !defined(CONFIG_USER_ONLY)
780 static int cpu_common_post_load(void *opaque
, int version_id
)
782 CPUState
*cpu
= opaque
;
784 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
785 version_id is increased. */
786 cpu
->interrupt_request
&= ~0x01;
789 /* loadvm has just updated the content of RAM, bypassing the
790 * usual mechanisms that ensure we flush TBs for writes to
791 * memory we've translated code from. So we must flush all TBs,
792 * which will now be stale.
799 static int cpu_common_pre_load(void *opaque
)
801 CPUState
*cpu
= opaque
;
803 cpu
->exception_index
= -1;
808 static bool cpu_common_exception_index_needed(void *opaque
)
810 CPUState
*cpu
= opaque
;
812 return tcg_enabled() && cpu
->exception_index
!= -1;
815 static const VMStateDescription vmstate_cpu_common_exception_index
= {
816 .name
= "cpu_common/exception_index",
818 .minimum_version_id
= 1,
819 .needed
= cpu_common_exception_index_needed
,
820 .fields
= (VMStateField
[]) {
821 VMSTATE_INT32(exception_index
, CPUState
),
822 VMSTATE_END_OF_LIST()
826 static bool cpu_common_crash_occurred_needed(void *opaque
)
828 CPUState
*cpu
= opaque
;
830 return cpu
->crash_occurred
;
833 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
834 .name
= "cpu_common/crash_occurred",
836 .minimum_version_id
= 1,
837 .needed
= cpu_common_crash_occurred_needed
,
838 .fields
= (VMStateField
[]) {
839 VMSTATE_BOOL(crash_occurred
, CPUState
),
840 VMSTATE_END_OF_LIST()
844 const VMStateDescription vmstate_cpu_common
= {
845 .name
= "cpu_common",
847 .minimum_version_id
= 1,
848 .pre_load
= cpu_common_pre_load
,
849 .post_load
= cpu_common_post_load
,
850 .fields
= (VMStateField
[]) {
851 VMSTATE_UINT32(halted
, CPUState
),
852 VMSTATE_UINT32(interrupt_request
, CPUState
),
853 VMSTATE_END_OF_LIST()
855 .subsections
= (const VMStateDescription
*[]) {
856 &vmstate_cpu_common_exception_index
,
857 &vmstate_cpu_common_crash_occurred
,
864 CPUState
*qemu_get_cpu(int index
)
869 if (cpu
->cpu_index
== index
) {
877 #if !defined(CONFIG_USER_ONLY)
878 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
879 const char *prefix
, MemoryRegion
*mr
)
881 CPUAddressSpace
*newas
;
882 AddressSpace
*as
= g_new0(AddressSpace
, 1);
886 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
887 address_space_init(as
, mr
, as_name
);
890 /* Target code should have set num_ases before calling us */
891 assert(asidx
< cpu
->num_ases
);
894 /* address space 0 gets the convenience alias */
898 /* KVM cannot currently support multiple address spaces. */
899 assert(asidx
== 0 || !kvm_enabled());
901 if (!cpu
->cpu_ases
) {
902 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
905 newas
= &cpu
->cpu_ases
[asidx
];
909 newas
->tcg_as_listener
.log_global_after_sync
= tcg_log_global_after_sync
;
910 newas
->tcg_as_listener
.commit
= tcg_commit
;
911 memory_listener_register(&newas
->tcg_as_listener
, as
);
915 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
917 /* Return the AddressSpace corresponding to the specified index */
918 return cpu
->cpu_ases
[asidx
].as
;
922 void cpu_exec_unrealizefn(CPUState
*cpu
)
924 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
926 cpu_list_remove(cpu
);
928 if (cc
->vmsd
!= NULL
) {
929 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
931 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
932 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
934 #ifndef CONFIG_USER_ONLY
935 tcg_iommu_free_notifier_list(cpu
);
939 Property cpu_common_props
[] = {
940 #ifndef CONFIG_USER_ONLY
941 /* Create a memory property for softmmu CPU object,
942 * so users can wire up its memory. (This can't go in hw/core/cpu.c
943 * because that file is compiled only once for both user-mode
944 * and system builds.) The default if no link is set up is to use
945 * the system address space.
947 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
950 DEFINE_PROP_END_OF_LIST(),
953 void cpu_exec_initfn(CPUState
*cpu
)
958 #ifndef CONFIG_USER_ONLY
959 cpu
->thread_id
= qemu_get_thread_id();
960 cpu
->memory
= system_memory
;
961 object_ref(OBJECT(cpu
->memory
));
965 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
967 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
968 static bool tcg_target_initialized
;
972 if (tcg_enabled() && !tcg_target_initialized
) {
973 tcg_target_initialized
= true;
974 cc
->tcg_initialize();
978 #ifndef CONFIG_USER_ONLY
979 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
980 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
982 if (cc
->vmsd
!= NULL
) {
983 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
986 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
*));
990 const char *parse_cpu_option(const char *cpu_option
)
994 gchar
**model_pieces
;
995 const char *cpu_type
;
997 model_pieces
= g_strsplit(cpu_option
, ",", 2);
998 if (!model_pieces
[0]) {
999 error_report("-cpu option cannot be empty");
1003 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
1005 error_report("unable to find CPU model '%s'", model_pieces
[0]);
1006 g_strfreev(model_pieces
);
1010 cpu_type
= object_class_get_name(oc
);
1012 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1013 g_strfreev(model_pieces
);
1017 #if defined(CONFIG_USER_ONLY)
1018 void tb_invalidate_phys_addr(target_ulong addr
)
1021 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1025 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1027 tb_invalidate_phys_addr(pc
);
1030 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1032 ram_addr_t ram_addr
;
1036 if (!tcg_enabled()) {
1041 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1042 if (!(memory_region_is_ram(mr
)
1043 || memory_region_is_romd(mr
))) {
1047 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1048 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1052 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1055 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1056 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1058 /* Locks grabbed by tb_invalidate_phys_addr */
1059 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1060 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1065 #ifndef CONFIG_USER_ONLY
1066 /* Add a watchpoint. */
1067 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1068 int flags
, CPUWatchpoint
**watchpoint
)
1072 /* forbid ranges which are empty or run off the end of the address space */
1073 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1074 error_report("tried to set invalid watchpoint at %"
1075 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1078 wp
= g_malloc(sizeof(*wp
));
1084 /* keep all GDB-injected watchpoints in front */
1085 if (flags
& BP_GDB
) {
1086 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1088 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1091 tlb_flush_page(cpu
, addr
);
1098 /* Remove a specific watchpoint. */
1099 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1104 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1105 if (addr
== wp
->vaddr
&& len
== wp
->len
1106 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1107 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1114 /* Remove a specific watchpoint by reference. */
1115 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1117 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1119 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1124 /* Remove all matching watchpoints. */
1125 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1127 CPUWatchpoint
*wp
, *next
;
1129 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1130 if (wp
->flags
& mask
) {
1131 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1136 /* Return true if this watchpoint address matches the specified
1137 * access (ie the address range covered by the watchpoint overlaps
1138 * partially or completely with the address range covered by the
1141 static inline bool watchpoint_address_matches(CPUWatchpoint
*wp
,
1142 vaddr addr
, vaddr len
)
1144 /* We know the lengths are non-zero, but a little caution is
1145 * required to avoid errors in the case where the range ends
1146 * exactly at the top of the address space and so addr + len
1147 * wraps round to zero.
1149 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1150 vaddr addrend
= addr
+ len
- 1;
1152 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1155 /* Return flags for watchpoints that match addr + prot. */
1156 int cpu_watchpoint_address_matches(CPUState
*cpu
, vaddr addr
, vaddr len
)
1161 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1162 if (watchpoint_address_matches(wp
, addr
, TARGET_PAGE_SIZE
)) {
1168 #endif /* !CONFIG_USER_ONLY */
1170 /* Add a breakpoint. */
1171 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1172 CPUBreakpoint
**breakpoint
)
1176 bp
= g_malloc(sizeof(*bp
));
1181 /* keep all GDB-injected breakpoints in front */
1182 if (flags
& BP_GDB
) {
1183 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1185 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1188 breakpoint_invalidate(cpu
, pc
);
1196 /* Remove a specific breakpoint. */
1197 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1201 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1202 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1203 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1210 /* Remove a specific breakpoint by reference. */
1211 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1213 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1215 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1220 /* Remove all matching breakpoints. */
1221 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1223 CPUBreakpoint
*bp
, *next
;
1225 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1226 if (bp
->flags
& mask
) {
1227 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1232 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1233 CPU loop after each instruction */
1234 void cpu_single_step(CPUState
*cpu
, int enabled
)
1236 if (cpu
->singlestep_enabled
!= enabled
) {
1237 cpu
->singlestep_enabled
= enabled
;
1238 if (kvm_enabled()) {
1239 kvm_update_guest_debug(cpu
, 0);
1241 /* must flush all the translated code to avoid inconsistencies */
1242 /* XXX: only flush what is necessary */
1248 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1255 fprintf(stderr
, "qemu: fatal: ");
1256 vfprintf(stderr
, fmt
, ap
);
1257 fprintf(stderr
, "\n");
1258 cpu_dump_state(cpu
, stderr
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1259 if (qemu_log_separate()) {
1261 qemu_log("qemu: fatal: ");
1262 qemu_log_vprintf(fmt
, ap2
);
1264 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1272 #if defined(CONFIG_USER_ONLY)
1274 struct sigaction act
;
1275 sigfillset(&act
.sa_mask
);
1276 act
.sa_handler
= SIG_DFL
;
1278 sigaction(SIGABRT
, &act
, NULL
);
1284 #if !defined(CONFIG_USER_ONLY)
1285 /* Called from RCU critical section */
1286 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1290 block
= atomic_rcu_read(&ram_list
.mru_block
);
1291 if (block
&& addr
- block
->offset
< block
->max_length
) {
1294 RAMBLOCK_FOREACH(block
) {
1295 if (addr
- block
->offset
< block
->max_length
) {
1300 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1304 /* It is safe to write mru_block outside the iothread lock. This
1309 * xxx removed from list
1313 * call_rcu(reclaim_ramblock, xxx);
1316 * atomic_rcu_set is not needed here. The block was already published
1317 * when it was placed into the list. Here we're just making an extra
1318 * copy of the pointer.
1320 ram_list
.mru_block
= block
;
1324 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1331 assert(tcg_enabled());
1332 end
= TARGET_PAGE_ALIGN(start
+ length
);
1333 start
&= TARGET_PAGE_MASK
;
1336 block
= qemu_get_ram_block(start
);
1337 assert(block
== qemu_get_ram_block(end
- 1));
1338 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1340 tlb_reset_dirty(cpu
, start1
, length
);
1345 /* Note: start and end must be within the same ram block. */
1346 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1350 DirtyMemoryBlocks
*blocks
;
1351 unsigned long end
, page
;
1354 uint64_t mr_offset
, mr_size
;
1360 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1361 page
= start
>> TARGET_PAGE_BITS
;
1365 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1366 ramblock
= qemu_get_ram_block(start
);
1367 /* Range sanity check on the ramblock */
1368 assert(start
>= ramblock
->offset
&&
1369 start
+ length
<= ramblock
->offset
+ ramblock
->used_length
);
1371 while (page
< end
) {
1372 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1373 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1374 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1376 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1381 mr_offset
= (ram_addr_t
)(page
<< TARGET_PAGE_BITS
) - ramblock
->offset
;
1382 mr_size
= (end
- page
) << TARGET_PAGE_BITS
;
1383 memory_region_clear_dirty_bitmap(ramblock
->mr
, mr_offset
, mr_size
);
1387 if (dirty
&& tcg_enabled()) {
1388 tlb_reset_dirty_range_all(start
, length
);
1394 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1395 (MemoryRegion
*mr
, hwaddr offset
, hwaddr length
, unsigned client
)
1397 DirtyMemoryBlocks
*blocks
;
1398 ram_addr_t start
= memory_region_get_ram_addr(mr
) + offset
;
1399 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1400 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1401 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1402 DirtyBitmapSnapshot
*snap
;
1403 unsigned long page
, end
, dest
;
1405 snap
= g_malloc0(sizeof(*snap
) +
1406 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1407 snap
->start
= first
;
1410 page
= first
>> TARGET_PAGE_BITS
;
1411 end
= last
>> TARGET_PAGE_BITS
;
1416 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1418 while (page
< end
) {
1419 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1420 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1421 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1423 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1424 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1425 offset
>>= BITS_PER_LEVEL
;
1427 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1428 blocks
->blocks
[idx
] + offset
,
1431 dest
+= num
>> BITS_PER_LEVEL
;
1436 if (tcg_enabled()) {
1437 tlb_reset_dirty_range_all(start
, length
);
1440 memory_region_clear_dirty_bitmap(mr
, offset
, length
);
1445 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1449 unsigned long page
, end
;
1451 assert(start
>= snap
->start
);
1452 assert(start
+ length
<= snap
->end
);
1454 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1455 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1457 while (page
< end
) {
1458 if (test_bit(page
, snap
->dirty
)) {
1466 /* Called from RCU critical section */
1467 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1468 MemoryRegionSection
*section
,
1470 hwaddr paddr
, hwaddr xlat
,
1472 target_ulong
*address
)
1477 if (memory_region_is_ram(section
->mr
)) {
1479 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1480 if (!section
->readonly
) {
1481 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1483 iotlb
|= PHYS_SECTION_ROM
;
1486 AddressSpaceDispatch
*d
;
1488 d
= flatview_to_dispatch(section
->fv
);
1489 iotlb
= section
- d
->map
.sections
;
1493 /* Avoid trapping reads of pages with a write breakpoint. */
1494 match
= (prot
& PAGE_READ
? BP_MEM_READ
: 0)
1495 | (prot
& PAGE_WRITE
? BP_MEM_WRITE
: 0);
1496 flags
= cpu_watchpoint_address_matches(cpu
, vaddr
, TARGET_PAGE_SIZE
);
1497 if (flags
& match
) {
1499 * Make accesses to pages with watchpoints go via the
1500 * watchpoint trap routines.
1502 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1503 *address
|= TLB_MMIO
;
1508 #endif /* defined(CONFIG_USER_ONLY) */
1510 #if !defined(CONFIG_USER_ONLY)
1512 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1514 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1516 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1517 qemu_anon_ram_alloc
;
1520 * Set a custom physical guest memory alloator.
1521 * Accelerators with unusual needs may need this. Hopefully, we can
1522 * get rid of it eventually.
1524 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1526 phys_mem_alloc
= alloc
;
1529 static uint16_t phys_section_add(PhysPageMap
*map
,
1530 MemoryRegionSection
*section
)
1532 /* The physical section number is ORed with a page-aligned
1533 * pointer to produce the iotlb entries. Thus it should
1534 * never overflow into the page-aligned value.
1536 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1538 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1539 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1540 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1541 map
->sections_nb_alloc
);
1543 map
->sections
[map
->sections_nb
] = *section
;
1544 memory_region_ref(section
->mr
);
1545 return map
->sections_nb
++;
1548 static void phys_section_destroy(MemoryRegion
*mr
)
1550 bool have_sub_page
= mr
->subpage
;
1552 memory_region_unref(mr
);
1554 if (have_sub_page
) {
1555 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1556 object_unref(OBJECT(&subpage
->iomem
));
1561 static void phys_sections_free(PhysPageMap
*map
)
1563 while (map
->sections_nb
> 0) {
1564 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1565 phys_section_destroy(section
->mr
);
1567 g_free(map
->sections
);
1571 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1573 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1575 hwaddr base
= section
->offset_within_address_space
1577 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1578 MemoryRegionSection subsection
= {
1579 .offset_within_address_space
= base
,
1580 .size
= int128_make64(TARGET_PAGE_SIZE
),
1584 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1586 if (!(existing
->mr
->subpage
)) {
1587 subpage
= subpage_init(fv
, base
);
1589 subsection
.mr
= &subpage
->iomem
;
1590 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1591 phys_section_add(&d
->map
, &subsection
));
1593 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1595 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1596 end
= start
+ int128_get64(section
->size
) - 1;
1597 subpage_register(subpage
, start
, end
,
1598 phys_section_add(&d
->map
, section
));
1602 static void register_multipage(FlatView
*fv
,
1603 MemoryRegionSection
*section
)
1605 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1606 hwaddr start_addr
= section
->offset_within_address_space
;
1607 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1608 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1612 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1616 * The range in *section* may look like this:
1620 * where s stands for subpage and P for page.
1622 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1624 MemoryRegionSection remain
= *section
;
1625 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1627 /* register first subpage */
1628 if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1629 uint64_t left
= TARGET_PAGE_ALIGN(remain
.offset_within_address_space
)
1630 - remain
.offset_within_address_space
;
1632 MemoryRegionSection now
= remain
;
1633 now
.size
= int128_min(int128_make64(left
), now
.size
);
1634 register_subpage(fv
, &now
);
1635 if (int128_eq(remain
.size
, now
.size
)) {
1638 remain
.size
= int128_sub(remain
.size
, now
.size
);
1639 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1640 remain
.offset_within_region
+= int128_get64(now
.size
);
1643 /* register whole pages */
1644 if (int128_ge(remain
.size
, page_size
)) {
1645 MemoryRegionSection now
= remain
;
1646 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1647 register_multipage(fv
, &now
);
1648 if (int128_eq(remain
.size
, now
.size
)) {
1651 remain
.size
= int128_sub(remain
.size
, now
.size
);
1652 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1653 remain
.offset_within_region
+= int128_get64(now
.size
);
1656 /* register last subpage */
1657 register_subpage(fv
, &remain
);
1660 void qemu_flush_coalesced_mmio_buffer(void)
1663 kvm_flush_coalesced_mmio_buffer();
1666 void qemu_mutex_lock_ramlist(void)
1668 qemu_mutex_lock(&ram_list
.mutex
);
1671 void qemu_mutex_unlock_ramlist(void)
1673 qemu_mutex_unlock(&ram_list
.mutex
);
1676 void ram_block_dump(Monitor
*mon
)
1682 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1683 "Block Name", "PSize", "Offset", "Used", "Total");
1684 RAMBLOCK_FOREACH(block
) {
1685 psize
= size_to_str(block
->page_size
);
1686 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1687 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1688 (uint64_t)block
->offset
,
1689 (uint64_t)block
->used_length
,
1690 (uint64_t)block
->max_length
);
1698 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1699 * may or may not name the same files / on the same filesystem now as
1700 * when we actually open and map them. Iterate over the file
1701 * descriptors instead, and use qemu_fd_getpagesize().
1703 static int find_min_backend_pagesize(Object
*obj
, void *opaque
)
1705 long *hpsize_min
= opaque
;
1707 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1708 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1709 long hpsize
= host_memory_backend_pagesize(backend
);
1711 if (host_memory_backend_is_mapped(backend
) && (hpsize
< *hpsize_min
)) {
1712 *hpsize_min
= hpsize
;
1719 static int find_max_backend_pagesize(Object
*obj
, void *opaque
)
1721 long *hpsize_max
= opaque
;
1723 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1724 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1725 long hpsize
= host_memory_backend_pagesize(backend
);
1727 if (host_memory_backend_is_mapped(backend
) && (hpsize
> *hpsize_max
)) {
1728 *hpsize_max
= hpsize
;
1736 * TODO: We assume right now that all mapped host memory backends are
1737 * used as RAM, however some might be used for different purposes.
1739 long qemu_minrampagesize(void)
1741 long hpsize
= LONG_MAX
;
1742 long mainrampagesize
;
1743 Object
*memdev_root
;
1745 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1747 /* it's possible we have memory-backend objects with
1748 * hugepage-backed RAM. these may get mapped into system
1749 * address space via -numa parameters or memory hotplug
1750 * hooks. we want to take these into account, but we
1751 * also want to make sure these supported hugepage
1752 * sizes are applicable across the entire range of memory
1753 * we may boot from, so we take the min across all
1754 * backends, and assume normal pages in cases where a
1755 * backend isn't backed by hugepages.
1757 memdev_root
= object_resolve_path("/objects", NULL
);
1759 object_child_foreach(memdev_root
, find_min_backend_pagesize
, &hpsize
);
1761 if (hpsize
== LONG_MAX
) {
1762 /* No additional memory regions found ==> Report main RAM page size */
1763 return mainrampagesize
;
1766 /* If NUMA is disabled or the NUMA nodes are not backed with a
1767 * memory-backend, then there is at least one node using "normal" RAM,
1768 * so if its page size is smaller we have got to report that size instead.
1770 if (hpsize
> mainrampagesize
&&
1771 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1774 error_report("Huge page support disabled (n/a for main memory).");
1777 return mainrampagesize
;
1783 long qemu_maxrampagesize(void)
1785 long pagesize
= qemu_mempath_getpagesize(mem_path
);
1786 Object
*memdev_root
= object_resolve_path("/objects", NULL
);
1789 object_child_foreach(memdev_root
, find_max_backend_pagesize
,
1795 long qemu_minrampagesize(void)
1797 return getpagesize();
1799 long qemu_maxrampagesize(void)
1801 return getpagesize();
1806 static int64_t get_file_size(int fd
)
1808 int64_t size
= lseek(fd
, 0, SEEK_END
);
1815 static int file_ram_open(const char *path
,
1816 const char *region_name
,
1821 char *sanitized_name
;
1827 fd
= open(path
, O_RDWR
);
1829 /* @path names an existing file, use it */
1832 if (errno
== ENOENT
) {
1833 /* @path names a file that doesn't exist, create it */
1834 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1839 } else if (errno
== EISDIR
) {
1840 /* @path names a directory, create a file there */
1841 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1842 sanitized_name
= g_strdup(region_name
);
1843 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1849 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1851 g_free(sanitized_name
);
1853 fd
= mkstemp(filename
);
1861 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1862 error_setg_errno(errp
, errno
,
1863 "can't open backing store %s for guest RAM",
1868 * Try again on EINTR and EEXIST. The latter happens when
1869 * something else creates the file between our two open().
1876 static void *file_ram_alloc(RAMBlock
*block
,
1882 MachineState
*ms
= MACHINE(qdev_get_machine());
1885 block
->page_size
= qemu_fd_getpagesize(fd
);
1886 if (block
->mr
->align
% block
->page_size
) {
1887 error_setg(errp
, "alignment 0x%" PRIx64
1888 " must be multiples of page size 0x%zx",
1889 block
->mr
->align
, block
->page_size
);
1891 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1892 error_setg(errp
, "alignment 0x%" PRIx64
1893 " must be a power of two", block
->mr
->align
);
1896 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1897 #if defined(__s390x__)
1898 if (kvm_enabled()) {
1899 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1903 if (memory
< block
->page_size
) {
1904 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1905 "or larger than page size 0x%zx",
1906 memory
, block
->page_size
);
1910 memory
= ROUND_UP(memory
, block
->page_size
);
1913 * ftruncate is not supported by hugetlbfs in older
1914 * hosts, so don't bother bailing out on errors.
1915 * If anything goes wrong with it under other filesystems,
1918 * Do not truncate the non-empty backend file to avoid corrupting
1919 * the existing data in the file. Disabling shrinking is not
1920 * enough. For example, the current vNVDIMM implementation stores
1921 * the guest NVDIMM labels at the end of the backend file. If the
1922 * backend file is later extended, QEMU will not be able to find
1923 * those labels. Therefore, extending the non-empty backend file
1924 * is disabled as well.
1926 if (truncate
&& ftruncate(fd
, memory
)) {
1927 perror("ftruncate");
1930 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1931 block
->flags
& RAM_SHARED
, block
->flags
& RAM_PMEM
);
1932 if (area
== MAP_FAILED
) {
1933 error_setg_errno(errp
, errno
,
1934 "unable to map backing store for guest RAM");
1939 os_mem_prealloc(fd
, area
, memory
, ms
->smp
.cpus
, errp
);
1940 if (errp
&& *errp
) {
1941 qemu_ram_munmap(fd
, area
, memory
);
1951 /* Allocate space within the ram_addr_t space that governs the
1953 * Called with the ramlist lock held.
1955 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1957 RAMBlock
*block
, *next_block
;
1958 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1960 assert(size
!= 0); /* it would hand out same offset multiple times */
1962 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1966 RAMBLOCK_FOREACH(block
) {
1967 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1969 /* Align blocks to start on a 'long' in the bitmap
1970 * which makes the bitmap sync'ing take the fast path.
1972 candidate
= block
->offset
+ block
->max_length
;
1973 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1975 /* Search for the closest following block
1978 RAMBLOCK_FOREACH(next_block
) {
1979 if (next_block
->offset
>= candidate
) {
1980 next
= MIN(next
, next_block
->offset
);
1984 /* If it fits remember our place and remember the size
1985 * of gap, but keep going so that we might find a smaller
1986 * gap to fill so avoiding fragmentation.
1988 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1990 mingap
= next
- candidate
;
1993 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1996 if (offset
== RAM_ADDR_MAX
) {
1997 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
2002 trace_find_ram_offset(size
, offset
);
2007 static unsigned long last_ram_page(void)
2010 ram_addr_t last
= 0;
2013 RAMBLOCK_FOREACH(block
) {
2014 last
= MAX(last
, block
->offset
+ block
->max_length
);
2017 return last
>> TARGET_PAGE_BITS
;
2020 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
2024 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
2025 if (!machine_dump_guest_core(current_machine
)) {
2026 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
2028 perror("qemu_madvise");
2029 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
2030 "but dump_guest_core=off specified\n");
2035 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
2040 void *qemu_ram_get_host_addr(RAMBlock
*rb
)
2045 ram_addr_t
qemu_ram_get_offset(RAMBlock
*rb
)
2050 ram_addr_t
qemu_ram_get_used_length(RAMBlock
*rb
)
2052 return rb
->used_length
;
2055 bool qemu_ram_is_shared(RAMBlock
*rb
)
2057 return rb
->flags
& RAM_SHARED
;
2060 /* Note: Only set at the start of postcopy */
2061 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
2063 return rb
->flags
& RAM_UF_ZEROPAGE
;
2066 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
2068 rb
->flags
|= RAM_UF_ZEROPAGE
;
2071 bool qemu_ram_is_migratable(RAMBlock
*rb
)
2073 return rb
->flags
& RAM_MIGRATABLE
;
2076 void qemu_ram_set_migratable(RAMBlock
*rb
)
2078 rb
->flags
|= RAM_MIGRATABLE
;
2081 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2083 rb
->flags
&= ~RAM_MIGRATABLE
;
2086 /* Called with iothread lock held. */
2087 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2092 assert(!new_block
->idstr
[0]);
2095 char *id
= qdev_get_dev_path(dev
);
2097 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2101 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2104 RAMBLOCK_FOREACH(block
) {
2105 if (block
!= new_block
&&
2106 !strcmp(block
->idstr
, new_block
->idstr
)) {
2107 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2115 /* Called with iothread lock held. */
2116 void qemu_ram_unset_idstr(RAMBlock
*block
)
2118 /* FIXME: arch_init.c assumes that this is not called throughout
2119 * migration. Ignore the problem since hot-unplug during migration
2120 * does not work anyway.
2123 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2127 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2129 return rb
->page_size
;
2132 /* Returns the largest size of page in use */
2133 size_t qemu_ram_pagesize_largest(void)
2138 RAMBLOCK_FOREACH(block
) {
2139 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2145 static int memory_try_enable_merging(void *addr
, size_t len
)
2147 if (!machine_mem_merge(current_machine
)) {
2148 /* disabled by the user */
2152 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2155 /* Only legal before guest might have detected the memory size: e.g. on
2156 * incoming migration, or right after reset.
2158 * As memory core doesn't know how is memory accessed, it is up to
2159 * resize callback to update device state and/or add assertions to detect
2160 * misuse, if necessary.
2162 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2166 newsize
= HOST_PAGE_ALIGN(newsize
);
2168 if (block
->used_length
== newsize
) {
2172 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2173 error_setg_errno(errp
, EINVAL
,
2174 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2175 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2176 newsize
, block
->used_length
);
2180 if (block
->max_length
< newsize
) {
2181 error_setg_errno(errp
, EINVAL
,
2182 "Length too large: %s: 0x" RAM_ADDR_FMT
2183 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2184 newsize
, block
->max_length
);
2188 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2189 block
->used_length
= newsize
;
2190 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2192 memory_region_set_size(block
->mr
, newsize
);
2193 if (block
->resized
) {
2194 block
->resized(block
->idstr
, newsize
, block
->host
);
2199 /* Called with ram_list.mutex held */
2200 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2201 ram_addr_t new_ram_size
)
2203 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2204 DIRTY_MEMORY_BLOCK_SIZE
);
2205 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2206 DIRTY_MEMORY_BLOCK_SIZE
);
2209 /* Only need to extend if block count increased */
2210 if (new_num_blocks
<= old_num_blocks
) {
2214 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2215 DirtyMemoryBlocks
*old_blocks
;
2216 DirtyMemoryBlocks
*new_blocks
;
2219 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2220 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2221 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2223 if (old_num_blocks
) {
2224 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2225 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2228 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2229 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2232 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2235 g_free_rcu(old_blocks
, rcu
);
2240 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2243 RAMBlock
*last_block
= NULL
;
2244 ram_addr_t old_ram_size
, new_ram_size
;
2247 old_ram_size
= last_ram_page();
2249 qemu_mutex_lock_ramlist();
2250 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2252 if (!new_block
->host
) {
2253 if (xen_enabled()) {
2254 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2255 new_block
->mr
, &err
);
2257 error_propagate(errp
, err
);
2258 qemu_mutex_unlock_ramlist();
2262 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2263 &new_block
->mr
->align
, shared
);
2264 if (!new_block
->host
) {
2265 error_setg_errno(errp
, errno
,
2266 "cannot set up guest memory '%s'",
2267 memory_region_name(new_block
->mr
));
2268 qemu_mutex_unlock_ramlist();
2271 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2275 new_ram_size
= MAX(old_ram_size
,
2276 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2277 if (new_ram_size
> old_ram_size
) {
2278 dirty_memory_extend(old_ram_size
, new_ram_size
);
2280 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2281 * QLIST (which has an RCU-friendly variant) does not have insertion at
2282 * tail, so save the last element in last_block.
2284 RAMBLOCK_FOREACH(block
) {
2286 if (block
->max_length
< new_block
->max_length
) {
2291 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2292 } else if (last_block
) {
2293 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2294 } else { /* list is empty */
2295 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2297 ram_list
.mru_block
= NULL
;
2299 /* Write list before version */
2302 qemu_mutex_unlock_ramlist();
2304 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2305 new_block
->used_length
,
2308 if (new_block
->host
) {
2309 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2310 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2311 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2312 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2313 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2318 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2319 uint32_t ram_flags
, int fd
,
2322 RAMBlock
*new_block
;
2323 Error
*local_err
= NULL
;
2326 /* Just support these ram flags by now. */
2327 assert((ram_flags
& ~(RAM_SHARED
| RAM_PMEM
)) == 0);
2329 if (xen_enabled()) {
2330 error_setg(errp
, "-mem-path not supported with Xen");
2334 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2336 "host lacks kvm mmu notifiers, -mem-path unsupported");
2340 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2342 * file_ram_alloc() needs to allocate just like
2343 * phys_mem_alloc, but we haven't bothered to provide
2347 "-mem-path not supported with this accelerator");
2351 size
= HOST_PAGE_ALIGN(size
);
2352 file_size
= get_file_size(fd
);
2353 if (file_size
> 0 && file_size
< size
) {
2354 error_setg(errp
, "backing store %s size 0x%" PRIx64
2355 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2356 mem_path
, file_size
, size
);
2360 new_block
= g_malloc0(sizeof(*new_block
));
2362 new_block
->used_length
= size
;
2363 new_block
->max_length
= size
;
2364 new_block
->flags
= ram_flags
;
2365 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2366 if (!new_block
->host
) {
2371 ram_block_add(new_block
, &local_err
, ram_flags
& RAM_SHARED
);
2374 error_propagate(errp
, local_err
);
2382 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2383 uint32_t ram_flags
, const char *mem_path
,
2390 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2395 block
= qemu_ram_alloc_from_fd(size
, mr
, ram_flags
, fd
, errp
);
2409 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2410 void (*resized
)(const char*,
2413 void *host
, bool resizeable
, bool share
,
2414 MemoryRegion
*mr
, Error
**errp
)
2416 RAMBlock
*new_block
;
2417 Error
*local_err
= NULL
;
2419 size
= HOST_PAGE_ALIGN(size
);
2420 max_size
= HOST_PAGE_ALIGN(max_size
);
2421 new_block
= g_malloc0(sizeof(*new_block
));
2423 new_block
->resized
= resized
;
2424 new_block
->used_length
= size
;
2425 new_block
->max_length
= max_size
;
2426 assert(max_size
>= size
);
2428 new_block
->page_size
= getpagesize();
2429 new_block
->host
= host
;
2431 new_block
->flags
|= RAM_PREALLOC
;
2434 new_block
->flags
|= RAM_RESIZEABLE
;
2436 ram_block_add(new_block
, &local_err
, share
);
2439 error_propagate(errp
, local_err
);
2445 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2446 MemoryRegion
*mr
, Error
**errp
)
2448 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2452 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2453 MemoryRegion
*mr
, Error
**errp
)
2455 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2459 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2460 void (*resized
)(const char*,
2463 MemoryRegion
*mr
, Error
**errp
)
2465 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2469 static void reclaim_ramblock(RAMBlock
*block
)
2471 if (block
->flags
& RAM_PREALLOC
) {
2473 } else if (xen_enabled()) {
2474 xen_invalidate_map_cache_entry(block
->host
);
2476 } else if (block
->fd
>= 0) {
2477 qemu_ram_munmap(block
->fd
, block
->host
, block
->max_length
);
2481 qemu_anon_ram_free(block
->host
, block
->max_length
);
2486 void qemu_ram_free(RAMBlock
*block
)
2493 ram_block_notify_remove(block
->host
, block
->max_length
);
2496 qemu_mutex_lock_ramlist();
2497 QLIST_REMOVE_RCU(block
, next
);
2498 ram_list
.mru_block
= NULL
;
2499 /* Write list before version */
2502 call_rcu(block
, reclaim_ramblock
, rcu
);
2503 qemu_mutex_unlock_ramlist();
2507 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2514 RAMBLOCK_FOREACH(block
) {
2515 offset
= addr
- block
->offset
;
2516 if (offset
< block
->max_length
) {
2517 vaddr
= ramblock_ptr(block
, offset
);
2518 if (block
->flags
& RAM_PREALLOC
) {
2520 } else if (xen_enabled()) {
2524 if (block
->fd
>= 0) {
2525 flags
|= (block
->flags
& RAM_SHARED
?
2526 MAP_SHARED
: MAP_PRIVATE
);
2527 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2528 flags
, block
->fd
, offset
);
2531 * Remap needs to match alloc. Accelerators that
2532 * set phys_mem_alloc never remap. If they did,
2533 * we'd need a remap hook here.
2535 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2537 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2538 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2541 if (area
!= vaddr
) {
2542 error_report("Could not remap addr: "
2543 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2547 memory_try_enable_merging(vaddr
, length
);
2548 qemu_ram_setup_dump(vaddr
, length
);
2553 #endif /* !_WIN32 */
2555 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2556 * This should not be used for general purpose DMA. Use address_space_map
2557 * or address_space_rw instead. For local memory (e.g. video ram) that the
2558 * device owns, use memory_region_get_ram_ptr.
2560 * Called within RCU critical section.
2562 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2564 RAMBlock
*block
= ram_block
;
2566 if (block
== NULL
) {
2567 block
= qemu_get_ram_block(addr
);
2568 addr
-= block
->offset
;
2571 if (xen_enabled() && block
->host
== NULL
) {
2572 /* We need to check if the requested address is in the RAM
2573 * because we don't want to map the entire memory in QEMU.
2574 * In that case just map until the end of the page.
2576 if (block
->offset
== 0) {
2577 return xen_map_cache(addr
, 0, 0, false);
2580 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2582 return ramblock_ptr(block
, addr
);
2585 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2586 * but takes a size argument.
2588 * Called within RCU critical section.
2590 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2591 hwaddr
*size
, bool lock
)
2593 RAMBlock
*block
= ram_block
;
2598 if (block
== NULL
) {
2599 block
= qemu_get_ram_block(addr
);
2600 addr
-= block
->offset
;
2602 *size
= MIN(*size
, block
->max_length
- addr
);
2604 if (xen_enabled() && block
->host
== NULL
) {
2605 /* We need to check if the requested address is in the RAM
2606 * because we don't want to map the entire memory in QEMU.
2607 * In that case just map the requested area.
2609 if (block
->offset
== 0) {
2610 return xen_map_cache(addr
, *size
, lock
, lock
);
2613 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2616 return ramblock_ptr(block
, addr
);
2619 /* Return the offset of a hostpointer within a ramblock */
2620 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2622 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2623 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2624 assert(res
< rb
->max_length
);
2630 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2633 * ptr: Host pointer to look up
2634 * round_offset: If true round the result offset down to a page boundary
2635 * *ram_addr: set to result ram_addr
2636 * *offset: set to result offset within the RAMBlock
2638 * Returns: RAMBlock (or NULL if not found)
2640 * By the time this function returns, the returned pointer is not protected
2641 * by RCU anymore. If the caller is not within an RCU critical section and
2642 * does not hold the iothread lock, it must have other means of protecting the
2643 * pointer, such as a reference to the region that includes the incoming
2646 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2650 uint8_t *host
= ptr
;
2652 if (xen_enabled()) {
2653 ram_addr_t ram_addr
;
2655 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2656 block
= qemu_get_ram_block(ram_addr
);
2658 *offset
= ram_addr
- block
->offset
;
2665 block
= atomic_rcu_read(&ram_list
.mru_block
);
2666 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2670 RAMBLOCK_FOREACH(block
) {
2671 /* This case append when the block is not mapped. */
2672 if (block
->host
== NULL
) {
2675 if (host
- block
->host
< block
->max_length
) {
2684 *offset
= (host
- block
->host
);
2686 *offset
&= TARGET_PAGE_MASK
;
2693 * Finds the named RAMBlock
2695 * name: The name of RAMBlock to find
2697 * Returns: RAMBlock (or NULL if not found)
2699 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2703 RAMBLOCK_FOREACH(block
) {
2704 if (!strcmp(name
, block
->idstr
)) {
2712 /* Some of the softmmu routines need to translate from a host pointer
2713 (typically a TLB entry) back to a ram offset. */
2714 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2719 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2721 return RAM_ADDR_INVALID
;
2724 return block
->offset
+ offset
;
2727 /* Called within RCU critical section. */
2728 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2731 ram_addr_t ram_addr
,
2735 ndi
->ram_addr
= ram_addr
;
2736 ndi
->mem_vaddr
= mem_vaddr
;
2740 assert(tcg_enabled());
2741 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2742 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2743 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2747 /* Called within RCU critical section. */
2748 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2751 assert(tcg_enabled());
2752 page_collection_unlock(ndi
->pages
);
2756 /* Set both VGA and migration bits for simplicity and to remove
2757 * the notdirty callback faster.
2759 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2760 DIRTY_CLIENTS_NOCODE
);
2761 /* we remove the notdirty callback only if the code has been
2763 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2764 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2768 /* Called within RCU critical section. */
2769 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2770 uint64_t val
, unsigned size
)
2774 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2777 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2778 memory_notdirty_write_complete(&ndi
);
2781 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2782 unsigned size
, bool is_write
,
2788 static const MemoryRegionOps notdirty_mem_ops
= {
2789 .write
= notdirty_mem_write
,
2790 .valid
.accepts
= notdirty_mem_accepts
,
2791 .endianness
= DEVICE_NATIVE_ENDIAN
,
2793 .min_access_size
= 1,
2794 .max_access_size
= 8,
2798 .min_access_size
= 1,
2799 .max_access_size
= 8,
2804 /* Generate a debug exception if a watchpoint has been hit. */
2805 void cpu_check_watchpoint(CPUState
*cpu
, vaddr addr
, vaddr len
,
2806 MemTxAttrs attrs
, int flags
, uintptr_t ra
)
2808 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2811 assert(tcg_enabled());
2812 if (cpu
->watchpoint_hit
) {
2813 /* We re-entered the check after replacing the TB. Now raise
2814 * the debug interrupt so that is will trigger after the
2815 * current instruction. */
2816 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2820 addr
= cc
->adjust_watchpoint_address(cpu
, addr
, len
);
2821 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2822 if (watchpoint_address_matches(wp
, addr
, len
)
2823 && (wp
->flags
& flags
)) {
2824 if (flags
== BP_MEM_READ
) {
2825 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2827 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2829 wp
->hitaddr
= MAX(addr
, wp
->vaddr
);
2830 wp
->hitattrs
= attrs
;
2831 if (!cpu
->watchpoint_hit
) {
2832 if (wp
->flags
& BP_CPU
&&
2833 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2834 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2837 cpu
->watchpoint_hit
= wp
;
2840 tb_check_watchpoint(cpu
);
2841 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2842 cpu
->exception_index
= EXCP_DEBUG
;
2844 cpu_loop_exit_restore(cpu
, ra
);
2846 /* Force execution of one insn next time. */
2847 cpu
->cflags_next_tb
= 1 | curr_cflags();
2850 cpu_restore_state(cpu
, ra
, true);
2852 cpu_loop_exit_noexc(cpu
);
2856 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2861 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2863 CPUState
*cpu
= current_cpu
;
2864 vaddr addr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2866 cpu_check_watchpoint(cpu
, addr
, len
, attrs
, flags
, 0);
2869 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2870 so these check for a hit then pass through to the normal out-of-line
2872 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2873 unsigned size
, MemTxAttrs attrs
)
2877 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2878 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2880 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2883 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2886 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2889 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2892 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2900 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2901 uint64_t val
, unsigned size
,
2905 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2906 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2908 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2911 address_space_stb(as
, addr
, val
, attrs
, &res
);
2914 address_space_stw(as
, addr
, val
, attrs
, &res
);
2917 address_space_stl(as
, addr
, val
, attrs
, &res
);
2920 address_space_stq(as
, addr
, val
, attrs
, &res
);
2927 static const MemoryRegionOps watch_mem_ops
= {
2928 .read_with_attrs
= watch_mem_read
,
2929 .write_with_attrs
= watch_mem_write
,
2930 .endianness
= DEVICE_NATIVE_ENDIAN
,
2932 .min_access_size
= 1,
2933 .max_access_size
= 8,
2937 .min_access_size
= 1,
2938 .max_access_size
= 8,
2943 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2944 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
);
2945 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2946 const uint8_t *buf
, hwaddr len
);
2947 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
2948 bool is_write
, MemTxAttrs attrs
);
2950 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2951 unsigned len
, MemTxAttrs attrs
)
2953 subpage_t
*subpage
= opaque
;
2957 #if defined(DEBUG_SUBPAGE)
2958 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2959 subpage
, len
, addr
);
2961 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2965 *data
= ldn_p(buf
, len
);
2969 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2970 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2972 subpage_t
*subpage
= opaque
;
2975 #if defined(DEBUG_SUBPAGE)
2976 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2977 " value %"PRIx64
"\n",
2978 __func__
, subpage
, len
, addr
, value
);
2980 stn_p(buf
, len
, value
);
2981 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2984 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2985 unsigned len
, bool is_write
,
2988 subpage_t
*subpage
= opaque
;
2989 #if defined(DEBUG_SUBPAGE)
2990 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2991 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2994 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2995 len
, is_write
, attrs
);
2998 static const MemoryRegionOps subpage_ops
= {
2999 .read_with_attrs
= subpage_read
,
3000 .write_with_attrs
= subpage_write
,
3001 .impl
.min_access_size
= 1,
3002 .impl
.max_access_size
= 8,
3003 .valid
.min_access_size
= 1,
3004 .valid
.max_access_size
= 8,
3005 .valid
.accepts
= subpage_accepts
,
3006 .endianness
= DEVICE_NATIVE_ENDIAN
,
3009 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
3014 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
3016 idx
= SUBPAGE_IDX(start
);
3017 eidx
= SUBPAGE_IDX(end
);
3018 #if defined(DEBUG_SUBPAGE)
3019 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
3020 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
3022 for (; idx
<= eidx
; idx
++) {
3023 mmio
->sub_section
[idx
] = section
;
3029 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
3033 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
3036 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
3037 NULL
, TARGET_PAGE_SIZE
);
3038 mmio
->iomem
.subpage
= true;
3039 #if defined(DEBUG_SUBPAGE)
3040 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
3041 mmio
, base
, TARGET_PAGE_SIZE
);
3043 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
3048 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
3051 MemoryRegionSection section
= {
3054 .offset_within_address_space
= 0,
3055 .offset_within_region
= 0,
3056 .size
= int128_2_64(),
3059 return phys_section_add(map
, §ion
);
3062 static void readonly_mem_write(void *opaque
, hwaddr addr
,
3063 uint64_t val
, unsigned size
)
3065 /* Ignore any write to ROM. */
3068 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
3069 unsigned size
, bool is_write
,
3075 /* This will only be used for writes, because reads are special cased
3076 * to directly access the underlying host ram.
3078 static const MemoryRegionOps readonly_mem_ops
= {
3079 .write
= readonly_mem_write
,
3080 .valid
.accepts
= readonly_mem_accepts
,
3081 .endianness
= DEVICE_NATIVE_ENDIAN
,
3083 .min_access_size
= 1,
3084 .max_access_size
= 8,
3088 .min_access_size
= 1,
3089 .max_access_size
= 8,
3094 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3095 hwaddr index
, MemTxAttrs attrs
)
3097 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3098 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3099 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3100 MemoryRegionSection
*sections
= d
->map
.sections
;
3102 return §ions
[index
& ~TARGET_PAGE_MASK
];
3105 static void io_mem_init(void)
3107 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3108 NULL
, NULL
, UINT64_MAX
);
3109 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3112 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3113 * which can be called without the iothread mutex.
3115 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3117 memory_region_clear_global_locking(&io_mem_notdirty
);
3119 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3123 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3125 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3128 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3129 assert(n
== PHYS_SECTION_UNASSIGNED
);
3130 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3131 assert(n
== PHYS_SECTION_NOTDIRTY
);
3132 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3133 assert(n
== PHYS_SECTION_ROM
);
3134 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3135 assert(n
== PHYS_SECTION_WATCH
);
3137 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3142 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3144 phys_sections_free(&d
->map
);
3148 static void do_nothing(CPUState
*cpu
, run_on_cpu_data d
)
3152 static void tcg_log_global_after_sync(MemoryListener
*listener
)
3154 CPUAddressSpace
*cpuas
;
3156 /* Wait for the CPU to end the current TB. This avoids the following
3160 * ---------------------- -------------------------
3161 * TLB check -> slow path
3162 * notdirty_mem_write
3166 * TLB check -> fast path
3170 * by pushing the migration thread's memory read after the vCPU thread has
3171 * written the memory.
3173 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3174 run_on_cpu(cpuas
->cpu
, do_nothing
, RUN_ON_CPU_NULL
);
3177 static void tcg_commit(MemoryListener
*listener
)
3179 CPUAddressSpace
*cpuas
;
3180 AddressSpaceDispatch
*d
;
3182 assert(tcg_enabled());
3183 /* since each CPU stores ram addresses in its TLB cache, we must
3184 reset the modified entries */
3185 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3186 cpu_reloading_memory_map();
3187 /* The CPU and TLB are protected by the iothread lock.
3188 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3189 * may have split the RCU critical section.
3191 d
= address_space_to_dispatch(cpuas
->as
);
3192 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3193 tlb_flush(cpuas
->cpu
);
3196 static void memory_map_init(void)
3198 system_memory
= g_malloc(sizeof(*system_memory
));
3200 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3201 address_space_init(&address_space_memory
, system_memory
, "memory");
3203 system_io
= g_malloc(sizeof(*system_io
));
3204 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3206 address_space_init(&address_space_io
, system_io
, "I/O");
3209 MemoryRegion
*get_system_memory(void)
3211 return system_memory
;
3214 MemoryRegion
*get_system_io(void)
3219 #endif /* !defined(CONFIG_USER_ONLY) */
3221 /* physical memory access (slow version, mainly for debug) */
3222 #if defined(CONFIG_USER_ONLY)
3223 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3224 uint8_t *buf
, target_ulong len
, int is_write
)
3227 target_ulong l
, page
;
3231 page
= addr
& TARGET_PAGE_MASK
;
3232 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3235 flags
= page_get_flags(page
);
3236 if (!(flags
& PAGE_VALID
))
3239 if (!(flags
& PAGE_WRITE
))
3241 /* XXX: this code should not depend on lock_user */
3242 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3245 unlock_user(p
, addr
, l
);
3247 if (!(flags
& PAGE_READ
))
3249 /* XXX: this code should not depend on lock_user */
3250 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3253 unlock_user(p
, addr
, 0);
3264 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3267 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3268 addr
+= memory_region_get_ram_addr(mr
);
3270 /* No early return if dirty_log_mask is or becomes 0, because
3271 * cpu_physical_memory_set_dirty_range will still call
3272 * xen_modified_memory.
3274 if (dirty_log_mask
) {
3276 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3278 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3279 assert(tcg_enabled());
3280 tb_invalidate_phys_range(addr
, addr
+ length
);
3281 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3283 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3286 void memory_region_flush_rom_device(MemoryRegion
*mr
, hwaddr addr
, hwaddr size
)
3289 * In principle this function would work on other memory region types too,
3290 * but the ROM device use case is the only one where this operation is
3291 * necessary. Other memory regions should use the
3292 * address_space_read/write() APIs.
3294 assert(memory_region_is_romd(mr
));
3296 invalidate_and_set_dirty(mr
, addr
, size
);
3299 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3301 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3303 /* Regions are assumed to support 1-4 byte accesses unless
3304 otherwise specified. */
3305 if (access_size_max
== 0) {
3306 access_size_max
= 4;
3309 /* Bound the maximum access by the alignment of the address. */
3310 if (!mr
->ops
->impl
.unaligned
) {
3311 unsigned align_size_max
= addr
& -addr
;
3312 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3313 access_size_max
= align_size_max
;
3317 /* Don't attempt accesses larger than the maximum. */
3318 if (l
> access_size_max
) {
3319 l
= access_size_max
;
3326 static bool prepare_mmio_access(MemoryRegion
*mr
)
3328 bool unlocked
= !qemu_mutex_iothread_locked();
3329 bool release_lock
= false;
3331 if (unlocked
&& mr
->global_locking
) {
3332 qemu_mutex_lock_iothread();
3334 release_lock
= true;
3336 if (mr
->flush_coalesced_mmio
) {
3338 qemu_mutex_lock_iothread();
3340 qemu_flush_coalesced_mmio_buffer();
3342 qemu_mutex_unlock_iothread();
3346 return release_lock
;
3349 /* Called within RCU critical section. */
3350 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3353 hwaddr len
, hwaddr addr1
,
3354 hwaddr l
, MemoryRegion
*mr
)
3358 MemTxResult result
= MEMTX_OK
;
3359 bool release_lock
= false;
3362 if (!memory_access_is_direct(mr
, true)) {
3363 release_lock
|= prepare_mmio_access(mr
);
3364 l
= memory_access_size(mr
, l
, addr1
);
3365 /* XXX: could force current_cpu to NULL to avoid
3367 val
= ldn_he_p(buf
, l
);
3368 result
|= memory_region_dispatch_write(mr
, addr1
, val
,
3369 size_memop(l
), attrs
);
3372 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3373 memcpy(ptr
, buf
, l
);
3374 invalidate_and_set_dirty(mr
, addr1
, l
);
3378 qemu_mutex_unlock_iothread();
3379 release_lock
= false;
3391 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3397 /* Called from RCU critical section. */
3398 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3399 const uint8_t *buf
, hwaddr len
)
3404 MemTxResult result
= MEMTX_OK
;
3407 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3408 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3414 /* Called within RCU critical section. */
3415 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3416 MemTxAttrs attrs
, uint8_t *buf
,
3417 hwaddr len
, hwaddr addr1
, hwaddr l
,
3422 MemTxResult result
= MEMTX_OK
;
3423 bool release_lock
= false;
3426 if (!memory_access_is_direct(mr
, false)) {
3428 release_lock
|= prepare_mmio_access(mr
);
3429 l
= memory_access_size(mr
, l
, addr1
);
3430 result
|= memory_region_dispatch_read(mr
, addr1
, &val
,
3431 size_memop(l
), attrs
);
3432 stn_he_p(buf
, l
, val
);
3435 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3436 memcpy(buf
, ptr
, l
);
3440 qemu_mutex_unlock_iothread();
3441 release_lock
= false;
3453 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3459 /* Called from RCU critical section. */
3460 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3461 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3468 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3469 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3473 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3474 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3476 MemTxResult result
= MEMTX_OK
;
3481 fv
= address_space_to_flatview(as
);
3482 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3489 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3491 const uint8_t *buf
, hwaddr len
)
3493 MemTxResult result
= MEMTX_OK
;
3498 fv
= address_space_to_flatview(as
);
3499 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3506 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3507 uint8_t *buf
, hwaddr len
, bool is_write
)
3510 return address_space_write(as
, addr
, attrs
, buf
, len
);
3512 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3516 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3517 hwaddr len
, int is_write
)
3519 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3520 buf
, len
, is_write
);
3523 enum write_rom_type
{
3528 static inline MemTxResult
address_space_write_rom_internal(AddressSpace
*as
,
3533 enum write_rom_type type
)
3543 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true, attrs
);
3545 if (!(memory_region_is_ram(mr
) ||
3546 memory_region_is_romd(mr
))) {
3547 l
= memory_access_size(mr
, l
, addr1
);
3550 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3553 memcpy(ptr
, buf
, l
);
3554 invalidate_and_set_dirty(mr
, addr1
, l
);
3557 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3569 /* used for ROM loading : can write in RAM and ROM */
3570 MemTxResult
address_space_write_rom(AddressSpace
*as
, hwaddr addr
,
3572 const uint8_t *buf
, hwaddr len
)
3574 return address_space_write_rom_internal(as
, addr
, attrs
,
3575 buf
, len
, WRITE_DATA
);
3578 void cpu_flush_icache_range(hwaddr start
, hwaddr len
)
3581 * This function should do the same thing as an icache flush that was
3582 * triggered from within the guest. For TCG we are always cache coherent,
3583 * so there is no need to flush anything. For KVM / Xen we need to flush
3584 * the host's instruction cache at least.
3586 if (tcg_enabled()) {
3590 address_space_write_rom_internal(&address_space_memory
,
3591 start
, MEMTXATTRS_UNSPECIFIED
,
3592 NULL
, len
, FLUSH_CACHE
);
3603 static BounceBuffer bounce
;
3605 typedef struct MapClient
{
3607 QLIST_ENTRY(MapClient
) link
;
3610 QemuMutex map_client_list_lock
;
3611 static QLIST_HEAD(, MapClient
) map_client_list
3612 = QLIST_HEAD_INITIALIZER(map_client_list
);
3614 static void cpu_unregister_map_client_do(MapClient
*client
)
3616 QLIST_REMOVE(client
, link
);
3620 static void cpu_notify_map_clients_locked(void)
3624 while (!QLIST_EMPTY(&map_client_list
)) {
3625 client
= QLIST_FIRST(&map_client_list
);
3626 qemu_bh_schedule(client
->bh
);
3627 cpu_unregister_map_client_do(client
);
3631 void cpu_register_map_client(QEMUBH
*bh
)
3633 MapClient
*client
= g_malloc(sizeof(*client
));
3635 qemu_mutex_lock(&map_client_list_lock
);
3637 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3638 if (!atomic_read(&bounce
.in_use
)) {
3639 cpu_notify_map_clients_locked();
3641 qemu_mutex_unlock(&map_client_list_lock
);
3644 void cpu_exec_init_all(void)
3646 qemu_mutex_init(&ram_list
.mutex
);
3647 /* The data structures we set up here depend on knowing the page size,
3648 * so no more changes can be made after this point.
3649 * In an ideal world, nothing we did before we had finished the
3650 * machine setup would care about the target page size, and we could
3651 * do this much later, rather than requiring board models to state
3652 * up front what their requirements are.
3654 finalize_target_page_bits();
3657 qemu_mutex_init(&map_client_list_lock
);
3660 void cpu_unregister_map_client(QEMUBH
*bh
)
3664 qemu_mutex_lock(&map_client_list_lock
);
3665 QLIST_FOREACH(client
, &map_client_list
, link
) {
3666 if (client
->bh
== bh
) {
3667 cpu_unregister_map_client_do(client
);
3671 qemu_mutex_unlock(&map_client_list_lock
);
3674 static void cpu_notify_map_clients(void)
3676 qemu_mutex_lock(&map_client_list_lock
);
3677 cpu_notify_map_clients_locked();
3678 qemu_mutex_unlock(&map_client_list_lock
);
3681 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
3682 bool is_write
, MemTxAttrs attrs
)
3689 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3690 if (!memory_access_is_direct(mr
, is_write
)) {
3691 l
= memory_access_size(mr
, l
, addr
);
3692 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3703 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3704 hwaddr len
, bool is_write
,
3711 fv
= address_space_to_flatview(as
);
3712 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3718 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3720 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3721 bool is_write
, MemTxAttrs attrs
)
3725 MemoryRegion
*this_mr
;
3731 if (target_len
== 0) {
3736 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3737 &len
, is_write
, attrs
);
3738 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3744 /* Map a physical memory region into a host virtual address.
3745 * May map a subset of the requested range, given by and returned in *plen.
3746 * May return NULL if resources needed to perform the mapping are exhausted.
3747 * Use only for reads OR writes - not for read-modify-write operations.
3748 * Use cpu_register_map_client() to know when retrying the map operation is
3749 * likely to succeed.
3751 void *address_space_map(AddressSpace
*as
,
3769 fv
= address_space_to_flatview(as
);
3770 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3772 if (!memory_access_is_direct(mr
, is_write
)) {
3773 if (atomic_xchg(&bounce
.in_use
, true)) {
3777 /* Avoid unbounded allocations */
3778 l
= MIN(l
, TARGET_PAGE_SIZE
);
3779 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3783 memory_region_ref(mr
);
3786 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3792 return bounce
.buffer
;
3796 memory_region_ref(mr
);
3797 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3798 l
, is_write
, attrs
);
3799 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3805 /* Unmaps a memory region previously mapped by address_space_map().
3806 * Will also mark the memory as dirty if is_write == 1. access_len gives
3807 * the amount of memory that was actually read or written by the caller.
3809 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3810 int is_write
, hwaddr access_len
)
3812 if (buffer
!= bounce
.buffer
) {
3816 mr
= memory_region_from_host(buffer
, &addr1
);
3819 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3821 if (xen_enabled()) {
3822 xen_invalidate_map_cache_entry(buffer
);
3824 memory_region_unref(mr
);
3828 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3829 bounce
.buffer
, access_len
);
3831 qemu_vfree(bounce
.buffer
);
3832 bounce
.buffer
= NULL
;
3833 memory_region_unref(bounce
.mr
);
3834 atomic_mb_set(&bounce
.in_use
, false);
3835 cpu_notify_map_clients();
3838 void *cpu_physical_memory_map(hwaddr addr
,
3842 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3843 MEMTXATTRS_UNSPECIFIED
);
3846 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3847 int is_write
, hwaddr access_len
)
3849 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3852 #define ARG1_DECL AddressSpace *as
3855 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3856 #define RCU_READ_LOCK(...) rcu_read_lock()
3857 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3858 #include "memory_ldst.inc.c"
3860 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3866 AddressSpaceDispatch
*d
;
3873 cache
->fv
= address_space_get_flatview(as
);
3874 d
= flatview_to_dispatch(cache
->fv
);
3875 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3878 memory_region_ref(mr
);
3879 if (memory_access_is_direct(mr
, is_write
)) {
3880 /* We don't care about the memory attributes here as we're only
3881 * doing this if we found actual RAM, which behaves the same
3882 * regardless of attributes; so UNSPECIFIED is fine.
3884 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3885 cache
->xlat
, l
, is_write
,
3886 MEMTXATTRS_UNSPECIFIED
);
3887 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3893 cache
->is_write
= is_write
;
3897 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3901 assert(cache
->is_write
);
3902 if (likely(cache
->ptr
)) {
3903 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3907 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3909 if (!cache
->mrs
.mr
) {
3913 if (xen_enabled()) {
3914 xen_invalidate_map_cache_entry(cache
->ptr
);
3916 memory_region_unref(cache
->mrs
.mr
);
3917 flatview_unref(cache
->fv
);
3918 cache
->mrs
.mr
= NULL
;
3922 /* Called from RCU critical section. This function has the same
3923 * semantics as address_space_translate, but it only works on a
3924 * predefined range of a MemoryRegion that was mapped with
3925 * address_space_cache_init.
3927 static inline MemoryRegion
*address_space_translate_cached(
3928 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3929 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3931 MemoryRegionSection section
;
3933 IOMMUMemoryRegion
*iommu_mr
;
3934 AddressSpace
*target_as
;
3936 assert(!cache
->ptr
);
3937 *xlat
= addr
+ cache
->xlat
;
3940 iommu_mr
= memory_region_get_iommu(mr
);
3946 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3947 NULL
, is_write
, true,
3952 /* Called from RCU critical section. address_space_read_cached uses this
3953 * out of line function when the target is an MMIO or IOMMU region.
3956 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3957 void *buf
, hwaddr len
)
3963 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3964 MEMTXATTRS_UNSPECIFIED
);
3965 flatview_read_continue(cache
->fv
,
3966 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3970 /* Called from RCU critical section. address_space_write_cached uses this
3971 * out of line function when the target is an MMIO or IOMMU region.
3974 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3975 const void *buf
, hwaddr len
)
3981 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3982 MEMTXATTRS_UNSPECIFIED
);
3983 flatview_write_continue(cache
->fv
,
3984 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3988 #define ARG1_DECL MemoryRegionCache *cache
3990 #define SUFFIX _cached_slow
3991 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3992 #define RCU_READ_LOCK() ((void)0)
3993 #define RCU_READ_UNLOCK() ((void)0)
3994 #include "memory_ldst.inc.c"
3996 /* virtual memory access for debug (includes writing to ROM) */
3997 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3998 uint8_t *buf
, target_ulong len
, int is_write
)
4001 target_ulong l
, page
;
4003 cpu_synchronize_state(cpu
);
4008 page
= addr
& TARGET_PAGE_MASK
;
4009 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
4010 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
4011 /* if no physical page mapped, return an error */
4012 if (phys_addr
== -1)
4014 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
4017 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
4019 address_space_write_rom(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
4022 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
4033 * Allows code that needs to deal with migration bitmaps etc to still be built
4034 * target independent.
4036 size_t qemu_target_page_size(void)
4038 return TARGET_PAGE_SIZE
;
4041 int qemu_target_page_bits(void)
4043 return TARGET_PAGE_BITS
;
4046 int qemu_target_page_bits_min(void)
4048 return TARGET_PAGE_BITS_MIN
;
4052 bool target_words_bigendian(void)
4054 #if defined(TARGET_WORDS_BIGENDIAN)
4061 #ifndef CONFIG_USER_ONLY
4062 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
4069 mr
= address_space_translate(&address_space_memory
,
4070 phys_addr
, &phys_addr
, &l
, false,
4071 MEMTXATTRS_UNSPECIFIED
);
4073 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
4078 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
4084 RAMBLOCK_FOREACH(block
) {
4085 ret
= func(block
, opaque
);
4095 * Unmap pages of memory from start to start+length such that
4096 * they a) read as 0, b) Trigger whatever fault mechanism
4097 * the OS provides for postcopy.
4098 * The pages must be unmapped by the end of the function.
4099 * Returns: 0 on success, none-0 on failure
4102 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
4106 uint8_t *host_startaddr
= rb
->host
+ start
;
4108 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
4109 error_report("ram_block_discard_range: Unaligned start address: %p",
4114 if ((start
+ length
) <= rb
->used_length
) {
4115 bool need_madvise
, need_fallocate
;
4116 uint8_t *host_endaddr
= host_startaddr
+ length
;
4117 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
4118 error_report("ram_block_discard_range: Unaligned end address: %p",
4123 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4125 /* The logic here is messy;
4126 * madvise DONTNEED fails for hugepages
4127 * fallocate works on hugepages and shmem
4129 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4130 need_fallocate
= rb
->fd
!= -1;
4131 if (need_fallocate
) {
4132 /* For a file, this causes the area of the file to be zero'd
4133 * if read, and for hugetlbfs also causes it to be unmapped
4134 * so a userfault will trigger.
4136 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4137 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4141 error_report("ram_block_discard_range: Failed to fallocate "
4142 "%s:%" PRIx64
" +%zx (%d)",
4143 rb
->idstr
, start
, length
, ret
);
4148 error_report("ram_block_discard_range: fallocate not available/file"
4149 "%s:%" PRIx64
" +%zx (%d)",
4150 rb
->idstr
, start
, length
, ret
);
4155 /* For normal RAM this causes it to be unmapped,
4156 * for shared memory it causes the local mapping to disappear
4157 * and to fall back on the file contents (which we just
4158 * fallocate'd away).
4160 #if defined(CONFIG_MADVISE)
4161 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4164 error_report("ram_block_discard_range: Failed to discard range "
4165 "%s:%" PRIx64
" +%zx (%d)",
4166 rb
->idstr
, start
, length
, ret
);
4171 error_report("ram_block_discard_range: MADVISE not available"
4172 "%s:%" PRIx64
" +%zx (%d)",
4173 rb
->idstr
, start
, length
, ret
);
4177 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4178 need_madvise
, need_fallocate
, ret
);
4180 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4181 "/%zx/" RAM_ADDR_FMT
")",
4182 rb
->idstr
, start
, length
, rb
->used_length
);
4189 bool ramblock_is_pmem(RAMBlock
*rb
)
4191 return rb
->flags
& RAM_PMEM
;
4196 void page_size_init(void)
4198 /* NOTE: we can always suppose that qemu_host_page_size >=
4200 if (qemu_host_page_size
== 0) {
4201 qemu_host_page_size
= qemu_real_host_page_size
;
4203 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4204 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4206 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4209 #if !defined(CONFIG_USER_ONLY)
4211 static void mtree_print_phys_entries(int start
, int end
, int skip
, int ptr
)
4213 if (start
== end
- 1) {
4214 qemu_printf("\t%3d ", start
);
4216 qemu_printf("\t%3d..%-3d ", start
, end
- 1);
4218 qemu_printf(" skip=%d ", skip
);
4219 if (ptr
== PHYS_MAP_NODE_NIL
) {
4220 qemu_printf(" ptr=NIL");
4222 qemu_printf(" ptr=#%d", ptr
);
4224 qemu_printf(" ptr=[%d]", ptr
);
4229 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4230 int128_sub((size), int128_one())) : 0)
4232 void mtree_print_dispatch(AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4236 qemu_printf(" Dispatch\n");
4237 qemu_printf(" Physical sections\n");
4239 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4240 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4241 const char *names
[] = { " [unassigned]", " [not dirty]",
4242 " [ROM]", " [watch]" };
4244 qemu_printf(" #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
4247 s
->offset_within_address_space
,
4248 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4249 s
->mr
->name
? s
->mr
->name
: "(noname)",
4250 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4251 s
->mr
== root
? " [ROOT]" : "",
4252 s
== d
->mru_section
? " [MRU]" : "",
4253 s
->mr
->is_iommu
? " [iommu]" : "");
4256 qemu_printf(" alias=%s", s
->mr
->alias
->name
?
4257 s
->mr
->alias
->name
: "noname");
4262 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4263 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4264 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4267 Node
*n
= d
->map
.nodes
+ i
;
4269 qemu_printf(" [%d]\n", i
);
4271 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4272 PhysPageEntry
*pe
= *n
+ j
;
4274 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4278 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);
4284 if (jprev
!= ARRAY_SIZE(*n
)) {
4285 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);