]> git.proxmox.com Git - mirror_qemu.git/blob - hw/arm/allwinner-h3.c
projects / mirror_qemu.git / blob
? search:


2d684b5287b46ca3e38420a739542994a5338a2f
[mirror_qemu.git] / hw / arm / allwinner-h3.c
1 /*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qemu/units.h"
25 #include "hw/qdev-core.h"
26 #include "hw/sysbus.h"
27 #include "hw/char/serial.h"
28 #include "hw/misc/unimp.h"
29 #include "hw/usb/hcd-ehci.h"
30 #include "hw/loader.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/arm/allwinner-h3.h"
33 #include "target/arm/cpu-qom.h"
34
35 /* Memory map */
36 const hwaddr allwinner_h3_memmap[] = {
37 [AW_H3_DEV_SRAM_A1] = 0x00000000,
38 [AW_H3_DEV_SRAM_A2] = 0x00044000,
39 [AW_H3_DEV_SRAM_C] = 0x00010000,
40 [AW_H3_DEV_SYSCTRL] = 0x01c00000,
41 [AW_H3_DEV_MMC0] = 0x01c0f000,
42 [AW_H3_DEV_SID] = 0x01c14000,
43 [AW_H3_DEV_EHCI0] = 0x01c1a000,
44 [AW_H3_DEV_OHCI0] = 0x01c1a400,
45 [AW_H3_DEV_EHCI1] = 0x01c1b000,
46 [AW_H3_DEV_OHCI1] = 0x01c1b400,
47 [AW_H3_DEV_EHCI2] = 0x01c1c000,
48 [AW_H3_DEV_OHCI2] = 0x01c1c400,
49 [AW_H3_DEV_EHCI3] = 0x01c1d000,
50 [AW_H3_DEV_OHCI3] = 0x01c1d400,
51 [AW_H3_DEV_CCU] = 0x01c20000,
52 [AW_H3_DEV_PIT] = 0x01c20c00,
53 [AW_H3_DEV_WDT] = 0x01c20ca0,
54 [AW_H3_DEV_UART0] = 0x01c28000,
55 [AW_H3_DEV_UART1] = 0x01c28400,
56 [AW_H3_DEV_UART2] = 0x01c28800,
57 [AW_H3_DEV_UART3] = 0x01c28c00,
58 [AW_H3_DEV_TWI0] = 0x01c2ac00,
59 [AW_H3_DEV_TWI1] = 0x01c2b000,
60 [AW_H3_DEV_TWI2] = 0x01c2b400,
61 [AW_H3_DEV_EMAC] = 0x01c30000,
62 [AW_H3_DEV_DRAMCOM] = 0x01c62000,
63 [AW_H3_DEV_DRAMCTL] = 0x01c63000,
64 [AW_H3_DEV_DRAMPHY] = 0x01c65000,
65 [AW_H3_DEV_GIC_DIST] = 0x01c81000,
66 [AW_H3_DEV_GIC_CPU] = 0x01c82000,
67 [AW_H3_DEV_GIC_HYP] = 0x01c84000,
68 [AW_H3_DEV_GIC_VCPU] = 0x01c86000,
69 [AW_H3_DEV_RTC] = 0x01f00000,
70 [AW_H3_DEV_CPUCFG] = 0x01f01c00,
71 [AW_H3_DEV_R_TWI] = 0x01f02400,
72 [AW_H3_DEV_SDRAM] = 0x40000000
73 };
74
75 /* List of unimplemented devices */
76 struct AwH3Unimplemented {
77 const char *device_name;
78 hwaddr base;
79 hwaddr size;
80 } unimplemented[] = {
81 { "d-engine", 0x01000000, 4 * MiB },
82 { "d-inter", 0x01400000, 128 * KiB },
83 { "dma", 0x01c02000, 4 * KiB },
84 { "nfdc", 0x01c03000, 4 * KiB },
85 { "ts", 0x01c06000, 4 * KiB },
86 { "keymem", 0x01c0b000, 4 * KiB },
87 { "lcd0", 0x01c0c000, 4 * KiB },
88 { "lcd1", 0x01c0d000, 4 * KiB },
89 { "ve", 0x01c0e000, 4 * KiB },
90 { "mmc1", 0x01c10000, 4 * KiB },
91 { "mmc2", 0x01c11000, 4 * KiB },
92 { "crypto", 0x01c15000, 4 * KiB },
93 { "msgbox", 0x01c17000, 4 * KiB },
94 { "spinlock", 0x01c18000, 4 * KiB },
95 { "usb0-otg", 0x01c19000, 4 * KiB },
96 { "usb0-phy", 0x01c1a000, 4 * KiB },
97 { "usb1-phy", 0x01c1b000, 4 * KiB },
98 { "usb2-phy", 0x01c1c000, 4 * KiB },
99 { "usb3-phy", 0x01c1d000, 4 * KiB },
100 { "smc", 0x01c1e000, 4 * KiB },
101 { "pio", 0x01c20800, 1 * KiB },
102 { "owa", 0x01c21000, 1 * KiB },
103 { "pwm", 0x01c21400, 1 * KiB },
104 { "keyadc", 0x01c21800, 1 * KiB },
105 { "pcm0", 0x01c22000, 1 * KiB },
106 { "pcm1", 0x01c22400, 1 * KiB },
107 { "pcm2", 0x01c22800, 1 * KiB },
108 { "audio", 0x01c22c00, 2 * KiB },
109 { "smta", 0x01c23400, 1 * KiB },
110 { "ths", 0x01c25000, 1 * KiB },
111 { "uart0", 0x01c28000, 1 * KiB },
112 { "uart1", 0x01c28400, 1 * KiB },
113 { "uart2", 0x01c28800, 1 * KiB },
114 { "uart3", 0x01c28c00, 1 * KiB },
115 { "scr", 0x01c2c400, 1 * KiB },
116 { "gpu", 0x01c40000, 64 * KiB },
117 { "hstmr", 0x01c60000, 4 * KiB },
118 { "spi0", 0x01c68000, 4 * KiB },
119 { "spi1", 0x01c69000, 4 * KiB },
120 { "csi", 0x01cb0000, 320 * KiB },
121 { "tve", 0x01e00000, 64 * KiB },
122 { "hdmi", 0x01ee0000, 128 * KiB },
123 { "r_timer", 0x01f00800, 1 * KiB },
124 { "r_intc", 0x01f00c00, 1 * KiB },
125 { "r_wdog", 0x01f01000, 1 * KiB },
126 { "r_prcm", 0x01f01400, 1 * KiB },
127 { "r_twd", 0x01f01800, 1 * KiB },
128 { "r_cir-rx", 0x01f02000, 1 * KiB },
129 { "r_uart", 0x01f02800, 1 * KiB },
130 { "r_pio", 0x01f02c00, 1 * KiB },
131 { "r_pwm", 0x01f03800, 1 * KiB },
132 { "core-dbg", 0x3f500000, 128 * KiB },
133 { "tsgen-ro", 0x3f506000, 4 * KiB },
134 { "tsgen-ctl", 0x3f507000, 4 * KiB },
135 { "ddr-mem", 0x40000000, 2 * GiB },
136 { "n-brom", 0xffff0000, 32 * KiB },
137 { "s-brom", 0xffff0000, 64 * KiB }
138 };
139
140 /* Per Processor Interrupts */
141 enum {
142 AW_H3_GIC_PPI_MAINT = 9,
143 AW_H3_GIC_PPI_HYPTIMER = 10,
144 AW_H3_GIC_PPI_VIRTTIMER = 11,
145 AW_H3_GIC_PPI_SECTIMER = 13,
146 AW_H3_GIC_PPI_PHYSTIMER = 14
147 };
148
149 /* Shared Processor Interrupts */
150 enum {
151 AW_H3_GIC_SPI_UART0 = 0,
152 AW_H3_GIC_SPI_UART1 = 1,
153 AW_H3_GIC_SPI_UART2 = 2,
154 AW_H3_GIC_SPI_UART3 = 3,
155 AW_H3_GIC_SPI_TWI0 = 6,
156 AW_H3_GIC_SPI_TWI1 = 7,
157 AW_H3_GIC_SPI_TWI2 = 8,
158 AW_H3_GIC_SPI_TIMER0 = 18,
159 AW_H3_GIC_SPI_TIMER1 = 19,
160 AW_H3_GIC_SPI_R_TWI = 44,
161 AW_H3_GIC_SPI_MMC0 = 60,
162 AW_H3_GIC_SPI_EHCI0 = 72,
163 AW_H3_GIC_SPI_OHCI0 = 73,
164 AW_H3_GIC_SPI_EHCI1 = 74,
165 AW_H3_GIC_SPI_OHCI1 = 75,
166 AW_H3_GIC_SPI_EHCI2 = 76,
167 AW_H3_GIC_SPI_OHCI2 = 77,
168 AW_H3_GIC_SPI_EHCI3 = 78,
169 AW_H3_GIC_SPI_OHCI3 = 79,
170 AW_H3_GIC_SPI_EMAC = 82
171 };
172
173 /* Allwinner H3 general constants */
174 enum {
175 AW_H3_GIC_NUM_SPI = 128
176 };
177
178 void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
179 {
180 const int64_t rom_size = 32 * KiB;
181 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
182
183 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
184 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
185 __func__);
186 return;
187 }
188
189 rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
190 rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
191 NULL, NULL, NULL, NULL, false);
192 }
193
194 static void allwinner_h3_init(Object *obj)
195 {
196 AwH3State *s = AW_H3(obj);
197
198 s->memmap = allwinner_h3_memmap;
199
200 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
201 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
202 ARM_CPU_TYPE_NAME("cortex-a7"));
203 }
204
205 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
206
207 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
208 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
209 "clk0-freq");
210 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
211 "clk1-freq");
212
213 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_H3_CCU);
214
215 object_initialize_child(obj, "sysctrl", &s->sysctrl, TYPE_AW_H3_SYSCTRL);
216
217 object_initialize_child(obj, "cpucfg", &s->cpucfg, TYPE_AW_CPUCFG);
218
219 object_initialize_child(obj, "sid", &s->sid, TYPE_AW_SID);
220 object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
221 "identifier");
222
223 object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN5I);
224
225 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_SUN8I_EMAC);
226
227 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_H3_DRAMC);
228 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
229 "ram-addr");
230 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
231 "ram-size");
232
233 object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
234
235 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
236 object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I);
237 object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I);
238 object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
239
240 object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN6I);
241 }
242
243 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
244 {
245 AwH3State *s = AW_H3(dev);
246 unsigned i;
247
248 /* CPUs */
249 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
250
251 /*
252 * Disable secondary CPUs. Guest EL3 firmware will start
253 * them via CPU reset control registers.
254 */
255 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
256 i > 0);
257
258 /* All exception levels required */
259 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
260 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
261
262 /* Mark realized */
263 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
264 }
265
266 /* Generic Interrupt Controller */
267 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
268 GIC_INTERNAL);
269 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
270 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
271 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
272 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
273 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
274
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]);
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]);
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]);
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]);
279
280 /*
281 * Wire the outputs from each CPU's generic timer and the GICv3
282 * maintenance interrupt signal to the appropriate GIC PPI inputs,
283 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
284 */
285 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
286 DeviceState *cpudev = DEVICE(&s->cpus[i]);
287 int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
288 int irq;
289 /*
290 * Mapping from the output timer irq lines from the CPU to the
291 * GIC PPI inputs used for this board.
292 */
293 const int timer_irq[] = {
294 [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
295 [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
296 [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
297 [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
298 };
299
300 /* Connect CPU timer outputs to GIC PPI inputs */
301 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
302 qdev_connect_gpio_out(cpudev, irq,
303 qdev_get_gpio_in(DEVICE(&s->gic),
304 ppibase + timer_irq[irq]));
305 }
306
307 /* Connect GIC outputs to CPU interrupt inputs */
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
309 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
310 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
311 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
312 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
313 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
315 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
316
317 /* GIC maintenance signal */
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
319 qdev_get_gpio_in(DEVICE(&s->gic),
320 ppibase + AW_H3_GIC_PPI_MAINT));
321 }
322
323 /* Timer */
324 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]);
326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
327 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
329 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
330
331 /* SRAM */
332 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
333 64 * KiB, &error_abort);
334 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
335 32 * KiB, &error_abort);
336 memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
337 44 * KiB, &error_abort);
338 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1],
339 &s->sram_a1);
340 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2],
341 &s->sram_a2);
342 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C],
343 &s->sram_c);
344
345 /* Clock Control Unit */
346 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]);
348
349 /* System Control */
350 sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_DEV_SYSCTRL]);
352
353 /* CPU Configuration */
354 sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_DEV_CPUCFG]);
356
357 /* Security Identifier */
358 sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);
360
361 /* SD/MMC */
362 object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
363 OBJECT(get_system_memory()), &error_fatal);
364 sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
365 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
366 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
367 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
368
369 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
370 "sd-bus");
371
372 /* EMAC */
373 /* FIXME use qdev NIC properties instead of nd_table[] */
374 if (nd_table[0].used) {
375 qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
376 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
377 }
378 object_property_set_link(OBJECT(&s->emac), "dma-memory",
379 OBJECT(get_system_memory()), &error_fatal);
380 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
381 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
382 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
383 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
384
385 /* Universal Serial Bus */
386 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
387 qdev_get_gpio_in(DEVICE(&s->gic),
388 AW_H3_GIC_SPI_EHCI0));
389 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
390 qdev_get_gpio_in(DEVICE(&s->gic),
391 AW_H3_GIC_SPI_EHCI1));
392 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
393 qdev_get_gpio_in(DEVICE(&s->gic),
394 AW_H3_GIC_SPI_EHCI2));
395 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
396 qdev_get_gpio_in(DEVICE(&s->gic),
397 AW_H3_GIC_SPI_EHCI3));
398
399 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
400 qdev_get_gpio_in(DEVICE(&s->gic),
401 AW_H3_GIC_SPI_OHCI0));
402 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
403 qdev_get_gpio_in(DEVICE(&s->gic),
404 AW_H3_GIC_SPI_OHCI1));
405 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
406 qdev_get_gpio_in(DEVICE(&s->gic),
407 AW_H3_GIC_SPI_OHCI2));
408 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
409 qdev_get_gpio_in(DEVICE(&s->gic),
410 AW_H3_GIC_SPI_OHCI3));
411
412 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
413 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
414 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
415 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
416 /* UART1 */
417 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
418 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
419 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
420 /* UART2 */
421 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
422 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
423 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
424 /* UART3 */
425 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
426 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
427 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
428
429 /* DRAMC */
430 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
431 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DEV_DRAMCOM]);
432 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DEV_DRAMCTL]);
433 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DEV_DRAMPHY]);
434
435 /* RTC */
436 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
438
439 /* I2C */
440 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
441 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]);
442 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
443 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
444
445 sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
446 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
447 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
448 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
449
450 sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
451 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
452 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
453 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
454
455 sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
456 sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
457 sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
458 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
459
460 /* WDT */
461 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
462 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
463 s->memmap[AW_H3_DEV_WDT], 1);
464
465 /* Unimplemented devices */
466 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
467 create_unimplemented_device(unimplemented[i].device_name,
468 unimplemented[i].base,
469 unimplemented[i].size);
470 }
471 }
472
473 static void allwinner_h3_class_init(ObjectClass *oc, void *data)
474 {
475 DeviceClass *dc = DEVICE_CLASS(oc);
476
477 dc->realize = allwinner_h3_realize;
478 /* Reason: uses serial_hd() in realize function */
479 dc->user_creatable = false;
480 }
481
482 static const TypeInfo allwinner_h3_type_info = {
483 .name = TYPE_AW_H3,
484 .parent = TYPE_DEVICE,
485 .instance_size = sizeof(AwH3State),
486 .instance_init = allwinner_h3_init,
487 .class_init = allwinner_h3_class_init,
488 };
489
490 static void allwinner_h3_register_types(void)
491 {
492 type_register_static(&allwinner_h3_type_info);
493 }
494
495 type_init(allwinner_h3_register_types)
QEMU mirror