hw/arm/armv7m.c

   1 /*
   2  * ARMV7M System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/arm/armv7m.h"
  12 #include "qapi/error.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/loader.h"
  16 #include "hw/qdev-properties.h"
  17 #include "hw/qdev-clock.h"
  18 #include "elf.h"
  19 #include "sysemu/reset.h"
  20 #include "qemu/error-report.h"
  21 #include "qemu/module.h"
  22 #include "qemu/log.h"
  23 #include "target/arm/idau.h"
  24 #include "migration/vmstate.h"
  25
  26 /* Bitbanded IO.  Each word corresponds to a single bit.  */
  27
  28 /* Get the byte address of the real memory for a bitband access.  */
  29 static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
  30 {
  31     return s->base | (offset & 0x1ffffff) >> 5;
  32 }
  33
  34 static MemTxResult bitband_read(void *opaque, hwaddr offset,
  35                                 uint64_t *data, unsigned size, MemTxAttrs attrs)
  36 {
  37     BitBandState *s = opaque;
  38     uint8_t buf[4];
  39     MemTxResult res;
  40     int bitpos, bit;
  41     hwaddr addr;
  42
  43     assert(size <= 4);
  44
  45     /* Find address in underlying memory and round down to multiple of size */
  46     addr = bitband_addr(s, offset) & (-size);
  47     res = address_space_read(&s->source_as, addr, attrs, buf, size);
  48     if (res) {
  49         return res;
  50     }
  51     /* Bit position in the N bytes read... */
  52     bitpos = (offset >> 2) & ((size * 8) - 1);
  53     /* ...converted to byte in buffer and bit in byte */
  54     bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
  55     *data = bit;
  56     return MEMTX_OK;
  57 }
  58
  59 static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
  60                                  unsigned size, MemTxAttrs attrs)
  61 {
  62     BitBandState *s = opaque;
  63     uint8_t buf[4];
  64     MemTxResult res;
  65     int bitpos, bit;
  66     hwaddr addr;
  67
  68     assert(size <= 4);
  69
  70     /* Find address in underlying memory and round down to multiple of size */
  71     addr = bitband_addr(s, offset) & (-size);
  72     res = address_space_read(&s->source_as, addr, attrs, buf, size);
  73     if (res) {
  74         return res;
  75     }
  76     /* Bit position in the N bytes read... */
  77     bitpos = (offset >> 2) & ((size * 8) - 1);
  78     /* ...converted to byte in buffer and bit in byte */
  79     bit = 1 << (bitpos & 7);
  80     if (value & 1) {
  81         buf[bitpos >> 3] |= bit;
  82     } else {
  83         buf[bitpos >> 3] &= ~bit;
  84     }
  85     return address_space_write(&s->source_as, addr, attrs, buf, size);
  86 }
  87
  88 static const MemoryRegionOps bitband_ops = {
  89     .read_with_attrs = bitband_read,
  90     .write_with_attrs = bitband_write,
  91     .endianness = DEVICE_NATIVE_ENDIAN,
  92     .impl.min_access_size = 1,
  93     .impl.max_access_size = 4,
  94     .valid.min_access_size = 1,
  95     .valid.max_access_size = 4,
  96 };
  97
  98 static void bitband_init(Object *obj)
  99 {
 100     BitBandState *s = BITBAND(obj);
 101     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 102
 103     memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
 104                           "bitband", 0x02000000);
 105     sysbus_init_mmio(dev, &s->iomem);
 106 }
 107
 108 static void bitband_realize(DeviceState *dev, Error **errp)
 109 {
 110     BitBandState *s = BITBAND(dev);
 111
 112     if (!s->source_memory) {
 113         error_setg(errp, "source-memory property not set");
 114         return;
 115     }
 116
 117     address_space_init(&s->source_as, s->source_memory, "bitband-source");
 118 }
 119
 120 /* Board init.  */
 121
 122 static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
 123     0x20000000, 0x40000000
 124 };
 125
 126 static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
 127     0x22000000, 0x42000000
 128 };
 129
 130 static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr,
 131                                        uint64_t value, unsigned size,
 132                                        MemTxAttrs attrs)
 133 {
 134     MemoryRegion *mr = opaque;
 135
 136     if (attrs.secure) {
 137         /* S accesses to the alias act like NS accesses to the real region */
 138         attrs.secure = 0;
 139         return memory_region_dispatch_write(mr, addr, value,
 140                                             size_memop(size) | MO_TE, attrs);
 141     } else {
 142         /* NS attrs are RAZ/WI for privileged, and BusFault for user */
 143         if (attrs.user) {
 144             return MEMTX_ERROR;
 145         }
 146         return MEMTX_OK;
 147     }
 148 }
 149
 150 static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr,
 151                                       uint64_t *data, unsigned size,
 152                                       MemTxAttrs attrs)
 153 {
 154     MemoryRegion *mr = opaque;
 155
 156     if (attrs.secure) {
 157         /* S accesses to the alias act like NS accesses to the real region */
 158         attrs.secure = 0;
 159         return memory_region_dispatch_read(mr, addr, data,
 160                                            size_memop(size) | MO_TE, attrs);
 161     } else {
 162         /* NS attrs are RAZ/WI for privileged, and BusFault for user */
 163         if (attrs.user) {
 164             return MEMTX_ERROR;
 165         }
 166         *data = 0;
 167         return MEMTX_OK;
 168     }
 169 }
 170
 171 static const MemoryRegionOps v7m_sysreg_ns_ops = {
 172     .read_with_attrs = v7m_sysreg_ns_read,
 173     .write_with_attrs = v7m_sysreg_ns_write,
 174     .endianness = DEVICE_NATIVE_ENDIAN,
 175 };
 176
 177 static MemTxResult v7m_systick_write(void *opaque, hwaddr addr,
 178                                      uint64_t value, unsigned size,
 179                                      MemTxAttrs attrs)
 180 {
 181     ARMv7MState *s = opaque;
 182     MemoryRegion *mr;
 183
 184     /* Direct the access to the correct systick */
 185     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
 186     return memory_region_dispatch_write(mr, addr, value,
 187                                         size_memop(size) | MO_TE, attrs);
 188 }
 189
 190 static MemTxResult v7m_systick_read(void *opaque, hwaddr addr,
 191                                     uint64_t *data, unsigned size,
 192                                     MemTxAttrs attrs)
 193 {
 194     ARMv7MState *s = opaque;
 195     MemoryRegion *mr;
 196
 197     /* Direct the access to the correct systick */
 198     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
 199     return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
 200                                        attrs);
 201 }
 202
 203 static const MemoryRegionOps v7m_systick_ops = {
 204     .read_with_attrs = v7m_systick_read,
 205     .write_with_attrs = v7m_systick_write,
 206     .endianness = DEVICE_NATIVE_ENDIAN,
 207 };
 208
 209 /*
 210  * Unassigned portions of the PPB space are RAZ/WI for privileged
 211  * accesses, and fault for non-privileged accesses.
 212  */
 213 static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
 214                                     uint64_t *data, unsigned size,
 215                                     MemTxAttrs attrs)
 216 {
 217     qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
 218                   (uint32_t)addr);
 219     if (attrs.user) {
 220         return MEMTX_ERROR;
 221     }
 222     *data = 0;
 223     return MEMTX_OK;
 224 }
 225
 226 static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
 227                                      uint64_t value, unsigned size,
 228                                      MemTxAttrs attrs)
 229 {
 230     qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
 231                   (uint32_t)addr);
 232     if (attrs.user) {
 233         return MEMTX_ERROR;
 234     }
 235     return MEMTX_OK;
 236 }
 237
 238 static const MemoryRegionOps ppb_default_ops = {
 239     .read_with_attrs = ppb_default_read,
 240     .write_with_attrs = ppb_default_write,
 241     .endianness = DEVICE_NATIVE_ENDIAN,
 242     .valid.min_access_size = 1,
 243     .valid.max_access_size = 8,
 244 };
 245
 246 static void armv7m_instance_init(Object *obj)
 247 {
 248     ARMv7MState *s = ARMV7M(obj);
 249     int i;
 250
 251     /* Can't init the cpu here, we don't yet know which model to use */
 252
 253     memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
 254
 255     object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC);
 256     object_property_add_alias(obj, "num-irq",
 257                               OBJECT(&s->nvic), "num-irq");
 258
 259     object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS],
 260                             TYPE_SYSTICK);
 261     /*
 262      * We can't initialize the secure systick here, as we don't know
 263      * yet if we need it.
 264      */
 265
 266     for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
 267         object_initialize_child(obj, "bitband[*]", &s->bitband[i],
 268                                 TYPE_BITBAND);
 269     }
 270
 271     s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
 272     s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
 273 }
 274
 275 static void armv7m_realize(DeviceState *dev, Error **errp)
 276 {
 277     ARMv7MState *s = ARMV7M(dev);
 278     SysBusDevice *sbd;
 279     Error *err = NULL;
 280     int i;
 281
 282     if (!s->board_memory) {
 283         error_setg(errp, "memory property was not set");
 284         return;
 285     }
 286
 287     /* cpuclk must be connected; refclk is optional */
 288     if (!clock_has_source(s->cpuclk)) {
 289         error_setg(errp, "armv7m: cpuclk must be connected");
 290         return;
 291     }
 292
 293     memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
 294
 295     s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu",
 296                                            &err, NULL));
 297     if (err != NULL) {
 298         error_propagate(errp, err);
 299         return;
 300     }
 301
 302     object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->container),
 303                              &error_abort);
 304     if (object_property_find(OBJECT(s->cpu), "idau")) {
 305         object_property_set_link(OBJECT(s->cpu), "idau", s->idau,
 306                                  &error_abort);
 307     }
 308     if (object_property_find(OBJECT(s->cpu), "init-svtor")) {
 309         if (!object_property_set_uint(OBJECT(s->cpu), "init-svtor",
 310                                       s->init_svtor, errp)) {
 311             return;
 312         }
 313     }
 314     if (object_property_find(OBJECT(s->cpu), "init-nsvtor")) {
 315         if (!object_property_set_uint(OBJECT(s->cpu), "init-nsvtor",
 316                                       s->init_nsvtor, errp)) {
 317             return;
 318         }
 319     }
 320     if (object_property_find(OBJECT(s->cpu), "start-powered-off")) {
 321         if (!object_property_set_bool(OBJECT(s->cpu), "start-powered-off",
 322                                       s->start_powered_off, errp)) {
 323             return;
 324         }
 325     }
 326     if (object_property_find(OBJECT(s->cpu), "vfp")) {
 327         if (!object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, errp)) {
 328             return;
 329         }
 330     }
 331     if (object_property_find(OBJECT(s->cpu), "dsp")) {
 332         if (!object_property_set_bool(OBJECT(s->cpu), "dsp", s->dsp, errp)) {
 333             return;
 334         }
 335     }
 336
 337     /*
 338      * Real M-profile hardware can be configured with a different number of
 339      * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
 340      * support that yet, so catch attempts to select that.
 341      */
 342     if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
 343         s->mpu_ns_regions != s->mpu_s_regions) {
 344         error_setg(errp,
 345                    "mpu-ns-regions and mpu-s-regions properties must have the same value");
 346         return;
 347     }
 348     if (s->mpu_ns_regions != UINT_MAX &&
 349         object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
 350         if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
 351                                       s->mpu_ns_regions, errp)) {
 352             return;
 353         }
 354     }
 355
 356     /*
 357      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
 358      * have one. Similarly, tell the NVIC where its CPU is.
 359      */
 360     s->cpu->env.nvic = &s->nvic;
 361     s->nvic.cpu = s->cpu;
 362
 363     if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) {
 364         return;
 365     }
 366
 367     /* Note that we must realize the NVIC after the CPU */
 368     if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvic), errp)) {
 369         return;
 370     }
 371
 372     /* Alias the NVIC's input and output GPIOs as our own so the board
 373      * code can wire them up. (We do this in realize because the
 374      * NVIC doesn't create the input GPIO array until realize.)
 375      */
 376     qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
 377     qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
 378     qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
 379
 380     /*
 381      * We map various devices into the container MR at their architected
 382      * addresses. In particular, we map everything corresponding to the
 383      * "System PPB" space. This is the range from 0xe0000000 to 0xe00fffff
 384      * and includes the NVIC, the System Control Space (system registers),
 385      * the systick timer, and for CPUs with the Security extension an NS
 386      * banked version of all of these.
 387      *
 388      * The default behaviour for unimplemented registers/ranges
 389      * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
 390      * is to RAZ/WI for privileged access and BusFault for non-privileged
 391      * access.
 392      *
 393      * The NVIC and System Control Space (SCS) starts at 0xe000e000
 394      * and looks like this:
 395      *  0x004 - ICTR
 396      *  0x010 - 0xff - systick
 397      *  0x100..0x7ec - NVIC
 398      *  0x7f0..0xcff - Reserved
 399      *  0xd00..0xd3c - SCS registers
 400      *  0xd40..0xeff - Reserved or Not implemented
 401      *  0xf00 - STIR
 402      *
 403      * Some registers within this space are banked between security states.
 404      * In v8M there is a second range 0xe002e000..0xe002efff which is the
 405      * NonSecure alias SCS; secure accesses to this behave like NS accesses
 406      * to the main SCS range, and non-secure accesses (including when
 407      * the security extension is not implemented) are RAZ/WI.
 408      * Note that both the main SCS range and the alias range are defined
 409      * to be exempt from memory attribution (R_BLJT) and so the memory
 410      * transaction attribute always matches the current CPU security
 411      * state (attrs.secure == env->v7m.secure). In the v7m_sysreg_ns_ops
 412      * wrappers we change attrs.secure to indicate the NS access; so
 413      * generally code determining which banked register to use should
 414      * use attrs.secure; code determining actual behaviour of the system
 415      * should use env->v7m.secure.
 416      *
 417      * Within the PPB space, some MRs overlap, and the priority
 418      * of overlapping regions is:
 419      *  - default region (for RAZ/WI and BusFault) : -1
 420      *  - system register regions (provided by the NVIC) : 0
 421      *  - systick : 1
 422      * This is because the systick device is a small block of registers
 423      * in the middle of the other system control registers.
 424      */
 425
 426     memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
 427                           "nvic-default", 0x100000);
 428     memory_region_add_subregion_overlap(&s->container, 0xe0000000,
 429                                         &s->defaultmem, -1);
 430
 431     /* Wire the NVIC up to the CPU */
 432     sbd = SYS_BUS_DEVICE(&s->nvic);
 433     sysbus_connect_irq(sbd, 0,
 434                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
 435
 436     memory_region_add_subregion(&s->container, 0xe000e000,
 437                                 sysbus_mmio_get_region(sbd, 0));
 438     if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
 439         /* Create the NS alias region for the NVIC sysregs */
 440         memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
 441                               &v7m_sysreg_ns_ops,
 442                               sysbus_mmio_get_region(sbd, 0),
 443                               "nvic_sysregs_ns", 0x1000);
 444         memory_region_add_subregion(&s->container, 0xe002e000,
 445                                     &s->sysreg_ns_mem);
 446     }
 447
 448     /*
 449      * Create and map the systick devices. Note that we only connect
 450      * refclk if it has been connected to us; otherwise the systick
 451      * device gets the wrong answer for clock_has_source(refclk), because
 452      * it has an immediate source (the ARMv7M's clock object) but not
 453      * an ultimate source, and then it won't correctly auto-select the
 454      * CPU clock as its only possible clock source.
 455      */
 456     if (clock_has_source(s->refclk)) {
 457         qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk",
 458                               s->refclk);
 459     }
 460     qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk);
 461     if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
 462         return;
 463     }
 464     sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
 465                        qdev_get_gpio_in_named(DEVICE(&s->nvic),
 466                                               "systick-trigger", M_REG_NS));
 467
 468     if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
 469         /*
 470          * We couldn't init the secure systick device in instance_init
 471          * as we didn't know then if the CPU had the security extensions;
 472          * so we have to do it here.
 473          */
 474         object_initialize_child(OBJECT(dev), "systick-reg-s",
 475                                 &s->systick[M_REG_S], TYPE_SYSTICK);
 476         if (clock_has_source(s->refclk)) {
 477             qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
 478                                   s->refclk);
 479         }
 480         qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk",
 481                               s->cpuclk);
 482
 483         if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
 484             return;
 485         }
 486         sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
 487                            qdev_get_gpio_in_named(DEVICE(&s->nvic),
 488                                                   "systick-trigger", M_REG_S));
 489     }
 490
 491     memory_region_init_io(&s->systickmem, OBJECT(s),
 492                           &v7m_systick_ops, s,
 493                           "v7m_systick", 0xe0);
 494
 495     memory_region_add_subregion_overlap(&s->container, 0xe000e010,
 496                                         &s->systickmem, 1);
 497     if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
 498         memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
 499                               &v7m_sysreg_ns_ops, &s->systickmem,
 500                               "v7m_systick_ns", 0xe0);
 501         memory_region_add_subregion_overlap(&s->container, 0xe002e010,
 502                                             &s->systick_ns_mem, 1);
 503     }
 504
 505     /* If the CPU has RAS support, create the RAS register block */
 506     if (cpu_isar_feature(aa32_ras, s->cpu)) {
 507         object_initialize_child(OBJECT(dev), "armv7m-ras",
 508                                 &s->ras, TYPE_ARMV7M_RAS);
 509         sbd = SYS_BUS_DEVICE(&s->ras);
 510         if (!sysbus_realize(sbd, errp)) {
 511             return;
 512         }
 513         memory_region_add_subregion_overlap(&s->container, 0xe0005000,
 514                                             sysbus_mmio_get_region(sbd, 0), 1);
 515     }
 516
 517     for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
 518         if (s->enable_bitband) {
 519             Object *obj = OBJECT(&s->bitband[i]);
 520             sbd = SYS_BUS_DEVICE(&s->bitband[i]);
 521
 522             if (!object_property_set_int(obj, "base",
 523                                          bitband_input_addr[i], errp)) {
 524                 return;
 525             }
 526             object_property_set_link(obj, "source-memory",
 527                                      OBJECT(s->board_memory), &error_abort);
 528             if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) {
 529                 return;
 530             }
 531
 532             memory_region_add_subregion(&s->container, bitband_output_addr[i],
 533                                         sysbus_mmio_get_region(sbd, 0));
 534         } else {
 535             object_unparent(OBJECT(&s->bitband[i]));
 536         }
 537     }
 538 }
 539
 540 static Property armv7m_properties[] = {
 541     DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
 542     DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
 543                      MemoryRegion *),
 544     DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
 545     DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
 546     DEFINE_PROP_UINT32("init-nsvtor", ARMv7MState, init_nsvtor, 0),
 547     DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
 548     DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off,
 549                      false),
 550     DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
 551     DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
 552     DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
 553     DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
 554     DEFINE_PROP_END_OF_LIST(),
 555 };
 556
 557 static const VMStateDescription vmstate_armv7m = {
 558     .name = "armv7m",
 559     .version_id = 1,
 560     .minimum_version_id = 1,
 561     .fields = (VMStateField[]) {
 562         VMSTATE_CLOCK(refclk, ARMv7MState),
 563         VMSTATE_CLOCK(cpuclk, ARMv7MState),
 564         VMSTATE_END_OF_LIST()
 565     }
 566 };
 567
 568 static void armv7m_class_init(ObjectClass *klass, void *data)
 569 {
 570     DeviceClass *dc = DEVICE_CLASS(klass);
 571
 572     dc->realize = armv7m_realize;
 573     dc->vmsd = &vmstate_armv7m;
 574     device_class_set_props(dc, armv7m_properties);
 575 }
 576
 577 static const TypeInfo armv7m_info = {
 578     .name = TYPE_ARMV7M,
 579     .parent = TYPE_SYS_BUS_DEVICE,
 580     .instance_size = sizeof(ARMv7MState),
 581     .instance_init = armv7m_instance_init,
 582     .class_init = armv7m_class_init,
 583 };
 584
 585 static void armv7m_reset(void *opaque)
 586 {
 587     ARMCPU *cpu = opaque;
 588
 589     cpu_reset(CPU(cpu));
 590 }
 591
 592 void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename,
 593                         hwaddr mem_base, int mem_size)
 594 {
 595     ssize_t image_size;
 596     uint64_t entry;
 597     AddressSpace *as;
 598     int asidx;
 599     CPUState *cs = CPU(cpu);
 600
 601     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 602         asidx = ARMASIdx_S;
 603     } else {
 604         asidx = ARMASIdx_NS;
 605     }
 606     as = cpu_get_address_space(cs, asidx);
 607
 608     if (kernel_filename) {
 609         image_size = load_elf_as(kernel_filename, NULL, NULL, NULL,
 610                                  &entry, NULL, NULL,
 611                                  NULL, 0, EM_ARM, 1, 0, as);
 612         if (image_size < 0) {
 613             image_size = load_image_targphys_as(kernel_filename, mem_base,
 614                                                 mem_size, as);
 615         }
 616         if (image_size < 0) {
 617             error_report("Could not load kernel '%s'", kernel_filename);
 618             exit(1);
 619         }
 620     }
 621
 622     /* CPU objects (unlike devices) are not automatically reset on system
 623      * reset, so we must always register a handler to do so. Unlike
 624      * A-profile CPUs, we don't need to do anything special in the
 625      * handler to arrange that it starts correctly.
 626      * This is arguably the wrong place to do this, but it matches the
 627      * way A-profile does it. Note that this means that every M profile
 628      * board must call this function!
 629      */
 630     qemu_register_reset(armv7m_reset, cpu);
 631 }
 632
 633 static Property bitband_properties[] = {
 634     DEFINE_PROP_UINT32("base", BitBandState, base, 0),
 635     DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
 636                      TYPE_MEMORY_REGION, MemoryRegion *),
 637     DEFINE_PROP_END_OF_LIST(),
 638 };
 639
 640 static void bitband_class_init(ObjectClass *klass, void *data)
 641 {
 642     DeviceClass *dc = DEVICE_CLASS(klass);
 643
 644     dc->realize = bitband_realize;
 645     device_class_set_props(dc, bitband_properties);
 646 }
 647
 648 static const TypeInfo bitband_info = {
 649     .name          = TYPE_BITBAND,
 650     .parent        = TYPE_SYS_BUS_DEVICE,
 651     .instance_size = sizeof(BitBandState),
 652     .instance_init = bitband_init,
 653     .class_init    = bitband_class_init,
 654 };
 655
 656 static void armv7m_register_types(void)
 657 {
 658     type_register_static(&bitband_info);
 659     type_register_static(&armv7m_info);
 660 }
 661
 662 type_init(armv7m_register_types)