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1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "cpu.h"
15 #include "exec/address-spaces.h"
16 #include "hw/arm/boot.h"
17 #include "hw/arm/aspeed.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/i2c/smbus_eeprom.h"
20 #include "hw/misc/pca9552.h"
21 #include "hw/misc/tmp105.h"
22 #include "hw/misc/led.h"
23 #include "hw/qdev-properties.h"
24 #include "sysemu/block-backend.h"
25 #include "hw/loader.h"
26 #include "qemu/error-report.h"
27 #include "qemu/units.h"
28
29 static struct arm_boot_info aspeed_board_binfo = {
30 .board_id = -1, /* device-tree-only board */
31 };
32
33 struct AspeedMachineState {
34 /* Private */
35 MachineState parent_obj;
36 /* Public */
37
38 AspeedSoCState soc;
39 MemoryRegion ram_container;
40 MemoryRegion max_ram;
41 bool mmio_exec;
42 char *fmc_model;
43 char *spi_model;
44 };
45
46 /* Palmetto hardware value: 0x120CE416 */
47 #define PALMETTO_BMC_HW_STRAP1 ( \
48 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
49 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
50 SCU_AST2400_HW_STRAP_ACPI_DIS | \
51 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
52 SCU_HW_STRAP_VGA_CLASS_CODE | \
53 SCU_HW_STRAP_LPC_RESET_PIN | \
54 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
55 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
56 SCU_HW_STRAP_SPI_WIDTH | \
57 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
58 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
59
60 /* TODO: Find the actual hardware value */
61 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
62 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
63 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
64 SCU_AST2400_HW_STRAP_ACPI_DIS | \
65 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
66 SCU_HW_STRAP_VGA_CLASS_CODE | \
67 SCU_HW_STRAP_LPC_RESET_PIN | \
68 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
69 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
70 SCU_HW_STRAP_SPI_WIDTH | \
71 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
72 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
73
74 /* AST2500 evb hardware value: 0xF100C2E6 */
75 #define AST2500_EVB_HW_STRAP1 (( \
76 AST2500_HW_STRAP1_DEFAULTS | \
77 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
78 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
79 SCU_AST2500_HW_STRAP_UART_DEBUG | \
80 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
81 SCU_HW_STRAP_MAC1_RGMII | \
82 SCU_HW_STRAP_MAC0_RGMII) & \
83 ~SCU_HW_STRAP_2ND_BOOT_WDT)
84
85 /* Romulus hardware value: 0xF10AD206 */
86 #define ROMULUS_BMC_HW_STRAP1 ( \
87 AST2500_HW_STRAP1_DEFAULTS | \
88 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
89 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
90 SCU_AST2500_HW_STRAP_UART_DEBUG | \
91 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
92 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
93 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
94
95 /* Sonorapass hardware value: 0xF100D216 */
96 #define SONORAPASS_BMC_HW_STRAP1 ( \
97 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
98 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
99 SCU_AST2500_HW_STRAP_UART_DEBUG | \
100 SCU_AST2500_HW_STRAP_RESERVED28 | \
101 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
102 SCU_HW_STRAP_VGA_CLASS_CODE | \
103 SCU_HW_STRAP_LPC_RESET_PIN | \
104 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
105 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
106 SCU_HW_STRAP_VGA_BIOS_ROM | \
107 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
108 SCU_AST2500_HW_STRAP_RESERVED1)
109
110 /* Swift hardware value: 0xF11AD206 */
111 #define SWIFT_BMC_HW_STRAP1 ( \
112 AST2500_HW_STRAP1_DEFAULTS | \
113 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
114 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
115 SCU_AST2500_HW_STRAP_UART_DEBUG | \
116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
117 SCU_H_PLL_BYPASS_EN | \
118 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
119 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
120
121 #define G220A_BMC_HW_STRAP1 ( \
122 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
123 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
124 SCU_AST2500_HW_STRAP_UART_DEBUG | \
125 SCU_AST2500_HW_STRAP_RESERVED28 | \
126 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
127 SCU_HW_STRAP_2ND_BOOT_WDT | \
128 SCU_HW_STRAP_VGA_CLASS_CODE | \
129 SCU_HW_STRAP_LPC_RESET_PIN | \
130 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
131 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
132 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
133 SCU_AST2500_HW_STRAP_RESERVED1)
134
135 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
136 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
137
138 /* AST2600 evb hardware value */
139 #define AST2600_EVB_HW_STRAP1 0x000000C0
140 #define AST2600_EVB_HW_STRAP2 0x00000003
141
142 /* Tacoma hardware value */
143 #define TACOMA_BMC_HW_STRAP1 0x00000000
144 #define TACOMA_BMC_HW_STRAP2 0x00000040
145
146 /*
147 * The max ram region is for firmwares that scan the address space
148 * with load/store to guess how much RAM the SoC has.
149 */
150 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
151 {
152 return 0;
153 }
154
155 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
156 unsigned size)
157 {
158 /* Discard writes */
159 }
160
161 static const MemoryRegionOps max_ram_ops = {
162 .read = max_ram_read,
163 .write = max_ram_write,
164 .endianness = DEVICE_NATIVE_ENDIAN,
165 };
166
167 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
168 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
169 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
170 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
171 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
172 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
173 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
174
175 static void aspeed_write_smpboot(ARMCPU *cpu,
176 const struct arm_boot_info *info)
177 {
178 static const uint32_t poll_mailbox_ready[] = {
179 /*
180 * r2 = per-cpu go sign value
181 * r1 = AST_SMP_MBOX_FIELD_ENTRY
182 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
183 */
184 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
185 0xe21000ff, /* ands r0, r0, #255 */
186 0xe59f201c, /* ldr r2, [pc, #28] */
187 0xe1822000, /* orr r2, r2, r0 */
188
189 0xe59f1018, /* ldr r1, [pc, #24] */
190 0xe59f0018, /* ldr r0, [pc, #24] */
191
192 0xe320f002, /* wfe */
193 0xe5904000, /* ldr r4, [r0] */
194 0xe1520004, /* cmp r2, r4 */
195 0x1afffffb, /* bne <wfe> */
196 0xe591f000, /* ldr pc, [r1] */
197 AST_SMP_MBOX_GOSIGN,
198 AST_SMP_MBOX_FIELD_ENTRY,
199 AST_SMP_MBOX_FIELD_GOSIGN,
200 };
201
202 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
203 sizeof(poll_mailbox_ready),
204 info->smp_loader_start);
205 }
206
207 static void aspeed_reset_secondary(ARMCPU *cpu,
208 const struct arm_boot_info *info)
209 {
210 AddressSpace *as = arm_boot_address_space(cpu, info);
211 CPUState *cs = CPU(cpu);
212
213 /* info->smp_bootreg_addr */
214 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
215 MEMTXATTRS_UNSPECIFIED, NULL);
216 cpu_set_pc(cs, info->smp_loader_start);
217 }
218
219 #define FIRMWARE_ADDR 0x0
220
221 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
222 Error **errp)
223 {
224 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
225 uint8_t *storage;
226 int64_t size;
227
228 /* The block backend size should have already been 'validated' by
229 * the creation of the m25p80 object.
230 */
231 size = blk_getlength(blk);
232 if (size <= 0) {
233 error_setg(errp, "failed to get flash size");
234 return;
235 }
236
237 if (rom_size > size) {
238 rom_size = size;
239 }
240
241 storage = g_new0(uint8_t, rom_size);
242 if (blk_pread(blk, 0, storage, rom_size) < 0) {
243 error_setg(errp, "failed to read the initial flash content");
244 return;
245 }
246
247 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
248 g_free(storage);
249 }
250
251 static void aspeed_board_init_flashes(AspeedSMCState *s,
252 const char *flashtype)
253 {
254 int i ;
255
256 for (i = 0; i < s->num_cs; ++i) {
257 AspeedSMCFlash *fl = &s->flashes[i];
258 DriveInfo *dinfo = drive_get_next(IF_MTD);
259 qemu_irq cs_line;
260
261 fl->flash = qdev_new(flashtype);
262 if (dinfo) {
263 qdev_prop_set_drive(fl->flash, "drive",
264 blk_by_legacy_dinfo(dinfo));
265 }
266 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
267
268 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
269 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
270 }
271 }
272
273 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
274 {
275 DeviceState *card;
276
277 if (!dinfo) {
278 return;
279 }
280 card = qdev_new(TYPE_SD_CARD);
281 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
282 &error_fatal);
283 qdev_realize_and_unref(card,
284 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
285 &error_fatal);
286 }
287
288 static void aspeed_machine_init(MachineState *machine)
289 {
290 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
291 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
292 AspeedSoCClass *sc;
293 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
294 ram_addr_t max_ram_size;
295 int i;
296 NICInfo *nd = &nd_table[0];
297
298 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
299 4 * GiB);
300 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
301
302 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
303
304 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
305
306 /*
307 * This will error out if isize is not supported by memory controller.
308 */
309 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
310 &error_fatal);
311
312 for (i = 0; i < sc->macs_num; i++) {
313 if ((amc->macs_mask & (1 << i)) && nd->used) {
314 qemu_check_nic_model(nd, TYPE_FTGMAC100);
315 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
316 nd++;
317 }
318 }
319
320 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
321 &error_abort);
322 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
323 &error_abort);
324 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
325 &error_abort);
326 object_property_set_link(OBJECT(&bmc->soc), "dram",
327 OBJECT(&bmc->ram_container), &error_abort);
328 if (machine->kernel_filename) {
329 /*
330 * When booting with a -kernel command line there is no u-boot
331 * that runs to unlock the SCU. In this case set the default to
332 * be unlocked as the kernel expects
333 */
334 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
335 ASPEED_SCU_PROT_KEY, &error_abort);
336 }
337 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
338
339 memory_region_add_subregion(get_system_memory(),
340 sc->memmap[ASPEED_DEV_SDRAM],
341 &bmc->ram_container);
342
343 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
344 &error_abort);
345 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
346 "max_ram", max_ram_size - machine->ram_size);
347 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
348
349 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
350 bmc->fmc_model : amc->fmc_model);
351 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ?
352 bmc->spi_model : amc->spi_model);
353
354 /* Install first FMC flash content as a boot rom. */
355 if (drive0) {
356 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
357 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
358
359 /*
360 * create a ROM region using the default mapping window size of
361 * the flash module. The window size is 64MB for the AST2400
362 * SoC and 128MB for the AST2500 SoC, which is twice as big as
363 * needed by the flash modules of the Aspeed machines.
364 */
365 if (ASPEED_MACHINE(machine)->mmio_exec) {
366 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
367 &fl->mmio, 0, fl->size);
368 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
369 boot_rom);
370 } else {
371 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
372 fl->size, &error_abort);
373 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
374 boot_rom);
375 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
376 }
377 }
378
379 if (machine->kernel_filename && sc->num_cpus > 1) {
380 /* With no u-boot we must set up a boot stub for the secondary CPU */
381 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
382 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
383 0x80, &error_abort);
384 memory_region_add_subregion(get_system_memory(),
385 AST_SMP_MAILBOX_BASE, smpboot);
386
387 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
388 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
389 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
390 }
391
392 aspeed_board_binfo.ram_size = machine->ram_size;
393 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
394 aspeed_board_binfo.nb_cpus = sc->num_cpus;
395
396 if (amc->i2c_init) {
397 amc->i2c_init(bmc);
398 }
399
400 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
401 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
402 }
403
404 if (bmc->soc.emmc.num_slots) {
405 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
406 }
407
408 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
409 }
410
411 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
412 {
413 AspeedSoCState *soc = &bmc->soc;
414 DeviceState *dev;
415 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
416
417 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
418 * enough to provide basic RTC features. Alarms will be missing */
419 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
420
421 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
422 eeprom_buf);
423
424 /* add a TMP423 temperature sensor */
425 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
426 "tmp423", 0x4c));
427 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
428 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
429 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
430 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
431 }
432
433 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
434 {
435 AspeedSoCState *soc = &bmc->soc;
436 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
437
438 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
439 eeprom_buf);
440
441 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
442 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
443 TYPE_TMP105, 0x4d);
444
445 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
446 * plugged on the I2C bus header */
447 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
448 }
449
450 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
451 {
452 /* Start with some devices on our I2C busses */
453 ast2500_evb_i2c_init(bmc);
454 }
455
456 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
457 {
458 AspeedSoCState *soc = &bmc->soc;
459
460 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
461 * good enough */
462 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
463 }
464
465 static void swift_bmc_i2c_init(AspeedMachineState *bmc)
466 {
467 AspeedSoCState *soc = &bmc->soc;
468
469 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
470
471 /* The swift board expects a TMP275 but a TMP105 is compatible */
472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
473 /* The swift board expects a pca9551 but a pca9552 is compatible */
474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
475
476 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
477 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
478 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
479
480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
481 /* The swift board expects a pca9539 but a pca9552 is compatible */
482 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
483
484 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
485 /* The swift board expects a pca9539 but a pca9552 is compatible */
486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
487 0x74);
488
489 /* The swift board expects a TMP275 but a TMP105 is compatible */
490 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
491 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
492 }
493
494 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
495 {
496 AspeedSoCState *soc = &bmc->soc;
497
498 /* bus 2 : */
499 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
500 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
501 /* bus 2 : pca9546 @ 0x73 */
502
503 /* bus 3 : pca9548 @ 0x70 */
504
505 /* bus 4 : */
506 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
507 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
508 eeprom4_54);
509 /* PCA9539 @ 0x76, but PCA9552 is compatible */
510 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
511 /* PCA9539 @ 0x77, but PCA9552 is compatible */
512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
513
514 /* bus 6 : */
515 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
516 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
517 /* bus 6 : pca9546 @ 0x73 */
518
519 /* bus 8 : */
520 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
521 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
522 eeprom8_56);
523 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
524 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
525 /* bus 8 : adc128d818 @ 0x1d */
526 /* bus 8 : adc128d818 @ 0x1f */
527
528 /*
529 * bus 13 : pca9548 @ 0x71
530 * - channel 3:
531 * - tmm421 @ 0x4c
532 * - tmp421 @ 0x4e
533 * - tmp421 @ 0x4f
534 */
535
536 }
537
538 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
539 {
540 static const struct {
541 unsigned gpio_id;
542 LEDColor color;
543 const char *description;
544 bool gpio_polarity;
545 } pca1_leds[] = {
546 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
547 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
548 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
549 };
550 AspeedSoCState *soc = &bmc->soc;
551 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
552 DeviceState *dev;
553 LEDState *led;
554
555 /* Bus 3: TODO bmp280@77 */
556 /* Bus 3: TODO max31785@52 */
557 /* Bus 3: TODO dps310@76 */
558 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
559 qdev_prop_set_string(dev, "description", "pca1");
560 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
561 aspeed_i2c_get_bus(&soc->i2c, 3),
562 &error_fatal);
563
564 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
565 led = led_create_simple(OBJECT(bmc),
566 pca1_leds[i].gpio_polarity,
567 pca1_leds[i].color,
568 pca1_leds[i].description);
569 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
570 qdev_get_gpio_in(DEVICE(led), 0));
571 }
572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
573 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
574
575 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
576 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
577 0x4a);
578
579 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
580 * good enough */
581 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
582
583 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
584 eeprom_buf);
585 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
586 qdev_prop_set_string(dev, "description", "pca0");
587 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
588 aspeed_i2c_get_bus(&soc->i2c, 11),
589 &error_fatal);
590 /* Bus 11: TODO ucd90160@64 */
591 }
592
593 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
594 {
595 AspeedSoCState *soc = &bmc->soc;
596 DeviceState *dev;
597
598 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
599 "emc1413", 0x4c));
600 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
601 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
602 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
603
604 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
605 "emc1413", 0x4c));
606 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
607 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
608 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
609
610 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
611 "emc1413", 0x4c));
612 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
613 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
614 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
615
616 static uint8_t eeprom_buf[2 * 1024] = {
617 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
618 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
619 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
620 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
621 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
622 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
623 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
624 };
625 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
626 eeprom_buf);
627 }
628
629 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
630 {
631 return ASPEED_MACHINE(obj)->mmio_exec;
632 }
633
634 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
635 {
636 ASPEED_MACHINE(obj)->mmio_exec = value;
637 }
638
639 static void aspeed_machine_instance_init(Object *obj)
640 {
641 ASPEED_MACHINE(obj)->mmio_exec = false;
642 }
643
644 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
645 {
646 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
647 return g_strdup(bmc->fmc_model);
648 }
649
650 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
651 {
652 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
653
654 g_free(bmc->fmc_model);
655 bmc->fmc_model = g_strdup(value);
656 }
657
658 static char *aspeed_get_spi_model(Object *obj, Error **errp)
659 {
660 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
661 return g_strdup(bmc->spi_model);
662 }
663
664 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
665 {
666 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
667
668 g_free(bmc->spi_model);
669 bmc->spi_model = g_strdup(value);
670 }
671
672 static void aspeed_machine_class_props_init(ObjectClass *oc)
673 {
674 object_class_property_add_bool(oc, "execute-in-place",
675 aspeed_get_mmio_exec,
676 aspeed_set_mmio_exec);
677 object_class_property_set_description(oc, "execute-in-place",
678 "boot directly from CE0 flash device");
679
680 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
681 aspeed_set_fmc_model);
682 object_class_property_set_description(oc, "fmc-model",
683 "Change the FMC Flash model");
684 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
685 aspeed_set_spi_model);
686 object_class_property_set_description(oc, "spi-model",
687 "Change the SPI Flash model");
688 }
689
690 static int aspeed_soc_num_cpus(const char *soc_name)
691 {
692 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
693 return sc->num_cpus;
694 }
695
696 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
697 {
698 MachineClass *mc = MACHINE_CLASS(oc);
699 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
700
701 mc->init = aspeed_machine_init;
702 mc->no_floppy = 1;
703 mc->no_cdrom = 1;
704 mc->no_parallel = 1;
705 mc->default_ram_id = "ram";
706 amc->macs_mask = ASPEED_MAC0_ON;
707
708 aspeed_machine_class_props_init(oc);
709 }
710
711 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
712 {
713 MachineClass *mc = MACHINE_CLASS(oc);
714 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
715
716 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
717 amc->soc_name = "ast2400-a1";
718 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
719 amc->fmc_model = "n25q256a";
720 amc->spi_model = "mx25l25635e";
721 amc->num_cs = 1;
722 amc->i2c_init = palmetto_bmc_i2c_init;
723 mc->default_ram_size = 256 * MiB;
724 mc->default_cpus = mc->min_cpus = mc->max_cpus =
725 aspeed_soc_num_cpus(amc->soc_name);
726 };
727
728 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
729 void *data)
730 {
731 MachineClass *mc = MACHINE_CLASS(oc);
732 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
733
734 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
735 amc->soc_name = "ast2400-a1";
736 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
737 amc->fmc_model = "mx25l25635e";
738 amc->spi_model = "mx25l25635e";
739 amc->num_cs = 1;
740 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
741 amc->i2c_init = palmetto_bmc_i2c_init;
742 mc->default_ram_size = 256 * MiB;
743 }
744
745 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
746 {
747 MachineClass *mc = MACHINE_CLASS(oc);
748 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
749
750 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
751 amc->soc_name = "ast2500-a1";
752 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
753 amc->fmc_model = "w25q256";
754 amc->spi_model = "mx25l25635e";
755 amc->num_cs = 1;
756 amc->i2c_init = ast2500_evb_i2c_init;
757 mc->default_ram_size = 512 * MiB;
758 mc->default_cpus = mc->min_cpus = mc->max_cpus =
759 aspeed_soc_num_cpus(amc->soc_name);
760 };
761
762 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
763 {
764 MachineClass *mc = MACHINE_CLASS(oc);
765 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
766
767 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
768 amc->soc_name = "ast2500-a1";
769 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
770 amc->fmc_model = "n25q256a";
771 amc->spi_model = "mx66l1g45g";
772 amc->num_cs = 2;
773 amc->i2c_init = romulus_bmc_i2c_init;
774 mc->default_ram_size = 512 * MiB;
775 mc->default_cpus = mc->min_cpus = mc->max_cpus =
776 aspeed_soc_num_cpus(amc->soc_name);
777 };
778
779 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
780 {
781 MachineClass *mc = MACHINE_CLASS(oc);
782 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
783
784 mc->desc = "OCP SonoraPass BMC (ARM1176)";
785 amc->soc_name = "ast2500-a1";
786 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
787 amc->fmc_model = "mx66l1g45g";
788 amc->spi_model = "mx66l1g45g";
789 amc->num_cs = 2;
790 amc->i2c_init = sonorapass_bmc_i2c_init;
791 mc->default_ram_size = 512 * MiB;
792 mc->default_cpus = mc->min_cpus = mc->max_cpus =
793 aspeed_soc_num_cpus(amc->soc_name);
794 };
795
796 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
797 {
798 MachineClass *mc = MACHINE_CLASS(oc);
799 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
800
801 mc->desc = "OpenPOWER Swift BMC (ARM1176)";
802 amc->soc_name = "ast2500-a1";
803 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
804 amc->fmc_model = "mx66l1g45g";
805 amc->spi_model = "mx66l1g45g";
806 amc->num_cs = 2;
807 amc->i2c_init = swift_bmc_i2c_init;
808 mc->default_ram_size = 512 * MiB;
809 mc->default_cpus = mc->min_cpus = mc->max_cpus =
810 aspeed_soc_num_cpus(amc->soc_name);
811 };
812
813 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
814 {
815 MachineClass *mc = MACHINE_CLASS(oc);
816 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
817
818 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
819 amc->soc_name = "ast2500-a1";
820 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
821 amc->fmc_model = "mx25l25635e";
822 amc->spi_model = "mx66l1g45g";
823 amc->num_cs = 2;
824 amc->i2c_init = witherspoon_bmc_i2c_init;
825 mc->default_ram_size = 512 * MiB;
826 mc->default_cpus = mc->min_cpus = mc->max_cpus =
827 aspeed_soc_num_cpus(amc->soc_name);
828 };
829
830 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
831 {
832 MachineClass *mc = MACHINE_CLASS(oc);
833 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
834
835 mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
836 amc->soc_name = "ast2600-a1";
837 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
838 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
839 amc->fmc_model = "w25q512jv";
840 amc->spi_model = "mx66u51235f";
841 amc->num_cs = 1;
842 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
843 amc->i2c_init = ast2600_evb_i2c_init;
844 mc->default_ram_size = 1 * GiB;
845 mc->default_cpus = mc->min_cpus = mc->max_cpus =
846 aspeed_soc_num_cpus(amc->soc_name);
847 };
848
849 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
850 {
851 MachineClass *mc = MACHINE_CLASS(oc);
852 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
853
854 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
855 amc->soc_name = "ast2600-a1";
856 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
857 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
858 amc->fmc_model = "mx66l1g45g";
859 amc->spi_model = "mx66l1g45g";
860 amc->num_cs = 2;
861 amc->macs_mask = ASPEED_MAC2_ON;
862 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
863 mc->default_ram_size = 1 * GiB;
864 mc->default_cpus = mc->min_cpus = mc->max_cpus =
865 aspeed_soc_num_cpus(amc->soc_name);
866 };
867
868 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
869 {
870 MachineClass *mc = MACHINE_CLASS(oc);
871 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
872
873 mc->desc = "Bytedance G220A BMC (ARM1176)";
874 amc->soc_name = "ast2500-a1";
875 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
876 amc->fmc_model = "n25q512a";
877 amc->spi_model = "mx25l25635e";
878 amc->num_cs = 2;
879 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON;
880 amc->i2c_init = g220a_bmc_i2c_init;
881 mc->default_ram_size = 1024 * MiB;
882 mc->default_cpus = mc->min_cpus = mc->max_cpus =
883 aspeed_soc_num_cpus(amc->soc_name);
884 };
885
886 static const TypeInfo aspeed_machine_types[] = {
887 {
888 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
889 .parent = TYPE_ASPEED_MACHINE,
890 .class_init = aspeed_machine_palmetto_class_init,
891 }, {
892 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
893 .parent = TYPE_ASPEED_MACHINE,
894 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
895 }, {
896 .name = MACHINE_TYPE_NAME("ast2500-evb"),
897 .parent = TYPE_ASPEED_MACHINE,
898 .class_init = aspeed_machine_ast2500_evb_class_init,
899 }, {
900 .name = MACHINE_TYPE_NAME("romulus-bmc"),
901 .parent = TYPE_ASPEED_MACHINE,
902 .class_init = aspeed_machine_romulus_class_init,
903 }, {
904 .name = MACHINE_TYPE_NAME("swift-bmc"),
905 .parent = TYPE_ASPEED_MACHINE,
906 .class_init = aspeed_machine_swift_class_init,
907 }, {
908 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
909 .parent = TYPE_ASPEED_MACHINE,
910 .class_init = aspeed_machine_sonorapass_class_init,
911 }, {
912 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
913 .parent = TYPE_ASPEED_MACHINE,
914 .class_init = aspeed_machine_witherspoon_class_init,
915 }, {
916 .name = MACHINE_TYPE_NAME("ast2600-evb"),
917 .parent = TYPE_ASPEED_MACHINE,
918 .class_init = aspeed_machine_ast2600_evb_class_init,
919 }, {
920 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
921 .parent = TYPE_ASPEED_MACHINE,
922 .class_init = aspeed_machine_tacoma_class_init,
923 }, {
924 .name = MACHINE_TYPE_NAME("g220a-bmc"),
925 .parent = TYPE_ASPEED_MACHINE,
926 .class_init = aspeed_machine_g220a_class_init,
927 }, {
928 .name = TYPE_ASPEED_MACHINE,
929 .parent = TYPE_MACHINE,
930 .instance_size = sizeof(AspeedMachineState),
931 .instance_init = aspeed_machine_instance_init,
932 .class_size = sizeof(AspeedMachineClass),
933 .class_init = aspeed_machine_class_init,
934 .abstract = true,
935 }
936 };
937
938 DEFINE_TYPES(aspeed_machine_types)
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