hw/arm/fsl-imx31.c

   1 /*
   2  * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX31 SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx31.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the
  10  *  Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "hw/arm/fsl-imx31.h"
  26 #include "sysemu/sysemu.h"
  27 #include "exec/address-spaces.h"
  28 #include "hw/qdev-properties.h"
  29 #include "chardev/char.h"
  30
  31 static void fsl_imx31_init(Object *obj)
  32 {
  33     FslIMX31State *s = FSL_IMX31(obj);
  34     int i;
  35
  36     object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136"));
  37
  38     object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
  39
  40     object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX31_CCM);
  41
  42     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  43         object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
  44     }
  45
  46     object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX31_GPT);
  47
  48     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
  49         object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
  50     }
  51
  52     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
  53         object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
  54     }
  55
  56     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
  57         object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
  58     }
  59
  60     object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
  61 }
  62
  63 static void fsl_imx31_realize(DeviceState *dev, Error **errp)
  64 {
  65     FslIMX31State *s = FSL_IMX31(dev);
  66     uint16_t i;
  67     Error *err = NULL;
  68
  69     if (!qdev_realize(DEVICE(&s->cpu), NULL, &err)) {
  70         error_propagate(errp, err);
  71         return;
  72     }
  73
  74     if (!sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err)) {
  75         error_propagate(errp, err);
  76         return;
  77     }
  78     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
  79     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
  80                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
  81     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
  82                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
  83
  84     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err)) {
  85         error_propagate(errp, err);
  86         return;
  87     }
  88     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
  89
  90     /* Initialize all UARTS */
  91     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  92         static const struct {
  93             hwaddr addr;
  94             unsigned int irq;
  95         } serial_table[FSL_IMX31_NUM_UARTS] = {
  96             { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
  97             { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
  98         };
  99
 100         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 101
 102         if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err)) {
 103             error_propagate(errp, err);
 104             return;
 105         }
 106
 107         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 108         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 109                            qdev_get_gpio_in(DEVICE(&s->avic),
 110                                             serial_table[i].irq));
 111     }
 112
 113     s->gpt.ccm = IMX_CCM(&s->ccm);
 114
 115     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err)) {
 116         error_propagate(errp, err);
 117         return;
 118     }
 119
 120     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
 121     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
 122                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
 123
 124     /* Initialize all EPIT timers */
 125     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
 126         static const struct {
 127             hwaddr addr;
 128             unsigned int irq;
 129         } epit_table[FSL_IMX31_NUM_EPITS] = {
 130             { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
 131             { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
 132         };
 133
 134         s->epit[i].ccm = IMX_CCM(&s->ccm);
 135
 136         if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err)) {
 137             error_propagate(errp, err);
 138             return;
 139         }
 140
 141         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 142         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 143                            qdev_get_gpio_in(DEVICE(&s->avic),
 144                                             epit_table[i].irq));
 145     }
 146
 147     /* Initialize all I2C */
 148     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
 149         static const struct {
 150             hwaddr addr;
 151             unsigned int irq;
 152         } i2c_table[FSL_IMX31_NUM_I2CS] = {
 153             { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
 154             { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
 155             { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
 156         };
 157
 158         /* Initialize the I2C */
 159         if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err)) {
 160             error_propagate(errp, err);
 161             return;
 162         }
 163         /* Map I2C memory */
 164         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 165         /* Connect I2C IRQ to PIC */
 166         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 167                            qdev_get_gpio_in(DEVICE(&s->avic),
 168                                             i2c_table[i].irq));
 169     }
 170
 171     /* Initialize all GPIOs */
 172     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
 173         static const struct {
 174             hwaddr addr;
 175             unsigned int irq;
 176         } gpio_table[FSL_IMX31_NUM_GPIOS] = {
 177             { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
 178             { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
 179             { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
 180         };
 181
 182         object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
 183                                  &error_abort);
 184         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err)) {
 185             error_propagate(errp, err);
 186             return;
 187         }
 188         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 189         /* Connect GPIO IRQ to PIC */
 190         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 191                            qdev_get_gpio_in(DEVICE(&s->avic),
 192                                             gpio_table[i].irq));
 193     }
 194
 195     /* Watchdog */
 196     sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
 197     sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
 198
 199     /* On a real system, the first 16k is a `secure boot rom' */
 200     memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
 201                            FSL_IMX31_SECURE_ROM_SIZE, &err);
 202     if (err) {
 203         error_propagate(errp, err);
 204         return;
 205     }
 206     memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
 207                                 &s->secure_rom);
 208
 209     /* There is also a 16k ROM */
 210     memory_region_init_rom(&s->rom, OBJECT(dev), "imx31.rom",
 211                            FSL_IMX31_ROM_SIZE, &err);
 212     if (err) {
 213         error_propagate(errp, err);
 214         return;
 215     }
 216     memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
 217                                 &s->rom);
 218
 219     /* initialize internal RAM (16 KB) */
 220     memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
 221                            &err);
 222     if (err) {
 223         error_propagate(errp, err);
 224         return;
 225     }
 226     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
 227                                 &s->iram);
 228
 229     /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
 230     memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx31.iram_alias",
 231                              &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
 232     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
 233                                 &s->iram_alias);
 234 }
 235
 236 static void fsl_imx31_class_init(ObjectClass *oc, void *data)
 237 {
 238     DeviceClass *dc = DEVICE_CLASS(oc);
 239
 240     dc->realize = fsl_imx31_realize;
 241     dc->desc = "i.MX31 SOC";
 242     /*
 243      * Reason: uses serial_hds in realize and the kzm board does not
 244      * support multiple CPUs
 245      */
 246     dc->user_creatable = false;
 247 }
 248
 249 static const TypeInfo fsl_imx31_type_info = {
 250     .name = TYPE_FSL_IMX31,
 251     .parent = TYPE_DEVICE,
 252     .instance_size = sizeof(FslIMX31State),
 253     .instance_init = fsl_imx31_init,
 254     .class_init = fsl_imx31_class_init,
 255 };
 256
 257 static void fsl_imx31_register_types(void)
 258 {
 259     type_register_static(&fsl_imx31_type_info);
 260 }
 261
 262 type_init(fsl_imx31_register_types)