hw/arm/stm32f205_soc.c

   1 /*
   2  * STM32F205 SoC
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu/module.h"
  28 #include "hw/arm/boot.h"
  29 #include "exec/address-spaces.h"
  30 #include "hw/arm/stm32f205_soc.h"
  31 #include "hw/qdev-properties.h"
  32 #include "sysemu/sysemu.h"
  33
  34 /* At the moment only Timer 2 to 5 are modelled */
  35 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
  36     0x40000800, 0x40000C00 };
  37 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
  38     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
  39 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
  40     0x40012200 };
  41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
  42     0x40003C00 };
  43
  44 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
  45 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
  46 #define ADC_IRQ 18
  47 static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
  48
  49 static void stm32f205_soc_initfn(Object *obj)
  50 {
  51     STM32F205State *s = STM32F205_SOC(obj);
  52     int i;
  53
  54     object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
  55
  56     object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);
  57
  58     for (i = 0; i < STM_NUM_USARTS; i++) {
  59         object_initialize_child(obj, "usart[*]", &s->usart[i],
  60                                 TYPE_STM32F2XX_USART);
  61     }
  62
  63     for (i = 0; i < STM_NUM_TIMERS; i++) {
  64         object_initialize_child(obj, "timer[*]", &s->timer[i],
  65                                 TYPE_STM32F2XX_TIMER);
  66     }
  67
  68     s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
  69
  70     for (i = 0; i < STM_NUM_ADCS; i++) {
  71         object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
  72     }
  73
  74     for (i = 0; i < STM_NUM_SPIS; i++) {
  75         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
  76     }
  77 }
  78
  79 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
  80 {
  81     STM32F205State *s = STM32F205_SOC(dev_soc);
  82     DeviceState *dev, *armv7m;
  83     SysBusDevice *busdev;
  84     Error *err = NULL;
  85     int i;
  86
  87     MemoryRegion *system_memory = get_system_memory();
  88     MemoryRegion *sram = g_new(MemoryRegion, 1);
  89     MemoryRegion *flash = g_new(MemoryRegion, 1);
  90     MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
  91
  92     memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash",
  93                            FLASH_SIZE, &error_fatal);
  94     memory_region_init_alias(flash_alias, OBJECT(dev_soc),
  95                              "STM32F205.flash.alias", flash, 0, FLASH_SIZE);
  96
  97     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
  98     memory_region_add_subregion(system_memory, 0, flash_alias);
  99
 100     memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
 101                            &error_fatal);
 102     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 103
 104     armv7m = DEVICE(&s->armv7m);
 105     qdev_prop_set_uint32(armv7m, "num-irq", 96);
 106     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 107     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 108     object_property_set_link(OBJECT(&s->armv7m), "memory",
 109                              OBJECT(get_system_memory()), &error_abort);
 110     if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err)) {
 111         error_propagate(errp, err);
 112         return;
 113     }
 114
 115     /* System configuration controller */
 116     dev = DEVICE(&s->syscfg);
 117     if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err)) {
 118         error_propagate(errp, err);
 119         return;
 120     }
 121     busdev = SYS_BUS_DEVICE(dev);
 122     sysbus_mmio_map(busdev, 0, 0x40013800);
 123     sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
 124
 125     /* Attach UART (uses USART registers) and USART controllers */
 126     for (i = 0; i < STM_NUM_USARTS; i++) {
 127         dev = DEVICE(&(s->usart[i]));
 128         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 129         if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err)) {
 130             error_propagate(errp, err);
 131             return;
 132         }
 133         busdev = SYS_BUS_DEVICE(dev);
 134         sysbus_mmio_map(busdev, 0, usart_addr[i]);
 135         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
 136     }
 137
 138     /* Timer 2 to 5 */
 139     for (i = 0; i < STM_NUM_TIMERS; i++) {
 140         dev = DEVICE(&(s->timer[i]));
 141         qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
 142         if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err)) {
 143             error_propagate(errp, err);
 144             return;
 145         }
 146         busdev = SYS_BUS_DEVICE(dev);
 147         sysbus_mmio_map(busdev, 0, timer_addr[i]);
 148         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
 149     }
 150
 151     /* ADC 1 to 3 */
 152     object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS,
 153                             &error_abort);
 154     if (!qdev_realize(DEVICE(s->adc_irqs), NULL, &err)) {
 155         error_propagate(errp, err);
 156         return;
 157     }
 158     qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
 159                           qdev_get_gpio_in(armv7m, ADC_IRQ));
 160
 161     for (i = 0; i < STM_NUM_ADCS; i++) {
 162         dev = DEVICE(&(s->adc[i]));
 163         if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err)) {
 164             error_propagate(errp, err);
 165             return;
 166         }
 167         busdev = SYS_BUS_DEVICE(dev);
 168         sysbus_mmio_map(busdev, 0, adc_addr[i]);
 169         sysbus_connect_irq(busdev, 0,
 170                            qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
 171     }
 172
 173     /* SPI 1 and 2 */
 174     for (i = 0; i < STM_NUM_SPIS; i++) {
 175         dev = DEVICE(&(s->spi[i]));
 176         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) {
 177             error_propagate(errp, err);
 178             return;
 179         }
 180         busdev = SYS_BUS_DEVICE(dev);
 181         sysbus_mmio_map(busdev, 0, spi_addr[i]);
 182         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
 183     }
 184 }
 185
 186 static Property stm32f205_soc_properties[] = {
 187     DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
 188     DEFINE_PROP_END_OF_LIST(),
 189 };
 190
 191 static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
 192 {
 193     DeviceClass *dc = DEVICE_CLASS(klass);
 194
 195     dc->realize = stm32f205_soc_realize;
 196     device_class_set_props(dc, stm32f205_soc_properties);
 197 }
 198
 199 static const TypeInfo stm32f205_soc_info = {
 200     .name          = TYPE_STM32F205_SOC,
 201     .parent        = TYPE_SYS_BUS_DEVICE,
 202     .instance_size = sizeof(STM32F205State),
 203     .instance_init = stm32f205_soc_initfn,
 204     .class_init    = stm32f205_soc_class_init,
 205 };
 206
 207 static void stm32f205_soc_types(void)
 208 {
 209     type_register_static(&stm32f205_soc_info);
 210 }
 211
 212 type_init(stm32f205_soc_types)