hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu/module.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "hw/boards.h"
  25 #include "exec/address-spaces.h"
  26 #include "sysemu/kvm.h"
  27 #include "sysemu/sysemu.h"
  28 #include "kvm_arm.h"
  29
  30 #define GIC_NUM_SPI_INTR 160
  31
  32 #define ARM_PHYS_TIMER_PPI  30
  33 #define ARM_VIRT_TIMER_PPI  27
  34 #define ARM_HYP_TIMER_PPI   26
  35 #define ARM_SEC_TIMER_PPI   29
  36 #define GIC_MAINTENANCE_PPI 25
  37
  38 #define GEM_REVISION        0x40070106
  39
  40 #define GIC_BASE_ADDR       0xf9000000
  41 #define GIC_DIST_ADDR       0xf9010000
  42 #define GIC_CPU_ADDR        0xf9020000
  43 #define GIC_VIFACE_ADDR     0xf9040000
  44 #define GIC_VCPU_ADDR       0xf9060000
  45
  46 #define SATA_INTR           133
  47 #define SATA_ADDR           0xFD0C0000
  48 #define SATA_NUM_PORTS      2
  49
  50 #define QSPI_ADDR           0xff0f0000
  51 #define LQSPI_ADDR          0xc0000000
  52 #define QSPI_IRQ            15
  53
  54 #define DP_ADDR             0xfd4a0000
  55 #define DP_IRQ              113
  56
  57 #define DPDMA_ADDR          0xfd4c0000
  58 #define DPDMA_IRQ           116
  59
  60 #define IPI_ADDR            0xFF300000
  61 #define IPI_IRQ             64
  62
  63 #define RTC_ADDR            0xffa60000
  64 #define RTC_IRQ             26
  65
  66 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
  67
  68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  69     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  70 };
  71
  72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  73     57, 59, 61, 63,
  74 };
  75
  76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  77     0xFF000000, 0xFF010000,
  78 };
  79
  80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  81     21, 22,
  82 };
  83
  84 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  85     0xFF160000, 0xFF170000,
  86 };
  87
  88 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  89     48, 49,
  90 };
  91
  92 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  93     0xFF040000, 0xFF050000,
  94 };
  95
  96 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  97     19, 20,
  98 };
  99
 100 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
 101     0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
 102     0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
 103 };
 104
 105 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
 106     124, 125, 126, 127, 128, 129, 130, 131
 107 };
 108
 109 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 110     0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
 111     0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
 112 };
 113
 114 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 115     77, 78, 79, 80, 81, 82, 83, 84
 116 };
 117
 118 typedef struct XlnxZynqMPGICRegion {
 119     int region_index;
 120     uint32_t address;
 121     uint32_t offset;
 122     bool virt;
 123 } XlnxZynqMPGICRegion;
 124
 125 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
 126     /* Distributor */
 127     {
 128         .region_index = 0,
 129         .address = GIC_DIST_ADDR,
 130         .offset = 0,
 131         .virt = false
 132     },
 133
 134     /* CPU interface */
 135     {
 136         .region_index = 1,
 137         .address = GIC_CPU_ADDR,
 138         .offset = 0,
 139         .virt = false
 140     },
 141     {
 142         .region_index = 1,
 143         .address = GIC_CPU_ADDR + 0x10000,
 144         .offset = 0x1000,
 145         .virt = false
 146     },
 147
 148     /* Virtual interface */
 149     {
 150         .region_index = 2,
 151         .address = GIC_VIFACE_ADDR,
 152         .offset = 0,
 153         .virt = true
 154     },
 155
 156     /* Virtual CPU interface */
 157     {
 158         .region_index = 3,
 159         .address = GIC_VCPU_ADDR,
 160         .offset = 0,
 161         .virt = true
 162     },
 163     {
 164         .region_index = 3,
 165         .address = GIC_VCPU_ADDR + 0x10000,
 166         .offset = 0x1000,
 167         .virt = true
 168     },
 169 };
 170
 171 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
 172 {
 173     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
 174 }
 175
 176 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
 177                                    const char *boot_cpu, Error **errp)
 178 {
 179     Error *err = NULL;
 180     int i;
 181     int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
 182                        XLNX_ZYNQMP_NUM_RPU_CPUS);
 183
 184     if (num_rpus <= 0) {
 185         /* Don't create rpu-cluster object if there's nothing to put in it */
 186         return;
 187     }
 188
 189     object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
 190                             TYPE_CPU_CLUSTER);
 191     qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
 192
 193     for (i = 0; i < num_rpus; i++) {
 194         char *name;
 195
 196         object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
 197                                 &s->rpu_cpu[i],
 198                                 ARM_CPU_TYPE_NAME("cortex-r5f"));
 199
 200         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 201         if (strcmp(name, boot_cpu)) {
 202             /* Secondary CPUs start in PSCI powered-down state */
 203             object_property_set_bool(OBJECT(&s->rpu_cpu[i]),
 204                                      "start-powered-off", true, &error_abort);
 205         } else {
 206             s->boot_cpu_ptr = &s->rpu_cpu[i];
 207         }
 208         g_free(name);
 209
 210         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true,
 211                                  &error_abort);
 212         if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, &err)) {
 213             error_propagate(errp, err);
 214             return;
 215         }
 216     }
 217
 218     qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
 219 }
 220
 221 static void xlnx_zynqmp_init(Object *obj)
 222 {
 223     MachineState *ms = MACHINE(qdev_get_machine());
 224     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 225     int i;
 226     int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 227
 228     object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
 229                             TYPE_CPU_CLUSTER);
 230     qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
 231
 232     for (i = 0; i < num_apus; i++) {
 233         object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
 234                                 &s->apu_cpu[i],
 235                                 ARM_CPU_TYPE_NAME("cortex-a53"));
 236     }
 237
 238     object_initialize_child(obj, "gic", &s->gic, gic_class_name());
 239
 240     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 241         object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
 242     }
 243
 244     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 245         object_initialize_child(obj, "uart[*]", &s->uart[i],
 246                                 TYPE_CADENCE_UART);
 247     }
 248
 249     object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
 250
 251     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 252         object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
 253                                 TYPE_SYSBUS_SDHCI);
 254     }
 255
 256     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 257         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
 258     }
 259
 260     object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
 261
 262     object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
 263
 264     object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
 265
 266     object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
 267
 268     object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
 269
 270     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 271         object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
 272     }
 273
 274     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 275         object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
 276     }
 277 }
 278
 279 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 280 {
 281     MachineState *ms = MACHINE(qdev_get_machine());
 282     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 283     MemoryRegion *system_memory = get_system_memory();
 284     uint8_t i;
 285     uint64_t ram_size;
 286     int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 287     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 288     ram_addr_t ddr_low_size, ddr_high_size;
 289     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 290     Error *err = NULL;
 291
 292     ram_size = memory_region_size(s->ddr_ram);
 293
 294     /* Create the DDR Memory Regions. User friendly checks should happen at
 295      * the board level
 296      */
 297     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 298         /* The RAM size is above the maximum available for the low DDR.
 299          * Create the high DDR memory region as well.
 300          */
 301         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 302         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 303         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 304
 305         memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
 306                                  "ddr-ram-high", s->ddr_ram, ddr_low_size,
 307                                  ddr_high_size);
 308         memory_region_add_subregion(get_system_memory(),
 309                                     XLNX_ZYNQMP_HIGH_RAM_START,
 310                                     &s->ddr_ram_high);
 311     } else {
 312         /* RAM must be non-zero */
 313         assert(ram_size);
 314         ddr_low_size = ram_size;
 315     }
 316
 317     memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
 318                              s->ddr_ram, 0, ddr_low_size);
 319     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 320
 321     /* Create the four OCM banks */
 322     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 323         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 324
 325         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 326                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 327         memory_region_add_subregion(get_system_memory(),
 328                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 329                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 330                                     &s->ocm_ram[i]);
 331
 332         g_free(ocm_name);
 333     }
 334
 335     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 336     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 337     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
 338     qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
 339     qdev_prop_set_bit(DEVICE(&s->gic),
 340                       "has-virtualization-extensions", s->virt);
 341
 342     qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
 343
 344     /* Realize APUs before realizing the GIC. KVM requires this.  */
 345     for (i = 0; i < num_apus; i++) {
 346         char *name;
 347
 348         object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit",
 349                                 QEMU_PSCI_CONDUIT_SMC, &error_abort);
 350
 351         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 352         if (strcmp(name, boot_cpu)) {
 353             /* Secondary CPUs start in PSCI powered-down state */
 354             object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 355                                      "start-powered-off", true, &error_abort);
 356         } else {
 357             s->boot_cpu_ptr = &s->apu_cpu[i];
 358         }
 359         g_free(name);
 360
 361         object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure,
 362                                  NULL);
 363         object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt,
 364                                  NULL);
 365         object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar",
 366                                 GIC_BASE_ADDR, &error_abort);
 367         object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count",
 368                                 num_apus, &error_abort);
 369         if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, &err)) {
 370             error_propagate(errp, err);
 371             return;
 372         }
 373     }
 374
 375     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err)) {
 376         error_propagate(errp, err);
 377         return;
 378     }
 379
 380     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 381     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 382         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 383         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 384         MemoryRegion *mr;
 385         uint32_t addr = r->address;
 386         int j;
 387
 388         if (r->virt && !s->virt) {
 389             continue;
 390         }
 391
 392         mr = sysbus_mmio_get_region(gic, r->region_index);
 393         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 394             MemoryRegion *alias = &s->gic_mr[i][j];
 395
 396             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 397                                      r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
 398             memory_region_add_subregion(system_memory, addr, alias);
 399
 400             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 401         }
 402     }
 403
 404     for (i = 0; i < num_apus; i++) {
 405         qemu_irq irq;
 406
 407         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 408                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 409                                             ARM_CPU_IRQ));
 410         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
 411                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 412                                             ARM_CPU_FIQ));
 413         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
 414                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 415                                             ARM_CPU_VIRQ));
 416         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
 417                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 418                                             ARM_CPU_VFIQ));
 419         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 420                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 421         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
 422         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 423                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 424         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
 425         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 426                                arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
 427         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
 428         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 429                                arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
 430         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
 431
 432         if (s->virt) {
 433             irq = qdev_get_gpio_in(DEVICE(&s->gic),
 434                                    arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
 435             sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
 436         }
 437     }
 438
 439     if (s->has_rpu) {
 440         info_report("The 'has_rpu' property is no longer required, to use the "
 441                     "RPUs just use -smp 6.");
 442     }
 443
 444     xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
 445     if (err) {
 446         error_propagate(errp, err);
 447         return;
 448     }
 449
 450     if (!s->boot_cpu_ptr) {
 451         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 452         return;
 453     }
 454
 455     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 456         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 457     }
 458
 459     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 460         NICInfo *nd = &nd_table[i];
 461
 462         if (nd->used) {
 463             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 464             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 465         }
 466         object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
 467                                 &error_abort);
 468         object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
 469                                 &error_abort);
 470         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), &err)) {
 471             error_propagate(errp, err);
 472             return;
 473         }
 474         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 475         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 476                            gic_spi[gem_intr[i]]);
 477     }
 478
 479     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 480         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 481         if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err)) {
 482             error_propagate(errp, err);
 483             return;
 484         }
 485         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 486         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 487                            gic_spi[uart_intr[i]]);
 488     }
 489
 490     object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
 491                             &error_abort);
 492     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err)) {
 493         error_propagate(errp, err);
 494         return;
 495     }
 496
 497     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 498     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 499
 500     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 501         char *bus_name;
 502         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
 503         Object *sdhci = OBJECT(&s->sdhci[i]);
 504
 505         /* Compatible with:
 506          * - SD Host Controller Specification Version 3.00
 507          * - SDIO Specification Version 3.0
 508          * - eMMC Specification Version 4.51
 509          */
 510         if (!object_property_set_uint(sdhci, "sd-spec-version", 3, &err)) {
 511             error_propagate(errp, err);
 512             return;
 513         }
 514         if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
 515                                       &err)) {
 516             error_propagate(errp, err);
 517             return;
 518         }
 519         if (!object_property_set_uint(sdhci, "uhs", UHS_I, &err)) {
 520             error_propagate(errp, err);
 521             return;
 522         }
 523         if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), &err)) {
 524             error_propagate(errp, err);
 525             return;
 526         }
 527         sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
 528         sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
 529
 530         /* Alias controller SD bus to the SoC itself */
 531         bus_name = g_strdup_printf("sd-bus%d", i);
 532         object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
 533         g_free(bus_name);
 534     }
 535
 536     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 537         gchar *bus_name;
 538
 539         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) {
 540             error_propagate(errp, err);
 541             return;
 542         }
 543
 544         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 545         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 546                            gic_spi[spi_intr[i]]);
 547
 548         /* Alias controller SPI bus to the SoC itself */
 549         bus_name = g_strdup_printf("spi%d", i);
 550         object_property_add_alias(OBJECT(s), bus_name,
 551                                   OBJECT(&s->spi[i]), "spi0");
 552         g_free(bus_name);
 553     }
 554
 555     if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), &err)) {
 556         error_propagate(errp, err);
 557         return;
 558     }
 559     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
 560     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
 561     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
 562
 563     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
 564         gchar *bus_name;
 565         gchar *target_bus;
 566
 567         /* Alias controller SPI bus to the SoC itself */
 568         bus_name = g_strdup_printf("qspi%d", i);
 569         target_bus = g_strdup_printf("spi%d", i);
 570         object_property_add_alias(OBJECT(s), bus_name,
 571                                   OBJECT(&s->qspi), target_bus);
 572         g_free(bus_name);
 573         g_free(target_bus);
 574     }
 575
 576     if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), &err)) {
 577         error_propagate(errp, err);
 578         return;
 579     }
 580     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 581     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 582
 583     if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), &err)) {
 584         error_propagate(errp, err);
 585         return;
 586     }
 587     object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma),
 588                              &error_abort);
 589     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 590     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 591
 592     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), &err)) {
 593         error_propagate(errp, err);
 594         return;
 595     }
 596     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
 597     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
 598
 599     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err)) {
 600         error_propagate(errp, err);
 601         return;
 602     }
 603     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
 604     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
 605
 606     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 607         if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
 608                                       &err)) {
 609             error_propagate(errp, err);
 610             return;
 611         }
 612         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), &err)) {
 613             error_propagate(errp, err);
 614             return;
 615         }
 616
 617         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
 618         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
 619                            gic_spi[gdma_ch_intr[i]]);
 620     }
 621
 622     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 623         if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), &err)) {
 624             error_propagate(errp, err);
 625             return;
 626         }
 627
 628         sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
 629         sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
 630                            gic_spi[adma_ch_intr[i]]);
 631     }
 632 }
 633
 634 static Property xlnx_zynqmp_props[] = {
 635     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 636     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 637     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
 638     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
 639     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
 640                      MemoryRegion *),
 641     DEFINE_PROP_END_OF_LIST()
 642 };
 643
 644 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 645 {
 646     DeviceClass *dc = DEVICE_CLASS(oc);
 647
 648     device_class_set_props(dc, xlnx_zynqmp_props);
 649     dc->realize = xlnx_zynqmp_realize;
 650     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 651     dc->user_creatable = false;
 652 }
 653
 654 static const TypeInfo xlnx_zynqmp_type_info = {
 655     .name = TYPE_XLNX_ZYNQMP,
 656     .parent = TYPE_DEVICE,
 657     .instance_size = sizeof(XlnxZynqMPState),
 658     .instance_init = xlnx_zynqmp_init,
 659     .class_init = xlnx_zynqmp_class_init,
 660 };
 661
 662 static void xlnx_zynqmp_register_types(void)
 663 {
 664     type_register_static(&xlnx_zynqmp_type_info);
 665 }
 666
 667 type_init(xlnx_zynqmp_register_types)