2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "hw/arm/xlnx-zynqmp.h"
22 #include "hw/intc/arm_gic_common.h"
23 #include "hw/misc/unimp.h"
24 #include "hw/boards.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/sysemu.h"
28 #include "target/arm/cpu-qom.h"
30 #define GIC_NUM_SPI_INTR 160
32 #define ARM_PHYS_TIMER_PPI 30
33 #define ARM_VIRT_TIMER_PPI 27
34 #define ARM_HYP_TIMER_PPI 26
35 #define ARM_SEC_TIMER_PPI 29
36 #define GIC_MAINTENANCE_PPI 25
38 #define GEM_REVISION 0x40070106
40 #define GIC_BASE_ADDR 0xf9000000
41 #define GIC_DIST_ADDR 0xf9010000
42 #define GIC_CPU_ADDR 0xf9020000
43 #define GIC_VIFACE_ADDR 0xf9040000
44 #define GIC_VCPU_ADDR 0xf9060000
47 #define SATA_ADDR 0xFD0C0000
48 #define SATA_NUM_PORTS 2
50 #define QSPI_ADDR 0xff0f0000
51 #define LQSPI_ADDR 0xc0000000
53 #define QSPI_DMA_ADDR 0xff0f0800
54 #define NUM_QSPI_IRQ_LINES 2
56 #define CRF_ADDR 0xfd1a0000
59 /* Serializer/Deserializer. */
60 #define SERDES_ADDR 0xfd400000
61 #define SERDES_SIZE 0x20000
63 #define DP_ADDR 0xfd4a0000
66 #define DPDMA_ADDR 0xfd4c0000
67 #define DPDMA_IRQ 0x7a
69 #define APU_ADDR 0xfd5c0000
72 #define TTC0_ADDR 0xFF110000
75 #define IPI_ADDR 0xFF300000
78 #define RTC_ADDR 0xffa60000
81 #define BBRAM_ADDR 0xffcd0000
84 #define EFUSE_ADDR 0xffcc0000
87 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
89 static const uint64_t gem_addr
[XLNX_ZYNQMP_NUM_GEMS
] = {
90 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
93 static const int gem_intr
[XLNX_ZYNQMP_NUM_GEMS
] = {
97 static const uint64_t uart_addr
[XLNX_ZYNQMP_NUM_UARTS
] = {
98 0xFF000000, 0xFF010000,
101 static const int uart_intr
[XLNX_ZYNQMP_NUM_UARTS
] = {
105 static const uint64_t can_addr
[XLNX_ZYNQMP_NUM_CAN
] = {
106 0xFF060000, 0xFF070000,
109 static const int can_intr
[XLNX_ZYNQMP_NUM_CAN
] = {
113 static const uint64_t sdhci_addr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
114 0xFF160000, 0xFF170000,
117 static const int sdhci_intr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
121 static const uint64_t spi_addr
[XLNX_ZYNQMP_NUM_SPIS
] = {
122 0xFF040000, 0xFF050000,
125 static const int spi_intr
[XLNX_ZYNQMP_NUM_SPIS
] = {
129 static const uint64_t gdma_ch_addr
[XLNX_ZYNQMP_NUM_GDMA_CH
] = {
130 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
131 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
134 static const int gdma_ch_intr
[XLNX_ZYNQMP_NUM_GDMA_CH
] = {
135 124, 125, 126, 127, 128, 129, 130, 131
138 static const uint64_t adma_ch_addr
[XLNX_ZYNQMP_NUM_ADMA_CH
] = {
139 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
140 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
143 static const int adma_ch_intr
[XLNX_ZYNQMP_NUM_ADMA_CH
] = {
144 77, 78, 79, 80, 81, 82, 83, 84
147 static const uint64_t usb_addr
[XLNX_ZYNQMP_NUM_USB
] = {
148 0xFE200000, 0xFE300000
151 static const int usb_intr
[XLNX_ZYNQMP_NUM_USB
] = {
155 typedef struct XlnxZynqMPGICRegion
{
160 } XlnxZynqMPGICRegion
;
162 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions
[] = {
166 .address
= GIC_DIST_ADDR
,
174 .address
= GIC_CPU_ADDR
,
180 .address
= GIC_CPU_ADDR
+ 0x10000,
185 /* Virtual interface */
188 .address
= GIC_VIFACE_ADDR
,
193 /* Virtual CPU interface */
196 .address
= GIC_VCPU_ADDR
,
202 .address
= GIC_VCPU_ADDR
+ 0x10000,
208 static inline int arm_gic_ppi_index(int cpu_nr
, int ppi_index
)
210 return GIC_NUM_SPI_INTR
+ cpu_nr
* GIC_INTERNAL
+ ppi_index
;
213 static void xlnx_zynqmp_create_rpu(MachineState
*ms
, XlnxZynqMPState
*s
,
214 const char *boot_cpu
, Error
**errp
)
217 int num_rpus
= MIN((int)(ms
->smp
.cpus
- XLNX_ZYNQMP_NUM_APU_CPUS
),
218 XLNX_ZYNQMP_NUM_RPU_CPUS
);
221 /* Don't create rpu-cluster object if there's nothing to put in it */
225 object_initialize_child(OBJECT(s
), "rpu-cluster", &s
->rpu_cluster
,
227 qdev_prop_set_uint32(DEVICE(&s
->rpu_cluster
), "cluster-id", 1);
229 for (i
= 0; i
< num_rpus
; i
++) {
232 object_initialize_child(OBJECT(&s
->rpu_cluster
), "rpu-cpu[*]",
234 ARM_CPU_TYPE_NAME("cortex-r5f"));
236 name
= object_get_canonical_path_component(OBJECT(&s
->rpu_cpu
[i
]));
237 if (strcmp(name
, boot_cpu
)) {
239 * Secondary CPUs start in powered-down state.
241 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]),
242 "start-powered-off", true, &error_abort
);
244 s
->boot_cpu_ptr
= &s
->rpu_cpu
[i
];
247 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), "reset-hivecs", true,
249 if (!qdev_realize(DEVICE(&s
->rpu_cpu
[i
]), NULL
, errp
)) {
254 qdev_realize(DEVICE(&s
->rpu_cluster
), NULL
, &error_fatal
);
257 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState
*s
, qemu_irq
*gic
)
261 object_initialize_child_with_props(OBJECT(s
), "bbram", &s
->bbram
,
262 sizeof(s
->bbram
), TYPE_XLNX_BBRAM
,
266 sbd
= SYS_BUS_DEVICE(&s
->bbram
);
268 sysbus_realize(sbd
, &error_fatal
);
269 sysbus_mmio_map(sbd
, 0, BBRAM_ADDR
);
270 sysbus_connect_irq(sbd
, 0, gic
[BBRAM_IRQ
]);
273 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState
*s
, qemu_irq
*gic
)
275 Object
*bits
= OBJECT(&s
->efuse
);
276 Object
*ctrl
= OBJECT(&s
->efuse_ctrl
);
279 object_initialize_child(OBJECT(s
), "efuse-ctrl", &s
->efuse_ctrl
,
280 TYPE_XLNX_ZYNQMP_EFUSE
);
282 object_initialize_child_with_props(ctrl
, "xlnx-efuse@0", bits
,
284 TYPE_XLNX_EFUSE
, &error_abort
,
286 "efuse-size", "2048",
289 qdev_realize(DEVICE(bits
), NULL
, &error_abort
);
290 object_property_set_link(ctrl
, "efuse", bits
, &error_abort
);
292 sbd
= SYS_BUS_DEVICE(ctrl
);
293 sysbus_realize(sbd
, &error_abort
);
294 sysbus_mmio_map(sbd
, 0, EFUSE_ADDR
);
295 sysbus_connect_irq(sbd
, 0, gic
[EFUSE_IRQ
]);
298 static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState
*s
, qemu_irq
*gic
)
303 object_initialize_child(OBJECT(s
), "apu-ctrl", &s
->apu_ctrl
,
304 TYPE_XLNX_ZYNQMP_APU_CTRL
);
305 sbd
= SYS_BUS_DEVICE(&s
->apu_ctrl
);
307 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
308 g_autofree gchar
*name
= g_strdup_printf("cpu%d", i
);
310 object_property_set_link(OBJECT(&s
->apu_ctrl
), name
,
311 OBJECT(&s
->apu_cpu
[i
]), &error_abort
);
314 sysbus_realize(sbd
, &error_fatal
);
315 sysbus_mmio_map(sbd
, 0, APU_ADDR
);
316 sysbus_connect_irq(sbd
, 0, gic
[APU_IRQ
]);
319 static void xlnx_zynqmp_create_crf(XlnxZynqMPState
*s
, qemu_irq
*gic
)
323 object_initialize_child(OBJECT(s
), "crf", &s
->crf
, TYPE_XLNX_ZYNQMP_CRF
);
324 sbd
= SYS_BUS_DEVICE(&s
->crf
);
326 sysbus_realize(sbd
, &error_fatal
);
327 sysbus_mmio_map(sbd
, 0, CRF_ADDR
);
328 sysbus_connect_irq(sbd
, 0, gic
[CRF_IRQ
]);
331 static void xlnx_zynqmp_create_ttc(XlnxZynqMPState
*s
, qemu_irq
*gic
)
336 for (i
= 0; i
< XLNX_ZYNQMP_NUM_TTC
; i
++) {
337 object_initialize_child(OBJECT(s
), "ttc[*]", &s
->ttc
[i
],
339 sbd
= SYS_BUS_DEVICE(&s
->ttc
[i
]);
341 sysbus_realize(sbd
, &error_fatal
);
342 sysbus_mmio_map(sbd
, 0, TTC0_ADDR
+ i
* 0x10000);
343 for (irq
= 0; irq
< 3; irq
++) {
344 sysbus_connect_irq(sbd
, irq
, gic
[TTC0_IRQ
+ i
* 3 + irq
]);
349 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState
*s
)
351 static const struct UnimpInfo
{
355 } unimp_areas
[ARRAY_SIZE(s
->mr_unimp
)] = {
356 { .name
= "serdes", SERDES_ADDR
, SERDES_SIZE
},
360 for (nr
= 0; nr
< ARRAY_SIZE(unimp_areas
); nr
++) {
361 const struct UnimpInfo
*info
= &unimp_areas
[nr
];
362 DeviceState
*dev
= qdev_new(TYPE_UNIMPLEMENTED_DEVICE
);
363 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
365 assert(info
->name
&& info
->base
&& info
->size
> 0);
366 qdev_prop_set_string(dev
, "name", info
->name
);
367 qdev_prop_set_uint64(dev
, "size", info
->size
);
368 object_property_add_child(OBJECT(s
), info
->name
, OBJECT(dev
));
370 sysbus_realize_and_unref(sbd
, &error_fatal
);
371 sysbus_mmio_map(sbd
, 0, info
->base
);
375 static void xlnx_zynqmp_init(Object
*obj
)
377 MachineState
*ms
= MACHINE(qdev_get_machine());
378 XlnxZynqMPState
*s
= XLNX_ZYNQMP(obj
);
380 int num_apus
= MIN(ms
->smp
.cpus
, XLNX_ZYNQMP_NUM_APU_CPUS
);
382 object_initialize_child(obj
, "apu-cluster", &s
->apu_cluster
,
384 qdev_prop_set_uint32(DEVICE(&s
->apu_cluster
), "cluster-id", 0);
386 for (i
= 0; i
< num_apus
; i
++) {
387 object_initialize_child(OBJECT(&s
->apu_cluster
), "apu-cpu[*]",
389 ARM_CPU_TYPE_NAME("cortex-a53"));
392 object_initialize_child(obj
, "gic", &s
->gic
, gic_class_name());
394 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
395 object_initialize_child(obj
, "gem[*]", &s
->gem
[i
], TYPE_CADENCE_GEM
);
398 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
399 object_initialize_child(obj
, "uart[*]", &s
->uart
[i
],
403 for (i
= 0; i
< XLNX_ZYNQMP_NUM_CAN
; i
++) {
404 object_initialize_child(obj
, "can[*]", &s
->can
[i
],
405 TYPE_XLNX_ZYNQMP_CAN
);
408 object_initialize_child(obj
, "sata", &s
->sata
, TYPE_SYSBUS_AHCI
);
410 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
411 object_initialize_child(obj
, "sdhci[*]", &s
->sdhci
[i
],
415 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
416 object_initialize_child(obj
, "spi[*]", &s
->spi
[i
], TYPE_XILINX_SPIPS
);
419 object_initialize_child(obj
, "qspi", &s
->qspi
, TYPE_XLNX_ZYNQMP_QSPIPS
);
421 object_initialize_child(obj
, "xxxdp", &s
->dp
, TYPE_XLNX_DP
);
423 object_initialize_child(obj
, "dp-dma", &s
->dpdma
, TYPE_XLNX_DPDMA
);
425 object_initialize_child(obj
, "ipi", &s
->ipi
, TYPE_XLNX_ZYNQMP_IPI
);
427 object_initialize_child(obj
, "rtc", &s
->rtc
, TYPE_XLNX_ZYNQMP_RTC
);
429 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GDMA_CH
; i
++) {
430 object_initialize_child(obj
, "gdma[*]", &s
->gdma
[i
], TYPE_XLNX_ZDMA
);
433 for (i
= 0; i
< XLNX_ZYNQMP_NUM_ADMA_CH
; i
++) {
434 object_initialize_child(obj
, "adma[*]", &s
->adma
[i
], TYPE_XLNX_ZDMA
);
437 object_initialize_child(obj
, "qspi-dma", &s
->qspi_dma
, TYPE_XLNX_CSU_DMA
);
438 object_initialize_child(obj
, "qspi-irq-orgate",
439 &s
->qspi_irq_orgate
, TYPE_OR_IRQ
);
441 for (i
= 0; i
< XLNX_ZYNQMP_NUM_USB
; i
++) {
442 object_initialize_child(obj
, "usb[*]", &s
->usb
[i
], TYPE_USB_DWC3
);
446 static void xlnx_zynqmp_realize(DeviceState
*dev
, Error
**errp
)
448 MachineState
*ms
= MACHINE(qdev_get_machine());
449 XlnxZynqMPState
*s
= XLNX_ZYNQMP(dev
);
450 MemoryRegion
*system_memory
= get_system_memory();
453 int num_apus
= MIN(ms
->smp
.cpus
, XLNX_ZYNQMP_NUM_APU_CPUS
);
454 const char *boot_cpu
= s
->boot_cpu
? s
->boot_cpu
: "apu-cpu[0]";
455 ram_addr_t ddr_low_size
, ddr_high_size
;
456 qemu_irq gic_spi
[GIC_NUM_SPI_INTR
];
459 ram_size
= memory_region_size(s
->ddr_ram
);
462 * Create the DDR Memory Regions. User friendly checks should happen at
465 if (ram_size
> XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
) {
467 * The RAM size is above the maximum available for the low DDR.
468 * Create the high DDR memory region as well.
470 assert(ram_size
<= XLNX_ZYNQMP_MAX_RAM_SIZE
);
471 ddr_low_size
= XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
472 ddr_high_size
= ram_size
- XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
474 memory_region_init_alias(&s
->ddr_ram_high
, OBJECT(dev
),
475 "ddr-ram-high", s
->ddr_ram
, ddr_low_size
,
477 memory_region_add_subregion(get_system_memory(),
478 XLNX_ZYNQMP_HIGH_RAM_START
,
481 /* RAM must be non-zero */
483 ddr_low_size
= ram_size
;
486 memory_region_init_alias(&s
->ddr_ram_low
, OBJECT(dev
), "ddr-ram-low",
487 s
->ddr_ram
, 0, ddr_low_size
);
488 memory_region_add_subregion(get_system_memory(), 0, &s
->ddr_ram_low
);
490 /* Create the four OCM banks */
491 for (i
= 0; i
< XLNX_ZYNQMP_NUM_OCM_BANKS
; i
++) {
492 char *ocm_name
= g_strdup_printf("zynqmp.ocm_ram_bank_%d", i
);
494 memory_region_init_ram(&s
->ocm_ram
[i
], NULL
, ocm_name
,
495 XLNX_ZYNQMP_OCM_RAM_SIZE
, &error_fatal
);
496 memory_region_add_subregion(get_system_memory(),
497 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS
+
498 i
* XLNX_ZYNQMP_OCM_RAM_SIZE
,
504 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-irq", GIC_NUM_SPI_INTR
+ 32);
505 qdev_prop_set_uint32(DEVICE(&s
->gic
), "revision", 2);
506 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-cpu", num_apus
);
507 qdev_prop_set_bit(DEVICE(&s
->gic
), "has-security-extensions", s
->secure
);
508 qdev_prop_set_bit(DEVICE(&s
->gic
),
509 "has-virtualization-extensions", s
->virt
);
511 qdev_realize(DEVICE(&s
->apu_cluster
), NULL
, &error_fatal
);
513 /* Realize APUs before realizing the GIC. KVM requires this. */
514 for (i
= 0; i
< num_apus
; i
++) {
517 name
= object_get_canonical_path_component(OBJECT(&s
->apu_cpu
[i
]));
518 if (strcmp(name
, boot_cpu
)) {
520 * Secondary CPUs start in powered-down state.
522 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]),
523 "start-powered-off", true, &error_abort
);
525 s
->boot_cpu_ptr
= &s
->apu_cpu
[i
];
528 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), "has_el3", s
->secure
,
530 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), "has_el2", s
->virt
,
532 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), "reset-cbar",
533 GIC_BASE_ADDR
, &error_abort
);
534 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), "core-count",
535 num_apus
, &error_abort
);
536 if (!qdev_realize(DEVICE(&s
->apu_cpu
[i
]), NULL
, errp
)) {
541 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gic
), errp
)) {
545 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions
) == XLNX_ZYNQMP_GIC_REGIONS
);
546 for (i
= 0; i
< XLNX_ZYNQMP_GIC_REGIONS
; i
++) {
547 SysBusDevice
*gic
= SYS_BUS_DEVICE(&s
->gic
);
548 const XlnxZynqMPGICRegion
*r
= &xlnx_zynqmp_gic_regions
[i
];
550 uint32_t addr
= r
->address
;
553 if (r
->virt
&& !s
->virt
) {
557 mr
= sysbus_mmio_get_region(gic
, r
->region_index
);
558 for (j
= 0; j
< XLNX_ZYNQMP_GIC_ALIASES
; j
++) {
559 MemoryRegion
*alias
= &s
->gic_mr
[i
][j
];
561 memory_region_init_alias(alias
, OBJECT(s
), "zynqmp-gic-alias", mr
,
562 r
->offset
, XLNX_ZYNQMP_GIC_REGION_SIZE
);
563 memory_region_add_subregion(system_memory
, addr
, alias
);
565 addr
+= XLNX_ZYNQMP_GIC_REGION_SIZE
;
569 for (i
= 0; i
< num_apus
; i
++) {
572 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
,
573 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
575 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
+ num_apus
,
576 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
578 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
+ num_apus
* 2,
579 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
581 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
+ num_apus
* 3,
582 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
584 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
585 arm_gic_ppi_index(i
, ARM_PHYS_TIMER_PPI
));
586 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), GTIMER_PHYS
, irq
);
587 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
588 arm_gic_ppi_index(i
, ARM_VIRT_TIMER_PPI
));
589 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), GTIMER_VIRT
, irq
);
590 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
591 arm_gic_ppi_index(i
, ARM_HYP_TIMER_PPI
));
592 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), GTIMER_HYP
, irq
);
593 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
594 arm_gic_ppi_index(i
, ARM_SEC_TIMER_PPI
));
595 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), GTIMER_SEC
, irq
);
598 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
599 arm_gic_ppi_index(i
, GIC_MAINTENANCE_PPI
));
600 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
+ num_apus
* 4, irq
);
604 xlnx_zynqmp_create_rpu(ms
, s
, boot_cpu
, &err
);
606 error_propagate(errp
, err
);
610 if (!s
->boot_cpu_ptr
) {
611 error_setg(errp
, "ZynqMP Boot cpu %s not found", boot_cpu
);
615 for (i
= 0; i
< GIC_NUM_SPI_INTR
; i
++) {
616 gic_spi
[i
] = qdev_get_gpio_in(DEVICE(&s
->gic
), i
);
619 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
620 NICInfo
*nd
= &nd_table
[i
];
622 /* FIXME use qdev NIC properties instead of nd_table[] */
624 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
625 qdev_set_nic_properties(DEVICE(&s
->gem
[i
]), nd
);
627 object_property_set_int(OBJECT(&s
->gem
[i
]), "revision", GEM_REVISION
,
629 object_property_set_int(OBJECT(&s
->gem
[i
]), "phy-addr", 23,
631 object_property_set_int(OBJECT(&s
->gem
[i
]), "num-priority-queues", 2,
633 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gem
[i
]), errp
)) {
636 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
[i
]), 0, gem_addr
[i
]);
637 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
[i
]), 0,
638 gic_spi
[gem_intr
[i
]]);
641 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
642 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
643 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->uart
[i
]), errp
)) {
646 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, uart_addr
[i
]);
647 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
648 gic_spi
[uart_intr
[i
]]);
651 for (i
= 0; i
< XLNX_ZYNQMP_NUM_CAN
; i
++) {
652 object_property_set_int(OBJECT(&s
->can
[i
]), "ext_clk_freq",
653 XLNX_ZYNQMP_CAN_REF_CLK
, &error_abort
);
655 object_property_set_link(OBJECT(&s
->can
[i
]), "canbus",
656 OBJECT(s
->canbus
[i
]), &error_fatal
);
658 sysbus_realize(SYS_BUS_DEVICE(&s
->can
[i
]), &err
);
660 error_propagate(errp
, err
);
663 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->can
[i
]), 0, can_addr
[i
]);
664 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->can
[i
]), 0,
665 gic_spi
[can_intr
[i
]]);
668 object_property_set_int(OBJECT(&s
->sata
), "num-ports", SATA_NUM_PORTS
,
670 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sata
), errp
)) {
674 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, SATA_ADDR
);
675 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, gic_spi
[SATA_INTR
]);
677 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
679 SysBusDevice
*sbd
= SYS_BUS_DEVICE(&s
->sdhci
[i
]);
680 Object
*sdhci
= OBJECT(&s
->sdhci
[i
]);
684 * - SD Host Controller Specification Version 3.00
685 * - SDIO Specification Version 3.0
686 * - eMMC Specification Version 4.51
688 if (!object_property_set_uint(sdhci
, "sd-spec-version", 3, errp
)) {
691 if (!object_property_set_uint(sdhci
, "capareg", SDHCI_CAPABILITIES
,
695 if (!object_property_set_uint(sdhci
, "uhs", UHS_I
, errp
)) {
698 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci
), errp
)) {
701 sysbus_mmio_map(sbd
, 0, sdhci_addr
[i
]);
702 sysbus_connect_irq(sbd
, 0, gic_spi
[sdhci_intr
[i
]]);
704 /* Alias controller SD bus to the SoC itself */
705 bus_name
= g_strdup_printf("sd-bus%d", i
);
706 object_property_add_alias(OBJECT(s
), bus_name
, sdhci
, "sd-bus");
710 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
713 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), errp
)) {
717 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0, spi_addr
[i
]);
718 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
719 gic_spi
[spi_intr
[i
]]);
721 /* Alias controller SPI bus to the SoC itself */
722 bus_name
= g_strdup_printf("spi%d", i
);
723 object_property_add_alias(OBJECT(s
), bus_name
,
724 OBJECT(&s
->spi
[i
]), "spi0");
728 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->dp
), errp
)) {
731 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dp
), 0, DP_ADDR
);
732 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dp
), 0, gic_spi
[DP_IRQ
]);
734 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->dpdma
), errp
)) {
737 object_property_set_link(OBJECT(&s
->dp
), "dpdma", OBJECT(&s
->dpdma
),
739 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dpdma
), 0, DPDMA_ADDR
);
740 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dpdma
), 0, gic_spi
[DPDMA_IRQ
]);
742 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ipi
), errp
)) {
745 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ipi
), 0, IPI_ADDR
);
746 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ipi
), 0, gic_spi
[IPI_IRQ
]);
748 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->rtc
), errp
)) {
751 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, RTC_ADDR
);
752 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0, gic_spi
[RTC_IRQ
]);
754 xlnx_zynqmp_create_bbram(s
, gic_spi
);
755 xlnx_zynqmp_create_efuse(s
, gic_spi
);
756 xlnx_zynqmp_create_apu_ctrl(s
, gic_spi
);
757 xlnx_zynqmp_create_crf(s
, gic_spi
);
758 xlnx_zynqmp_create_ttc(s
, gic_spi
);
759 xlnx_zynqmp_create_unimp_mmio(s
);
761 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GDMA_CH
; i
++) {
762 if (!object_property_set_uint(OBJECT(&s
->gdma
[i
]), "bus-width", 128,
766 if (!object_property_set_link(OBJECT(&s
->gdma
[i
]), "dma",
767 OBJECT(system_memory
), errp
)) {
770 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gdma
[i
]), errp
)) {
774 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gdma
[i
]), 0, gdma_ch_addr
[i
]);
775 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gdma
[i
]), 0,
776 gic_spi
[gdma_ch_intr
[i
]]);
779 for (i
= 0; i
< XLNX_ZYNQMP_NUM_ADMA_CH
; i
++) {
780 if (!object_property_set_link(OBJECT(&s
->adma
[i
]), "dma",
781 OBJECT(system_memory
), errp
)) {
784 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->adma
[i
]), errp
)) {
788 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->adma
[i
]), 0, adma_ch_addr
[i
]);
789 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->adma
[i
]), 0,
790 gic_spi
[adma_ch_intr
[i
]]);
793 object_property_set_int(OBJECT(&s
->qspi_irq_orgate
),
794 "num-lines", NUM_QSPI_IRQ_LINES
, &error_fatal
);
795 qdev_realize(DEVICE(&s
->qspi_irq_orgate
), NULL
, &error_fatal
);
796 qdev_connect_gpio_out(DEVICE(&s
->qspi_irq_orgate
), 0, gic_spi
[QSPI_IRQ
]);
798 if (!object_property_set_link(OBJECT(&s
->qspi_dma
), "dma",
799 OBJECT(system_memory
), errp
)) {
802 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->qspi_dma
), errp
)) {
806 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi_dma
), 0, QSPI_DMA_ADDR
);
807 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->qspi_dma
), 0,
808 qdev_get_gpio_in(DEVICE(&s
->qspi_irq_orgate
), 0));
810 if (!object_property_set_link(OBJECT(&s
->qspi
), "stream-connected-dma",
811 OBJECT(&s
->qspi_dma
), errp
)) {
814 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->qspi
), errp
)) {
817 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi
), 0, QSPI_ADDR
);
818 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi
), 1, LQSPI_ADDR
);
819 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->qspi
), 0,
820 qdev_get_gpio_in(DEVICE(&s
->qspi_irq_orgate
), 1));
822 for (i
= 0; i
< XLNX_ZYNQMP_NUM_QSPI_BUS
; i
++) {
823 g_autofree gchar
*bus_name
= g_strdup_printf("qspi%d", i
);
824 g_autofree gchar
*target_bus
= g_strdup_printf("spi%d", i
);
826 /* Alias controller SPI bus to the SoC itself */
827 object_property_add_alias(OBJECT(s
), bus_name
,
828 OBJECT(&s
->qspi
), target_bus
);
831 for (i
= 0; i
< XLNX_ZYNQMP_NUM_USB
; i
++) {
832 if (!object_property_set_link(OBJECT(&s
->usb
[i
].sysbus_xhci
), "dma",
833 OBJECT(system_memory
), errp
)) {
837 qdev_prop_set_uint32(DEVICE(&s
->usb
[i
].sysbus_xhci
), "intrs", 4);
838 qdev_prop_set_uint32(DEVICE(&s
->usb
[i
].sysbus_xhci
), "slots", 2);
840 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->usb
[i
]), errp
)) {
844 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usb
[i
]), 0, usb_addr
[i
]);
845 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
].sysbus_xhci
), 0,
846 gic_spi
[usb_intr
[i
]]);
847 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
].sysbus_xhci
), 1,
848 gic_spi
[usb_intr
[i
] + 1]);
849 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
].sysbus_xhci
), 2,
850 gic_spi
[usb_intr
[i
] + 2]);
851 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
].sysbus_xhci
), 3,
852 gic_spi
[usb_intr
[i
] + 3]);
856 static Property xlnx_zynqmp_props
[] = {
857 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState
, boot_cpu
),
858 DEFINE_PROP_BOOL("secure", XlnxZynqMPState
, secure
, false),
859 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState
, virt
, false),
860 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState
, ddr_ram
, TYPE_MEMORY_REGION
,
862 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState
, canbus
[0], TYPE_CAN_BUS
,
864 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState
, canbus
[1], TYPE_CAN_BUS
,
866 DEFINE_PROP_END_OF_LIST()
869 static void xlnx_zynqmp_class_init(ObjectClass
*oc
, void *data
)
871 DeviceClass
*dc
= DEVICE_CLASS(oc
);
873 device_class_set_props(dc
, xlnx_zynqmp_props
);
874 dc
->realize
= xlnx_zynqmp_realize
;
875 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
876 dc
->user_creatable
= false;
879 static const TypeInfo xlnx_zynqmp_type_info
= {
880 .name
= TYPE_XLNX_ZYNQMP
,
881 .parent
= TYPE_DEVICE
,
882 .instance_size
= sizeof(XlnxZynqMPState
),
883 .instance_init
= xlnx_zynqmp_init
,
884 .class_init
= xlnx_zynqmp_class_init
,
887 static void xlnx_zynqmp_register_types(void)
889 type_register_static(&xlnx_zynqmp_type_info
);
892 type_init(xlnx_zynqmp_register_types
)