hw/cpu/a9mpcore.c

   1 /*
   2  * Cortex-A9MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2009 CodeSourcery.
   5  * Copyright (c) 2011 Linaro Limited.
   6  * Written by Paul Brook, Peter Maydell.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qapi/error.h"
  13 #include "qemu/module.h"
  14 #include "hw/cpu/a9mpcore.h"
  15 #include "hw/irq.h"
  16 #include "hw/qdev-properties.h"
  17 #include "hw/core/cpu.h"
  18
  19 #define A9_GIC_NUM_PRIORITY_BITS    5
  20
  21 static void a9mp_priv_set_irq(void *opaque, int irq, int level)
  22 {
  23     A9MPPrivState *s = (A9MPPrivState *)opaque;
  24
  25     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  26 }
  27
  28 static void a9mp_priv_initfn(Object *obj)
  29 {
  30     A9MPPrivState *s = A9MPCORE_PRIV(obj);
  31
  32     memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
  33     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
  34
  35     object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU);
  36
  37     object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
  38
  39     object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER);
  40
  41     object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
  42
  43     object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER);
  44 }
  45
  46 static void a9mp_priv_realize(DeviceState *dev, Error **errp)
  47 {
  48     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  49     A9MPPrivState *s = A9MPCORE_PRIV(dev);
  50     DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
  51     SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
  52                  *wdtbusdev;
  53     Error *err = NULL;
  54     int i;
  55     bool has_el3;
  56     Object *cpuobj;
  57
  58     scudev = DEVICE(&s->scu);
  59     qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
  60     if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err)) {
  61         error_propagate(errp, err);
  62         return;
  63     }
  64     scubusdev = SYS_BUS_DEVICE(&s->scu);
  65
  66     gicdev = DEVICE(&s->gic);
  67     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  68     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  69     qdev_prop_set_uint32(gicdev, "num-priority-bits",
  70                          A9_GIC_NUM_PRIORITY_BITS);
  71
  72     /* Make the GIC's TZ support match the CPUs. We assume that
  73      * either all the CPUs have TZ, or none do.
  74      */
  75     cpuobj = OBJECT(qemu_get_cpu(0));
  76     has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
  77         object_property_get_bool(cpuobj, "has_el3", &error_abort);
  78     qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
  79
  80     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err)) {
  81         error_propagate(errp, err);
  82         return;
  83     }
  84     gicbusdev = SYS_BUS_DEVICE(&s->gic);
  85
  86     /* Pass through outbound IRQ lines from the GIC */
  87     sysbus_pass_irq(sbd, gicbusdev);
  88
  89     /* Pass through inbound GPIO lines to the GIC */
  90     qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
  91
  92     gtimerdev = DEVICE(&s->gtimer);
  93     qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
  94     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), &err)) {
  95         error_propagate(errp, err);
  96         return;
  97     }
  98     gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer);
  99
 100     mptimerdev = DEVICE(&s->mptimer);
 101     qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
 102     if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err)) {
 103         error_propagate(errp, err);
 104         return;
 105     }
 106     mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer);
 107
 108     wdtdev = DEVICE(&s->wdt);
 109     qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
 110     if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &err)) {
 111         error_propagate(errp, err);
 112         return;
 113     }
 114     wdtbusdev = SYS_BUS_DEVICE(&s->wdt);
 115
 116     /* Memory map (addresses are offsets from PERIPHBASE):
 117      *  0x0000-0x00ff -- Snoop Control Unit
 118      *  0x0100-0x01ff -- GIC CPU interface
 119      *  0x0200-0x02ff -- Global Timer
 120      *  0x0300-0x05ff -- nothing
 121      *  0x0600-0x06ff -- private timers and watchdogs
 122      *  0x0700-0x0fff -- nothing
 123      *  0x1000-0x1fff -- GIC Distributor
 124      */
 125     memory_region_add_subregion(&s->container, 0,
 126                                 sysbus_mmio_get_region(scubusdev, 0));
 127     /* GIC CPU interface */
 128     memory_region_add_subregion(&s->container, 0x100,
 129                                 sysbus_mmio_get_region(gicbusdev, 1));
 130     memory_region_add_subregion(&s->container, 0x200,
 131                                 sysbus_mmio_get_region(gtimerbusdev, 0));
 132     /* Note that the A9 exposes only the "timer/watchdog for this core"
 133      * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
 134      */
 135     memory_region_add_subregion(&s->container, 0x600,
 136                                 sysbus_mmio_get_region(mptimerbusdev, 0));
 137     memory_region_add_subregion(&s->container, 0x620,
 138                                 sysbus_mmio_get_region(wdtbusdev, 0));
 139     memory_region_add_subregion(&s->container, 0x1000,
 140                                 sysbus_mmio_get_region(gicbusdev, 0));
 141
 142     /* Wire up the interrupt from each watchdog and timer.
 143      * For each core the global timer is PPI 27, the private
 144      * timer is PPI 29 and the watchdog PPI 30.
 145      */
 146     for (i = 0; i < s->num_cpu; i++) {
 147         int ppibase = (s->num_irq - 32) + i * 32;
 148         sysbus_connect_irq(gtimerbusdev, i,
 149                            qdev_get_gpio_in(gicdev, ppibase + 27));
 150         sysbus_connect_irq(mptimerbusdev, i,
 151                            qdev_get_gpio_in(gicdev, ppibase + 29));
 152         sysbus_connect_irq(wdtbusdev, i,
 153                            qdev_get_gpio_in(gicdev, ppibase + 30));
 154     }
 155 }
 156
 157 static Property a9mp_priv_properties[] = {
 158     DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
 159     /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
 160      * IRQ lines (with another 32 internal). We default to 64+32, which
 161      * is the number provided by the Cortex-A9MP test chip in the
 162      * Realview PBX-A9 and Versatile Express A9 development boards.
 163      * Other boards may differ and should set this property appropriately.
 164      */
 165     DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
 166     DEFINE_PROP_END_OF_LIST(),
 167 };
 168
 169 static void a9mp_priv_class_init(ObjectClass *klass, void *data)
 170 {
 171     DeviceClass *dc = DEVICE_CLASS(klass);
 172
 173     dc->realize = a9mp_priv_realize;
 174     device_class_set_props(dc, a9mp_priv_properties);
 175 }
 176
 177 static const TypeInfo a9mp_priv_info = {
 178     .name          = TYPE_A9MPCORE_PRIV,
 179     .parent        = TYPE_SYS_BUS_DEVICE,
 180     .instance_size = sizeof(A9MPPrivState),
 181     .instance_init = a9mp_priv_initfn,
 182     .class_init    = a9mp_priv_class_init,
 183 };
 184
 185 static void a9mp_register_types(void)
 186 {
 187     type_register_static(&a9mp_priv_info);
 188 }
 189
 190 type_init(a9mp_register_types)