hw/cpu/arm11mpcore.c

   1 /*
   2  * ARM11MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "qemu/module.h"
  13 #include "hw/cpu/arm11mpcore.h"
  14 #include "hw/intc/realview_gic.h"
  15 #include "hw/irq.h"
  16 #include "hw/qdev-properties.h"
  17
  18 #define ARM11MPCORE_NUM_GIC_PRIORITY_BITS    4
  19
  20 static void mpcore_priv_set_irq(void *opaque, int irq, int level)
  21 {
  22     ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
  23
  24     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  25 }
  26
  27 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
  28 {
  29     int i;
  30     SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);
  31     DeviceState *gicdev = DEVICE(&s->gic);
  32     SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);
  33     SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);
  34     SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);
  35
  36     memory_region_add_subregion(&s->container, 0,
  37                                 sysbus_mmio_get_region(scubusdev, 0));
  38     /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
  39      * at 0x200, 0x300...
  40      */
  41     for (i = 0; i < (s->num_cpu + 1); i++) {
  42         hwaddr offset = 0x100 + (i * 0x100);
  43         memory_region_add_subregion(&s->container, offset,
  44                                     sysbus_mmio_get_region(gicbusdev, i + 1));
  45     }
  46     /* Add the regions for timer and watchdog for "current CPU" and
  47      * for each specific CPU.
  48      */
  49     for (i = 0; i < (s->num_cpu + 1); i++) {
  50         /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
  51         hwaddr offset = 0x600 + i * 0x100;
  52         memory_region_add_subregion(&s->container, offset,
  53                                     sysbus_mmio_get_region(timerbusdev, i));
  54         memory_region_add_subregion(&s->container, offset + 0x20,
  55                                     sysbus_mmio_get_region(wdtbusdev, i));
  56     }
  57     memory_region_add_subregion(&s->container, 0x1000,
  58                                 sysbus_mmio_get_region(gicbusdev, 0));
  59     /* Wire up the interrupt from each watchdog and timer.
  60      * For each core the timer is PPI 29 and the watchdog PPI 30.
  61      */
  62     for (i = 0; i < s->num_cpu; i++) {
  63         int ppibase = (s->num_irq - 32) + i * 32;
  64         sysbus_connect_irq(timerbusdev, i,
  65                            qdev_get_gpio_in(gicdev, ppibase + 29));
  66         sysbus_connect_irq(wdtbusdev, i,
  67                            qdev_get_gpio_in(gicdev, ppibase + 30));
  68     }
  69 }
  70
  71 static void mpcore_priv_realize(DeviceState *dev, Error **errp)
  72 {
  73     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  74     ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
  75     DeviceState *scudev = DEVICE(&s->scu);
  76     DeviceState *gicdev = DEVICE(&s->gic);
  77     DeviceState *mptimerdev = DEVICE(&s->mptimer);
  78     DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
  79     Error *err = NULL;
  80
  81     qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
  82     sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
  83     if (err != NULL) {
  84         error_propagate(errp, err);
  85         return;
  86     }
  87
  88     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  89     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  90     qdev_prop_set_uint32(gicdev, "num-priority-bits",
  91                          ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
  92
  93
  94     sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
  95     if (err != NULL) {
  96         error_propagate(errp, err);
  97         return;
  98     }
  99
 100     /* Pass through outbound IRQ lines from the GIC */
 101     sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));
 102
 103     /* Pass through inbound GPIO lines to the GIC */
 104     qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
 105
 106     qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
 107     sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err);
 108     if (err != NULL) {
 109         error_propagate(errp, err);
 110         return;
 111     }
 112
 113     qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
 114     sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), &err);
 115     if (err != NULL) {
 116         error_propagate(errp, err);
 117         return;
 118     }
 119
 120     mpcore_priv_map_setup(s);
 121 }
 122
 123 static void mpcore_priv_initfn(Object *obj)
 124 {
 125     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 126     ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
 127
 128     memory_region_init(&s->container, OBJECT(s),
 129                        "mpcore-priv-container", 0x2000);
 130     sysbus_init_mmio(sbd, &s->container);
 131
 132     object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU);
 133
 134     object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
 135     /* Request the legacy 11MPCore GIC behaviour: */
 136     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
 137
 138     object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
 139
 140     object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER);
 141 }
 142
 143 static Property mpcore_priv_properties[] = {
 144     DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
 145     /* The ARM11 MPCORE TRM says the on-chip controller may have
 146      * anything from 0 to 224 external interrupt IRQ lines (with another
 147      * 32 internal). We default to 32+32, which is the number provided by
 148      * the ARM11 MPCore test chip in the Realview Versatile Express
 149      * coretile. Other boards may differ and should set this property
 150      * appropriately. Some Linux kernels may not boot if the hardware
 151      * has more IRQ lines than the kernel expects.
 152      */
 153     DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
 154     DEFINE_PROP_END_OF_LIST(),
 155 };
 156
 157 static void mpcore_priv_class_init(ObjectClass *klass, void *data)
 158 {
 159     DeviceClass *dc = DEVICE_CLASS(klass);
 160
 161     dc->realize = mpcore_priv_realize;
 162     device_class_set_props(dc, mpcore_priv_properties);
 163 }
 164
 165 static const TypeInfo mpcore_priv_info = {
 166     .name          = TYPE_ARM11MPCORE_PRIV,
 167     .parent        = TYPE_SYS_BUS_DEVICE,
 168     .instance_size = sizeof(ARM11MPCorePriveState),
 169     .instance_init = mpcore_priv_initfn,
 170     .class_init    = mpcore_priv_class_init,
 171 };
 172
 173 static void arm11mpcore_register_types(void)
 174 {
 175     type_register_static(&mpcore_priv_info);
 176 }
 177
 178 type_init(arm11mpcore_register_types)