hw/hppa/dino.c

   1 /*
   2  * HP-PARISC Dino PCI chipset emulation.
   3  *
   4  * (C) 2017 by Helge Deller <deller@gmx.de>
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  *
   8  * Documentation available at:
   9  * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
  10  * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qemu/module.h"
  15 #include "qemu/units.h"
  16 #include "qapi/error.h"
  17 #include "cpu.h"
  18 #include "hw/irq.h"
  19 #include "sysemu/sysemu.h"
  20 #include "hw/pci/pci.h"
  21 #include "hw/pci/pci_bus.h"
  22 #include "migration/vmstate.h"
  23 #include "hppa_sys.h"
  24 #include "exec/address-spaces.h"
  25
  26
  27 #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
  28
  29 #define DINO_IAR0               0x004
  30 #define DINO_IODC               0x008
  31 #define DINO_IRR0               0x00C  /* RO */
  32 #define DINO_IAR1               0x010
  33 #define DINO_IRR1               0x014  /* RO */
  34 #define DINO_IMR                0x018
  35 #define DINO_IPR                0x01C
  36 #define DINO_TOC_ADDR           0x020
  37 #define DINO_ICR                0x024
  38 #define DINO_ILR                0x028  /* RO */
  39 #define DINO_IO_COMMAND         0x030  /* WO */
  40 #define DINO_IO_STATUS          0x034  /* RO */
  41 #define DINO_IO_CONTROL         0x038
  42 #define DINO_IO_GSC_ERR_RESP    0x040  /* RO */
  43 #define DINO_IO_ERR_INFO        0x044  /* RO */
  44 #define DINO_IO_PCI_ERR_RESP    0x048  /* RO */
  45 #define DINO_IO_FBB_EN          0x05c
  46 #define DINO_IO_ADDR_EN         0x060
  47 #define DINO_PCI_CONFIG_ADDR    0x064
  48 #define DINO_PCI_CONFIG_DATA    0x068
  49 #define DINO_PCI_IO_DATA        0x06c
  50 #define DINO_PCI_MEM_DATA       0x070  /* Dino 3.x only */
  51 #define DINO_GSC2X_CONFIG       0x7b4  /* RO */
  52 #define DINO_GMASK              0x800
  53 #define DINO_PAMR               0x804
  54 #define DINO_PAPR               0x808
  55 #define DINO_DAMODE             0x80c
  56 #define DINO_PCICMD             0x810
  57 #define DINO_PCISTS             0x814  /* R/WC */
  58 #define DINO_MLTIM              0x81c
  59 #define DINO_BRDG_FEAT          0x820
  60 #define DINO_PCIROR             0x824
  61 #define DINO_PCIWOR             0x828
  62 #define DINO_TLTIM              0x830
  63
  64 #define DINO_IRQS         11      /* bits 0-10 are architected */
  65 #define DINO_IRR_MASK     0x5ff   /* only 10 bits are implemented */
  66 #define DINO_LOCAL_IRQS   (DINO_IRQS + 1)
  67 #define DINO_MASK_IRQ(x)  (1 << (x))
  68
  69 #define PCIINTA   0x001
  70 #define PCIINTB   0x002
  71 #define PCIINTC   0x004
  72 #define PCIINTD   0x008
  73 #define PCIINTE   0x010
  74 #define PCIINTF   0x020
  75 #define GSCEXTINT 0x040
  76 /* #define xxx       0x080 - bit 7 is "default" */
  77 /* #define xxx    0x100 - bit 8 not used */
  78 /* #define xxx    0x200 - bit 9 not used */
  79 #define RS232INT  0x400
  80
  81 #define DINO_MEM_CHUNK_SIZE (8 * MiB)
  82
  83 #define DINO_PCI_HOST_BRIDGE(obj) \
  84     OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
  85
  86 typedef struct DinoState {
  87     PCIHostState parent_obj;
  88
  89     /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
  90        so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops.  */
  91
  92     uint32_t iar0;
  93     uint32_t iar1;
  94     uint32_t imr;
  95     uint32_t ipr;
  96     uint32_t icr;
  97     uint32_t ilr;
  98     uint32_t io_addr_en;
  99     uint32_t io_control;
 100
 101     MemoryRegion this_mem;
 102     MemoryRegion pci_mem;
 103     MemoryRegion pci_mem_alias[32];
 104
 105     AddressSpace bm_as;
 106     MemoryRegion bm;
 107     MemoryRegion bm_ram_alias;
 108     MemoryRegion bm_pci_alias;
 109     MemoryRegion bm_cpu_alias;
 110
 111     MemoryRegion cpu0_eir_mem;
 112 } DinoState;
 113
 114 /*
 115  * Dino can forward memory accesses from the CPU in the range between
 116  * 0xf0800000 and 0xff000000 to the PCI bus.
 117  */
 118 static void gsc_to_pci_forwarding(DinoState *s)
 119 {
 120     uint32_t io_addr_en, tmp;
 121     int enabled, i;
 122
 123     tmp = extract32(s->io_control, 7, 2);
 124     enabled = (tmp == 0x01);
 125     io_addr_en = s->io_addr_en;
 126
 127     memory_region_transaction_begin();
 128     for (i = 1; i < 31; i++) {
 129         MemoryRegion *mem = &s->pci_mem_alias[i];
 130         if (enabled && (io_addr_en & (1U << i))) {
 131             if (!memory_region_is_mapped(mem)) {
 132                 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
 133                 memory_region_add_subregion(get_system_memory(), addr, mem);
 134             }
 135         } else if (memory_region_is_mapped(mem)) {
 136             memory_region_del_subregion(get_system_memory(), mem);
 137         }
 138     }
 139     memory_region_transaction_commit();
 140 }
 141
 142 static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
 143                                 unsigned size, bool is_write,
 144                                 MemTxAttrs attrs)
 145 {
 146     switch (addr) {
 147     case DINO_IAR0:
 148     case DINO_IAR1:
 149     case DINO_IRR0:
 150     case DINO_IRR1:
 151     case DINO_IMR:
 152     case DINO_IPR:
 153     case DINO_ICR:
 154     case DINO_ILR:
 155     case DINO_IO_CONTROL:
 156     case DINO_IO_ADDR_EN:
 157     case DINO_PCI_IO_DATA:
 158         return true;
 159     case DINO_PCI_IO_DATA + 2:
 160         return size <= 2;
 161     case DINO_PCI_IO_DATA + 1:
 162     case DINO_PCI_IO_DATA + 3:
 163         return size == 1;
 164     }
 165     return false;
 166 }
 167
 168 static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
 169                                              uint64_t *data, unsigned size,
 170                                              MemTxAttrs attrs)
 171 {
 172     DinoState *s = opaque;
 173     MemTxResult ret = MEMTX_OK;
 174     AddressSpace *io;
 175     uint16_t ioaddr;
 176     uint32_t val;
 177
 178     switch (addr) {
 179     case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
 180         /* Read from PCI IO space. */
 181         io = &address_space_io;
 182         ioaddr = s->parent_obj.config_reg + (addr & 3);
 183         switch (size) {
 184         case 1:
 185             val = address_space_ldub(io, ioaddr, attrs, &ret);
 186             break;
 187         case 2:
 188             val = address_space_lduw_be(io, ioaddr, attrs, &ret);
 189             break;
 190         case 4:
 191             val = address_space_ldl_be(io, ioaddr, attrs, &ret);
 192             break;
 193         default:
 194             g_assert_not_reached();
 195         }
 196         break;
 197
 198     case DINO_IO_ADDR_EN:
 199         val = s->io_addr_en;
 200         break;
 201     case DINO_IO_CONTROL:
 202         val = s->io_control;
 203         break;
 204
 205     case DINO_IAR0:
 206         val = s->iar0;
 207         break;
 208     case DINO_IAR1:
 209         val = s->iar1;
 210         break;
 211     case DINO_IMR:
 212         val = s->imr;
 213         break;
 214     case DINO_ICR:
 215         val = s->icr;
 216         break;
 217     case DINO_IPR:
 218         val = s->ipr;
 219         /* Any read to IPR clears the register.  */
 220         s->ipr = 0;
 221         break;
 222     case DINO_ILR:
 223         val = s->ilr;
 224         break;
 225     case DINO_IRR0:
 226         val = s->ilr & s->imr & ~s->icr;
 227         break;
 228     case DINO_IRR1:
 229         val = s->ilr & s->imr & s->icr;
 230         break;
 231
 232     default:
 233         /* Controlled by dino_chip_mem_valid above.  */
 234         g_assert_not_reached();
 235     }
 236
 237     *data = val;
 238     return ret;
 239 }
 240
 241 static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
 242                                               uint64_t val, unsigned size,
 243                                               MemTxAttrs attrs)
 244 {
 245     DinoState *s = opaque;
 246     AddressSpace *io;
 247     MemTxResult ret;
 248     uint16_t ioaddr;
 249
 250     switch (addr) {
 251     case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
 252         /* Write into PCI IO space.  */
 253         io = &address_space_io;
 254         ioaddr = s->parent_obj.config_reg + (addr & 3);
 255         switch (size) {
 256         case 1:
 257             address_space_stb(io, ioaddr, val, attrs, &ret);
 258             break;
 259         case 2:
 260             address_space_stw_be(io, ioaddr, val, attrs, &ret);
 261             break;
 262         case 4:
 263             address_space_stl_be(io, ioaddr, val, attrs, &ret);
 264             break;
 265         default:
 266             g_assert_not_reached();
 267         }
 268         return ret;
 269
 270     case DINO_IO_ADDR_EN:
 271         /* Never allow first (=firmware) and last (=Dino) areas.  */
 272         s->io_addr_en = val & 0x7ffffffe;
 273         gsc_to_pci_forwarding(s);
 274         break;
 275     case DINO_IO_CONTROL:
 276         s->io_control = val;
 277         gsc_to_pci_forwarding(s);
 278         break;
 279
 280     case DINO_IAR0:
 281         s->iar0 = val;
 282         break;
 283     case DINO_IAR1:
 284         s->iar1 = val;
 285         break;
 286     case DINO_IMR:
 287         s->imr = val;
 288         break;
 289     case DINO_ICR:
 290         s->icr = val;
 291         break;
 292     case DINO_IPR:
 293         /* Any write to IPR clears the register.  */
 294         s->ipr = 0;
 295         break;
 296
 297     case DINO_ILR:
 298     case DINO_IRR0:
 299     case DINO_IRR1:
 300         /* These registers are read-only.  */
 301         break;
 302
 303     default:
 304         /* Controlled by dino_chip_mem_valid above.  */
 305         g_assert_not_reached();
 306     }
 307     return MEMTX_OK;
 308 }
 309
 310 static const MemoryRegionOps dino_chip_ops = {
 311     .read_with_attrs = dino_chip_read_with_attrs,
 312     .write_with_attrs = dino_chip_write_with_attrs,
 313     .endianness = DEVICE_BIG_ENDIAN,
 314     .valid = {
 315         .min_access_size = 1,
 316         .max_access_size = 4,
 317         .accepts = dino_chip_mem_valid,
 318     },
 319     .impl = {
 320         .min_access_size = 1,
 321         .max_access_size = 4,
 322     },
 323 };
 324
 325 static const VMStateDescription vmstate_dino = {
 326     .name = "Dino",
 327     .version_id = 1,
 328     .minimum_version_id = 1,
 329     .fields = (VMStateField[]) {
 330         VMSTATE_UINT32(iar0, DinoState),
 331         VMSTATE_UINT32(iar1, DinoState),
 332         VMSTATE_UINT32(imr, DinoState),
 333         VMSTATE_UINT32(ipr, DinoState),
 334         VMSTATE_UINT32(icr, DinoState),
 335         VMSTATE_UINT32(ilr, DinoState),
 336         VMSTATE_UINT32(io_addr_en, DinoState),
 337         VMSTATE_UINT32(io_control, DinoState),
 338         VMSTATE_END_OF_LIST()
 339     }
 340 };
 341
 342
 343 /* Unlike pci_config_data_le_ops, no check of high bit set in config_reg.  */
 344
 345 static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
 346 {
 347     PCIHostState *s = opaque;
 348     return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
 349 }
 350
 351 static void dino_config_data_write(void *opaque, hwaddr addr,
 352                                    uint64_t val, unsigned len)
 353 {
 354     PCIHostState *s = opaque;
 355     pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
 356 }
 357
 358 static const MemoryRegionOps dino_config_data_ops = {
 359     .read = dino_config_data_read,
 360     .write = dino_config_data_write,
 361     .endianness = DEVICE_LITTLE_ENDIAN,
 362 };
 363
 364 static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
 365 {
 366     PCIHostState *s = opaque;
 367     return s->config_reg;
 368 }
 369
 370 static void dino_config_addr_write(void *opaque, hwaddr addr,
 371                                    uint64_t val, unsigned len)
 372 {
 373     PCIHostState *s = opaque;
 374     s->config_reg = val & ~3U;
 375 }
 376
 377 static const MemoryRegionOps dino_config_addr_ops = {
 378     .read = dino_config_addr_read,
 379     .write = dino_config_addr_write,
 380     .valid.min_access_size = 4,
 381     .valid.max_access_size = 4,
 382     .endianness = DEVICE_BIG_ENDIAN,
 383 };
 384
 385 static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
 386                                             int devfn)
 387 {
 388     DinoState *s = opaque;
 389
 390     return &s->bm_as;
 391 }
 392
 393 /*
 394  * Dino interrupts are connected as shown on Page 78, Table 23
 395  * (Little-endian bit numbers)
 396  *    0   PCI INTA
 397  *    1   PCI INTB
 398  *    2   PCI INTC
 399  *    3   PCI INTD
 400  *    4   PCI INTE
 401  *    5   PCI INTF
 402  *    6   GSC External Interrupt
 403  *    7   Bus Error for "less than fatal" mode
 404  *    8   PS2
 405  *    9   Unused
 406  *    10  RS232
 407  */
 408
 409 static void dino_set_irq(void *opaque, int irq, int level)
 410 {
 411     DinoState *s = opaque;
 412     uint32_t bit = 1u << irq;
 413     uint32_t old_ilr = s->ilr;
 414
 415     if (level) {
 416         uint32_t ena = bit & ~old_ilr;
 417         s->ipr |= ena;
 418         s->ilr = old_ilr | bit;
 419         if (ena & s->imr) {
 420             uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
 421             stl_be_phys(&address_space_memory, iar & -32, iar & 31);
 422         }
 423     } else {
 424         s->ilr = old_ilr & ~bit;
 425     }
 426 }
 427
 428 static int dino_pci_map_irq(PCIDevice *d, int irq_num)
 429 {
 430     int slot = d->devfn >> 3;
 431
 432     assert(irq_num >= 0 && irq_num <= 3);
 433
 434     return slot & 0x03;
 435 }
 436
 437 static void dino_set_timer_irq(void *opaque, int irq, int level)
 438 {
 439     /* ??? Not connected.  */
 440 }
 441
 442 static void dino_set_serial_irq(void *opaque, int irq, int level)
 443 {
 444     dino_set_irq(opaque, 10, level);
 445 }
 446
 447 PCIBus *dino_init(MemoryRegion *addr_space,
 448                   qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq)
 449 {
 450     DeviceState *dev;
 451     DinoState *s;
 452     PCIBus *b;
 453     int i;
 454
 455     dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
 456     s = DINO_PCI_HOST_BRIDGE(dev);
 457
 458     /* Dino PCI access from main memory.  */
 459     memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
 460                           s, "dino", 4096);
 461     memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);
 462
 463     /* Dino PCI config. */
 464     memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
 465                           &dino_config_addr_ops, dev, "pci-conf-idx", 4);
 466     memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
 467                           &dino_config_data_ops, dev, "pci-conf-data", 4);
 468     memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
 469                                 &s->parent_obj.conf_mem);
 470     memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
 471                                 &s->parent_obj.data_mem);
 472
 473     /* Dino PCI bus memory.  */
 474     memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32);
 475
 476     b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
 477                               &s->pci_mem, get_system_io(),
 478                               PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
 479     s->parent_obj.bus = b;
 480     qdev_init_nofail(dev);
 481
 482     /* Set up windows into PCI bus memory.  */
 483     for (i = 1; i < 31; i++) {
 484         uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
 485         char *name = g_strdup_printf("PCI Outbound Window %d", i);
 486         memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
 487                                  name, &s->pci_mem, addr,
 488                                  DINO_MEM_CHUNK_SIZE);
 489     }
 490
 491     /* Set up PCI view of memory: Bus master address space.  */
 492     memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32);
 493     memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
 494                              "bm-system", addr_space, 0,
 495                              0xf0000000 + DINO_MEM_CHUNK_SIZE);
 496     memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
 497                              "bm-pci", &s->pci_mem,
 498                              0xf0000000 + DINO_MEM_CHUNK_SIZE,
 499                              30 * DINO_MEM_CHUNK_SIZE);
 500     memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
 501                              "bm-cpu", addr_space, 0xfff00000,
 502                              0xfffff);
 503     memory_region_add_subregion(&s->bm, 0,
 504                                 &s->bm_ram_alias);
 505     memory_region_add_subregion(&s->bm,
 506                                 0xf0000000 + DINO_MEM_CHUNK_SIZE,
 507                                 &s->bm_pci_alias);
 508     memory_region_add_subregion(&s->bm, 0xfff00000,
 509                                 &s->bm_cpu_alias);
 510     address_space_init(&s->bm_as, &s->bm, "pci-bm");
 511     pci_setup_iommu(b, dino_pcihost_set_iommu, s);
 512
 513     *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
 514     *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);
 515
 516     return b;
 517 }
 518
 519 static void dino_pcihost_class_init(ObjectClass *klass, void *data)
 520 {
 521     DeviceClass *dc = DEVICE_CLASS(klass);
 522
 523     dc->vmsd = &vmstate_dino;
 524 }
 525
 526 static const TypeInfo dino_pcihost_info = {
 527     .name          = TYPE_DINO_PCI_HOST_BRIDGE,
 528     .parent        = TYPE_PCI_HOST_BRIDGE,
 529     .instance_size = sizeof(DinoState),
 530     .class_init    = dino_pcihost_class_init,
 531 };
 532
 533 static void dino_register_types(void)
 534 {
 535     type_register_static(&dino_pcihost_info);
 536 }
 537
 538 type_init(dino_register_types)