hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "hw/hw.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/char/parallel.h"
  31 #include "hw/i386/apic.h"
  32 #include "hw/i386/topology.h"
  33 #include "sysemu/cpus.h"
  34 #include "hw/block/fdc.h"
  35 #include "hw/ide.h"
  36 #include "hw/pci/pci.h"
  37 #include "hw/pci/pci_bus.h"
  38 #include "hw/nvram/fw_cfg.h"
  39 #include "hw/timer/hpet.h"
  40 #include "hw/smbios/smbios.h"
  41 #include "hw/loader.h"
  42 #include "elf.h"
  43 #include "multiboot.h"
  44 #include "hw/timer/mc146818rtc.h"
  45 #include "hw/dma/i8257.h"
  46 #include "hw/timer/i8254.h"
  47 #include "hw/input/i8042.h"
  48 #include "hw/audio/pcspk.h"
  49 #include "hw/pci/msi.h"
  50 #include "hw/sysbus.h"
  51 #include "sysemu/sysemu.h"
  52 #include "sysemu/numa.h"
  53 #include "sysemu/kvm.h"
  54 #include "sysemu/qtest.h"
  55 #include "kvm_i386.h"
  56 #include "hw/xen/xen.h"
  57 #include "ui/qemu-spice.h"
  58 #include "exec/memory.h"
  59 #include "exec/address-spaces.h"
  60 #include "sysemu/arch_init.h"
  61 #include "qemu/bitmap.h"
  62 #include "qemu/config-file.h"
  63 #include "qemu/error-report.h"
  64 #include "qemu/option.h"
  65 #include "hw/acpi/acpi.h"
  66 #include "hw/acpi/cpu_hotplug.h"
  67 #include "hw/boards.h"
  68 #include "acpi-build.h"
  69 #include "hw/mem/pc-dimm.h"
  70 #include "qapi/error.h"
  71 #include "qapi/qapi-visit-common.h"
  72 #include "qapi/visitor.h"
  73 #include "qom/cpu.h"
  74 #include "hw/nmi.h"
  75 #include "hw/i386/intel_iommu.h"
  76 #include "hw/net/ne2000-isa.h"
  77
  78 /* debug PC/ISA interrupts */
  79 //#define DEBUG_IRQ
  80
  81 #ifdef DEBUG_IRQ
  82 #define DPRINTF(fmt, ...)                                       \
  83     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  84 #else
  85 #define DPRINTF(fmt, ...)
  86 #endif
  87
  88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  93
  94 #define E820_NR_ENTRIES         16
  95
  96 struct e820_entry {
  97     uint64_t address;
  98     uint64_t length;
  99     uint32_t type;
 100 } QEMU_PACKED __attribute((__aligned__(4)));
 101
 102 struct e820_table {
 103     uint32_t count;
 104     struct e820_entry entry[E820_NR_ENTRIES];
 105 } QEMU_PACKED __attribute((__aligned__(4)));
 106
 107 static struct e820_table e820_reserve;
 108 static struct e820_entry *e820_table;
 109 static unsigned e820_entries;
 110 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
 111
 112 void gsi_handler(void *opaque, int n, int level)
 113 {
 114     GSIState *s = opaque;
 115
 116     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
 117     if (n < ISA_NUM_IRQS) {
 118         qemu_set_irq(s->i8259_irq[n], level);
 119     }
 120     qemu_set_irq(s->ioapic_irq[n], level);
 121 }
 122
 123 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 124                            unsigned size)
 125 {
 126 }
 127
 128 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 129 {
 130     return 0xffffffffffffffffULL;
 131 }
 132
 133 /* MSDOS compatibility mode FPU exception support */
 134 static qemu_irq ferr_irq;
 135
 136 void pc_register_ferr_irq(qemu_irq irq)
 137 {
 138     ferr_irq = irq;
 139 }
 140
 141 /* XXX: add IGNNE support */
 142 void cpu_set_ferr(CPUX86State *s)
 143 {
 144     qemu_irq_raise(ferr_irq);
 145 }
 146
 147 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 148                            unsigned size)
 149 {
 150     qemu_irq_lower(ferr_irq);
 151 }
 152
 153 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 154 {
 155     return 0xffffffffffffffffULL;
 156 }
 157
 158 /* TSC handling */
 159 uint64_t cpu_get_tsc(CPUX86State *env)
 160 {
 161     return cpu_get_ticks();
 162 }
 163
 164 /* IRQ handling */
 165 int cpu_get_pic_interrupt(CPUX86State *env)
 166 {
 167     X86CPU *cpu = x86_env_get_cpu(env);
 168     int intno;
 169
 170     if (!kvm_irqchip_in_kernel()) {
 171         intno = apic_get_interrupt(cpu->apic_state);
 172         if (intno >= 0) {
 173             return intno;
 174         }
 175         /* read the irq from the PIC */
 176         if (!apic_accept_pic_intr(cpu->apic_state)) {
 177             return -1;
 178         }
 179     }
 180
 181     intno = pic_read_irq(isa_pic);
 182     return intno;
 183 }
 184
 185 static void pic_irq_request(void *opaque, int irq, int level)
 186 {
 187     CPUState *cs = first_cpu;
 188     X86CPU *cpu = X86_CPU(cs);
 189
 190     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 191     if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
 192         CPU_FOREACH(cs) {
 193             cpu = X86_CPU(cs);
 194             if (apic_accept_pic_intr(cpu->apic_state)) {
 195                 apic_deliver_pic_intr(cpu->apic_state, level);
 196             }
 197         }
 198     } else {
 199         if (level) {
 200             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 201         } else {
 202             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 203         }
 204     }
 205 }
 206
 207 /* PC cmos mappings */
 208
 209 #define REG_EQUIPMENT_BYTE          0x14
 210
 211 int cmos_get_fd_drive_type(FloppyDriveType fd0)
 212 {
 213     int val;
 214
 215     switch (fd0) {
 216     case FLOPPY_DRIVE_TYPE_144:
 217         /* 1.44 Mb 3"5 drive */
 218         val = 4;
 219         break;
 220     case FLOPPY_DRIVE_TYPE_288:
 221         /* 2.88 Mb 3"5 drive */
 222         val = 5;
 223         break;
 224     case FLOPPY_DRIVE_TYPE_120:
 225         /* 1.2 Mb 5"5 drive */
 226         val = 2;
 227         break;
 228     case FLOPPY_DRIVE_TYPE_NONE:
 229     default:
 230         val = 0;
 231         break;
 232     }
 233     return val;
 234 }
 235
 236 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 237                          int16_t cylinders, int8_t heads, int8_t sectors)
 238 {
 239     rtc_set_memory(s, type_ofs, 47);
 240     rtc_set_memory(s, info_ofs, cylinders);
 241     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 242     rtc_set_memory(s, info_ofs + 2, heads);
 243     rtc_set_memory(s, info_ofs + 3, 0xff);
 244     rtc_set_memory(s, info_ofs + 4, 0xff);
 245     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 246     rtc_set_memory(s, info_ofs + 6, cylinders);
 247     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 248     rtc_set_memory(s, info_ofs + 8, sectors);
 249 }
 250
 251 /* convert boot_device letter to something recognizable by the bios */
 252 static int boot_device2nibble(char boot_device)
 253 {
 254     switch(boot_device) {
 255     case 'a':
 256     case 'b':
 257         return 0x01; /* floppy boot */
 258     case 'c':
 259         return 0x02; /* hard drive boot */
 260     case 'd':
 261         return 0x03; /* CD-ROM boot */
 262     case 'n':
 263         return 0x04; /* Network boot */
 264     }
 265     return 0;
 266 }
 267
 268 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
 269 {
 270 #define PC_MAX_BOOT_DEVICES 3
 271     int nbds, bds[3] = { 0, };
 272     int i;
 273
 274     nbds = strlen(boot_device);
 275     if (nbds > PC_MAX_BOOT_DEVICES) {
 276         error_setg(errp, "Too many boot devices for PC");
 277         return;
 278     }
 279     for (i = 0; i < nbds; i++) {
 280         bds[i] = boot_device2nibble(boot_device[i]);
 281         if (bds[i] == 0) {
 282             error_setg(errp, "Invalid boot device for PC: '%c'",
 283                        boot_device[i]);
 284             return;
 285         }
 286     }
 287     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 288     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 289 }
 290
 291 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
 292 {
 293     set_boot_dev(opaque, boot_device, errp);
 294 }
 295
 296 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
 297 {
 298     int val, nb, i;
 299     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
 300                                    FLOPPY_DRIVE_TYPE_NONE };
 301
 302     /* floppy type */
 303     if (floppy) {
 304         for (i = 0; i < 2; i++) {
 305             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 306         }
 307     }
 308     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 309         cmos_get_fd_drive_type(fd_type[1]);
 310     rtc_set_memory(rtc_state, 0x10, val);
 311
 312     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
 313     nb = 0;
 314     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
 315         nb++;
 316     }
 317     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
 318         nb++;
 319     }
 320     switch (nb) {
 321     case 0:
 322         break;
 323     case 1:
 324         val |= 0x01; /* 1 drive, ready for boot */
 325         break;
 326     case 2:
 327         val |= 0x41; /* 2 drives, ready for boot */
 328         break;
 329     }
 330     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
 331 }
 332
 333 typedef struct pc_cmos_init_late_arg {
 334     ISADevice *rtc_state;
 335     BusState *idebus[2];
 336 } pc_cmos_init_late_arg;
 337
 338 typedef struct check_fdc_state {
 339     ISADevice *floppy;
 340     bool multiple;
 341 } CheckFdcState;
 342
 343 static int check_fdc(Object *obj, void *opaque)
 344 {
 345     CheckFdcState *state = opaque;
 346     Object *fdc;
 347     uint32_t iobase;
 348     Error *local_err = NULL;
 349
 350     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
 351     if (!fdc) {
 352         return 0;
 353     }
 354
 355     iobase = object_property_get_uint(obj, "iobase", &local_err);
 356     if (local_err || iobase != 0x3f0) {
 357         error_free(local_err);
 358         return 0;
 359     }
 360
 361     if (state->floppy) {
 362         state->multiple = true;
 363     } else {
 364         state->floppy = ISA_DEVICE(obj);
 365     }
 366     return 0;
 367 }
 368
 369 static const char * const fdc_container_path[] = {
 370     "/unattached", "/peripheral", "/peripheral-anon"
 371 };
 372
 373 /*
 374  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
 375  * and ACPI objects.
 376  */
 377 ISADevice *pc_find_fdc0(void)
 378 {
 379     int i;
 380     Object *container;
 381     CheckFdcState state = { 0 };
 382
 383     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
 384         container = container_get(qdev_get_machine(), fdc_container_path[i]);
 385         object_child_foreach(container, check_fdc, &state);
 386     }
 387
 388     if (state.multiple) {
 389         warn_report("multiple floppy disk controllers with "
 390                     "iobase=0x3f0 have been found");
 391         error_printf("the one being picked for CMOS setup might not reflect "
 392                      "your intent");
 393     }
 394
 395     return state.floppy;
 396 }
 397
 398 static void pc_cmos_init_late(void *opaque)
 399 {
 400     pc_cmos_init_late_arg *arg = opaque;
 401     ISADevice *s = arg->rtc_state;
 402     int16_t cylinders;
 403     int8_t heads, sectors;
 404     int val;
 405     int i, trans;
 406
 407     val = 0;
 408     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
 409                                            &cylinders, &heads, &sectors) >= 0) {
 410         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 411         val |= 0xf0;
 412     }
 413     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
 414                                            &cylinders, &heads, &sectors) >= 0) {
 415         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 416         val |= 0x0f;
 417     }
 418     rtc_set_memory(s, 0x12, val);
 419
 420     val = 0;
 421     for (i = 0; i < 4; i++) {
 422         /* NOTE: ide_get_geometry() returns the physical
 423            geometry.  It is always such that: 1 <= sects <= 63, 1
 424            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 425            geometry can be different if a translation is done. */
 426         if (arg->idebus[i / 2] &&
 427             ide_get_geometry(arg->idebus[i / 2], i % 2,
 428                              &cylinders, &heads, &sectors) >= 0) {
 429             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 430             assert((trans & ~3) == 0);
 431             val |= trans << (i * 2);
 432         }
 433     }
 434     rtc_set_memory(s, 0x39, val);
 435
 436     pc_cmos_init_floppy(s, pc_find_fdc0());
 437
 438     qemu_unregister_reset(pc_cmos_init_late, opaque);
 439 }
 440
 441 void pc_cmos_init(PCMachineState *pcms,
 442                   BusState *idebus0, BusState *idebus1,
 443                   ISADevice *s)
 444 {
 445     int val;
 446     static pc_cmos_init_late_arg arg;
 447
 448     /* various important CMOS locations needed by PC/Bochs bios */
 449
 450     /* memory size */
 451     /* base memory (first MiB) */
 452     val = MIN(pcms->below_4g_mem_size / KiB, 640);
 453     rtc_set_memory(s, 0x15, val);
 454     rtc_set_memory(s, 0x16, val >> 8);
 455     /* extended memory (next 64MiB) */
 456     if (pcms->below_4g_mem_size > 1 * MiB) {
 457         val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
 458     } else {
 459         val = 0;
 460     }
 461     if (val > 65535)
 462         val = 65535;
 463     rtc_set_memory(s, 0x17, val);
 464     rtc_set_memory(s, 0x18, val >> 8);
 465     rtc_set_memory(s, 0x30, val);
 466     rtc_set_memory(s, 0x31, val >> 8);
 467     /* memory between 16MiB and 4GiB */
 468     if (pcms->below_4g_mem_size > 16 * MiB) {
 469         val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
 470     } else {
 471         val = 0;
 472     }
 473     if (val > 65535)
 474         val = 65535;
 475     rtc_set_memory(s, 0x34, val);
 476     rtc_set_memory(s, 0x35, val >> 8);
 477     /* memory above 4GiB */
 478     val = pcms->above_4g_mem_size / 65536;
 479     rtc_set_memory(s, 0x5b, val);
 480     rtc_set_memory(s, 0x5c, val >> 8);
 481     rtc_set_memory(s, 0x5d, val >> 16);
 482
 483     object_property_add_link(OBJECT(pcms), "rtc_state",
 484                              TYPE_ISA_DEVICE,
 485                              (Object **)&pcms->rtc,
 486                              object_property_allow_set_link,
 487                              OBJ_PROP_LINK_STRONG, &error_abort);
 488     object_property_set_link(OBJECT(pcms), OBJECT(s),
 489                              "rtc_state", &error_abort);
 490
 491     set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
 492
 493     val = 0;
 494     val |= 0x02; /* FPU is there */
 495     val |= 0x04; /* PS/2 mouse installed */
 496     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 497
 498     /* hard drives and FDC */
 499     arg.rtc_state = s;
 500     arg.idebus[0] = idebus0;
 501     arg.idebus[1] = idebus1;
 502     qemu_register_reset(pc_cmos_init_late, &arg);
 503 }
 504
 505 #define TYPE_PORT92 "port92"
 506 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 507
 508 /* port 92 stuff: could be split off */
 509 typedef struct Port92State {
 510     ISADevice parent_obj;
 511
 512     MemoryRegion io;
 513     uint8_t outport;
 514     qemu_irq a20_out;
 515 } Port92State;
 516
 517 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 518                          unsigned size)
 519 {
 520     Port92State *s = opaque;
 521     int oldval = s->outport;
 522
 523     DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
 524     s->outport = val;
 525     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 526     if ((val & 1) && !(oldval & 1)) {
 527         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 528     }
 529 }
 530
 531 static uint64_t port92_read(void *opaque, hwaddr addr,
 532                             unsigned size)
 533 {
 534     Port92State *s = opaque;
 535     uint32_t ret;
 536
 537     ret = s->outport;
 538     DPRINTF("port92: read 0x%02x\n", ret);
 539     return ret;
 540 }
 541
 542 static void port92_init(ISADevice *dev, qemu_irq a20_out)
 543 {
 544     qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
 545 }
 546
 547 static const VMStateDescription vmstate_port92_isa = {
 548     .name = "port92",
 549     .version_id = 1,
 550     .minimum_version_id = 1,
 551     .fields = (VMStateField[]) {
 552         VMSTATE_UINT8(outport, Port92State),
 553         VMSTATE_END_OF_LIST()
 554     }
 555 };
 556
 557 static void port92_reset(DeviceState *d)
 558 {
 559     Port92State *s = PORT92(d);
 560
 561     s->outport &= ~1;
 562 }
 563
 564 static const MemoryRegionOps port92_ops = {
 565     .read = port92_read,
 566     .write = port92_write,
 567     .impl = {
 568         .min_access_size = 1,
 569         .max_access_size = 1,
 570     },
 571     .endianness = DEVICE_LITTLE_ENDIAN,
 572 };
 573
 574 static void port92_initfn(Object *obj)
 575 {
 576     Port92State *s = PORT92(obj);
 577
 578     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 579
 580     s->outport = 0;
 581
 582     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
 583 }
 584
 585 static void port92_realizefn(DeviceState *dev, Error **errp)
 586 {
 587     ISADevice *isadev = ISA_DEVICE(dev);
 588     Port92State *s = PORT92(dev);
 589
 590     isa_register_ioport(isadev, &s->io, 0x92);
 591 }
 592
 593 static void port92_class_initfn(ObjectClass *klass, void *data)
 594 {
 595     DeviceClass *dc = DEVICE_CLASS(klass);
 596
 597     dc->realize = port92_realizefn;
 598     dc->reset = port92_reset;
 599     dc->vmsd = &vmstate_port92_isa;
 600     /*
 601      * Reason: unlike ordinary ISA devices, this one needs additional
 602      * wiring: its A20 output line needs to be wired up by
 603      * port92_init().
 604      */
 605     dc->user_creatable = false;
 606 }
 607
 608 static const TypeInfo port92_info = {
 609     .name          = TYPE_PORT92,
 610     .parent        = TYPE_ISA_DEVICE,
 611     .instance_size = sizeof(Port92State),
 612     .instance_init = port92_initfn,
 613     .class_init    = port92_class_initfn,
 614 };
 615
 616 static void port92_register_types(void)
 617 {
 618     type_register_static(&port92_info);
 619 }
 620
 621 type_init(port92_register_types)
 622
 623 static void handle_a20_line_change(void *opaque, int irq, int level)
 624 {
 625     X86CPU *cpu = opaque;
 626
 627     /* XXX: send to all CPUs ? */
 628     /* XXX: add logic to handle multiple A20 line sources */
 629     x86_cpu_set_a20(cpu, level);
 630 }
 631
 632 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 633 {
 634     int index = le32_to_cpu(e820_reserve.count);
 635     struct e820_entry *entry;
 636
 637     if (type != E820_RAM) {
 638         /* old FW_CFG_E820_TABLE entry -- reservations only */
 639         if (index >= E820_NR_ENTRIES) {
 640             return -EBUSY;
 641         }
 642         entry = &e820_reserve.entry[index++];
 643
 644         entry->address = cpu_to_le64(address);
 645         entry->length = cpu_to_le64(length);
 646         entry->type = cpu_to_le32(type);
 647
 648         e820_reserve.count = cpu_to_le32(index);
 649     }
 650
 651     /* new "etc/e820" file -- include ram too */
 652     e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
 653     e820_table[e820_entries].address = cpu_to_le64(address);
 654     e820_table[e820_entries].length = cpu_to_le64(length);
 655     e820_table[e820_entries].type = cpu_to_le32(type);
 656     e820_entries++;
 657
 658     return e820_entries;
 659 }
 660
 661 int e820_get_num_entries(void)
 662 {
 663     return e820_entries;
 664 }
 665
 666 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
 667 {
 668     if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
 669         *address = le64_to_cpu(e820_table[idx].address);
 670         *length = le64_to_cpu(e820_table[idx].length);
 671         return true;
 672     }
 673     return false;
 674 }
 675
 676 /* Enables contiguous-apic-ID mode, for compatibility */
 677 static bool compat_apic_id_mode;
 678
 679 void enable_compat_apic_id_mode(void)
 680 {
 681     compat_apic_id_mode = true;
 682 }
 683
 684 /* Calculates initial APIC ID for a specific CPU index
 685  *
 686  * Currently we need to be able to calculate the APIC ID from the CPU index
 687  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
 688  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
 689  * all CPUs up to max_cpus.
 690  */
 691 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
 692 {
 693     uint32_t correct_id;
 694     static bool warned;
 695
 696     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
 697     if (compat_apic_id_mode) {
 698         if (cpu_index != correct_id && !warned && !qtest_enabled()) {
 699             error_report("APIC IDs set in compatibility mode, "
 700                          "CPU topology won't match the configuration");
 701             warned = true;
 702         }
 703         return cpu_index;
 704     } else {
 705         return correct_id;
 706     }
 707 }
 708
 709 static void pc_build_smbios(PCMachineState *pcms)
 710 {
 711     uint8_t *smbios_tables, *smbios_anchor;
 712     size_t smbios_tables_len, smbios_anchor_len;
 713     struct smbios_phys_mem_area *mem_array;
 714     unsigned i, array_count;
 715     MachineState *ms = MACHINE(pcms);
 716     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 717
 718     /* tell smbios about cpuid version and features */
 719     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 720
 721     smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
 722     if (smbios_tables) {
 723         fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 724                          smbios_tables, smbios_tables_len);
 725     }
 726
 727     /* build the array of physical mem area from e820 table */
 728     mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
 729     for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
 730         uint64_t addr, len;
 731
 732         if (e820_get_entry(i, E820_RAM, &addr, &len)) {
 733             mem_array[array_count].address = addr;
 734             mem_array[array_count].length = len;
 735             array_count++;
 736         }
 737     }
 738     smbios_get_tables(mem_array, array_count,
 739                       &smbios_tables, &smbios_tables_len,
 740                       &smbios_anchor, &smbios_anchor_len);
 741     g_free(mem_array);
 742
 743     if (smbios_anchor) {
 744         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
 745                         smbios_tables, smbios_tables_len);
 746         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
 747                         smbios_anchor, smbios_anchor_len);
 748     }
 749 }
 750
 751 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
 752 {
 753     FWCfgState *fw_cfg;
 754     uint64_t *numa_fw_cfg;
 755     int i;
 756     const CPUArchIdList *cpus;
 757     MachineClass *mc = MACHINE_GET_CLASS(pcms);
 758
 759     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
 760     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
 761
 762     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 763      *
 764      * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 765      * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 766      * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 767      * for CPU hotplug also uses APIC ID and not "CPU index".
 768      * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 769      * but the "limit to the APIC ID values SeaBIOS may see".
 770      *
 771      * So for compatibility reasons with old BIOSes we are stuck with
 772      * "etc/max-cpus" actually being apic_id_limit
 773      */
 774     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
 775     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 776     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 777                      acpi_tables, acpi_tables_len);
 778     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 779
 780     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 781                      &e820_reserve, sizeof(e820_reserve));
 782     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 783                     sizeof(struct e820_entry) * e820_entries);
 784
 785     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 786     /* allocate memory for the NUMA channel: one (64bit) word for the number
 787      * of nodes, one word for each VCPU->node and one word for each node to
 788      * hold the amount of memory.
 789      */
 790     numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
 791     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 792     cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
 793     for (i = 0; i < cpus->len; i++) {
 794         unsigned int apic_id = cpus->cpus[i].arch_id;
 795         assert(apic_id < pcms->apic_id_limit);
 796         numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 797     }
 798     for (i = 0; i < nb_numa_nodes; i++) {
 799         numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
 800             cpu_to_le64(numa_info[i].node_mem);
 801     }
 802     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 803                      (1 + pcms->apic_id_limit + nb_numa_nodes) *
 804                      sizeof(*numa_fw_cfg));
 805
 806     return fw_cfg;
 807 }
 808
 809 static long get_file_size(FILE *f)
 810 {
 811     long where, size;
 812
 813     /* XXX: on Unix systems, using fstat() probably makes more sense */
 814
 815     where = ftell(f);
 816     fseek(f, 0, SEEK_END);
 817     size = ftell(f);
 818     fseek(f, where, SEEK_SET);
 819
 820     return size;
 821 }
 822
 823 /* setup_data types */
 824 #define SETUP_NONE     0
 825 #define SETUP_E820_EXT 1
 826 #define SETUP_DTB      2
 827 #define SETUP_PCI      3
 828 #define SETUP_EFI      4
 829
 830 struct setup_data {
 831     uint64_t next;
 832     uint32_t type;
 833     uint32_t len;
 834     uint8_t data[0];
 835 } __attribute__((packed));
 836
 837 static void load_linux(PCMachineState *pcms,
 838                        FWCfgState *fw_cfg)
 839 {
 840     uint16_t protocol;
 841     int setup_size, kernel_size, cmdline_size;
 842     int dtb_size, setup_data_offset;
 843     uint32_t initrd_max;
 844     uint8_t header[8192], *setup, *kernel;
 845     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 846     FILE *f;
 847     char *vmode;
 848     MachineState *machine = MACHINE(pcms);
 849     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 850     struct setup_data *setup_data;
 851     const char *kernel_filename = machine->kernel_filename;
 852     const char *initrd_filename = machine->initrd_filename;
 853     const char *dtb_filename = machine->dtb;
 854     const char *kernel_cmdline = machine->kernel_cmdline;
 855
 856     /* Align to 16 bytes as a paranoia measure */
 857     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 858
 859     /* load the kernel header */
 860     f = fopen(kernel_filename, "rb");
 861     if (!f || !(kernel_size = get_file_size(f)) ||
 862         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 863         MIN(ARRAY_SIZE(header), kernel_size)) {
 864         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 865                 kernel_filename, strerror(errno));
 866         exit(1);
 867     }
 868
 869     /* kernel protocol version */
 870 #if 0
 871     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 872 #endif
 873     if (ldl_p(header+0x202) == 0x53726448) {
 874         protocol = lduw_p(header+0x206);
 875     } else {
 876         /* This looks like a multiboot kernel. If it is, let's stop
 877            treating it like a Linux kernel. */
 878         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 879                            kernel_cmdline, kernel_size, header)) {
 880             return;
 881         }
 882         protocol = 0;
 883     }
 884
 885     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 886         /* Low kernel */
 887         real_addr    = 0x90000;
 888         cmdline_addr = 0x9a000 - cmdline_size;
 889         prot_addr    = 0x10000;
 890     } else if (protocol < 0x202) {
 891         /* High but ancient kernel */
 892         real_addr    = 0x90000;
 893         cmdline_addr = 0x9a000 - cmdline_size;
 894         prot_addr    = 0x100000;
 895     } else {
 896         /* High and recent kernel */
 897         real_addr    = 0x10000;
 898         cmdline_addr = 0x20000;
 899         prot_addr    = 0x100000;
 900     }
 901
 902 #if 0
 903     fprintf(stderr,
 904             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 905             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 906             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 907             real_addr,
 908             cmdline_addr,
 909             prot_addr);
 910 #endif
 911
 912     /* highest address for loading the initrd */
 913     if (protocol >= 0x203) {
 914         initrd_max = ldl_p(header+0x22c);
 915     } else {
 916         initrd_max = 0x37ffffff;
 917     }
 918
 919     if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
 920         initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
 921     }
 922
 923     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 924     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 925     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 926
 927     if (protocol >= 0x202) {
 928         stl_p(header+0x228, cmdline_addr);
 929     } else {
 930         stw_p(header+0x20, 0xA33F);
 931         stw_p(header+0x22, cmdline_addr-real_addr);
 932     }
 933
 934     /* handle vga= parameter */
 935     vmode = strstr(kernel_cmdline, "vga=");
 936     if (vmode) {
 937         unsigned int video_mode;
 938         /* skip "vga=" */
 939         vmode += 4;
 940         if (!strncmp(vmode, "normal", 6)) {
 941             video_mode = 0xffff;
 942         } else if (!strncmp(vmode, "ext", 3)) {
 943             video_mode = 0xfffe;
 944         } else if (!strncmp(vmode, "ask", 3)) {
 945             video_mode = 0xfffd;
 946         } else {
 947             video_mode = strtol(vmode, NULL, 0);
 948         }
 949         stw_p(header+0x1fa, video_mode);
 950     }
 951
 952     /* loader type */
 953     /* High nybble = B reserved for QEMU; low nybble is revision number.
 954        If this code is substantially changed, you may want to consider
 955        incrementing the revision. */
 956     if (protocol >= 0x200) {
 957         header[0x210] = 0xB0;
 958     }
 959     /* heap */
 960     if (protocol >= 0x201) {
 961         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 962         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 963     }
 964
 965     /* load initrd */
 966     if (initrd_filename) {
 967         gsize initrd_size;
 968         gchar *initrd_data;
 969         GError *gerr = NULL;
 970
 971         if (protocol < 0x200) {
 972             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 973             exit(1);
 974         }
 975
 976         if (!g_file_get_contents(initrd_filename, &initrd_data,
 977                                  &initrd_size, &gerr)) {
 978             fprintf(stderr, "qemu: error reading initrd %s: %s\n",
 979                     initrd_filename, gerr->message);
 980             exit(1);
 981         }
 982         if (initrd_size >= initrd_max) {
 983             fprintf(stderr, "qemu: initrd is too large, cannot support."
 984                     "(max: %"PRIu32", need %"PRId64")\n",
 985                     initrd_max, (uint64_t)initrd_size);
 986             exit(1);
 987         }
 988
 989         initrd_addr = (initrd_max-initrd_size) & ~4095;
 990
 991         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 992         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 993         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 994
 995         stl_p(header+0x218, initrd_addr);
 996         stl_p(header+0x21c, initrd_size);
 997     }
 998
 999     /* load kernel and setup */
1000     setup_size = header[0x1f1];
1001     if (setup_size == 0) {
1002         setup_size = 4;
1003     }
1004     setup_size = (setup_size+1)*512;
1005     if (setup_size > kernel_size) {
1006         fprintf(stderr, "qemu: invalid kernel header\n");
1007         exit(1);
1008     }
1009     kernel_size -= setup_size;
1010
1011     setup  = g_malloc(setup_size);
1012     kernel = g_malloc(kernel_size);
1013     fseek(f, 0, SEEK_SET);
1014     if (fread(setup, 1, setup_size, f) != setup_size) {
1015         fprintf(stderr, "fread() failed\n");
1016         exit(1);
1017     }
1018     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1019         fprintf(stderr, "fread() failed\n");
1020         exit(1);
1021     }
1022     fclose(f);
1023
1024     /* append dtb to kernel */
1025     if (dtb_filename) {
1026         if (protocol < 0x209) {
1027             fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1028             exit(1);
1029         }
1030
1031         dtb_size = get_image_size(dtb_filename);
1032         if (dtb_size <= 0) {
1033             fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1034                     dtb_filename, strerror(errno));
1035             exit(1);
1036         }
1037
1038         setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1039         kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1040         kernel = g_realloc(kernel, kernel_size);
1041
1042         stq_p(header+0x250, prot_addr + setup_data_offset);
1043
1044         setup_data = (struct setup_data *)(kernel + setup_data_offset);
1045         setup_data->next = 0;
1046         setup_data->type = cpu_to_le32(SETUP_DTB);
1047         setup_data->len = cpu_to_le32(dtb_size);
1048
1049         load_image_size(dtb_filename, setup_data->data, dtb_size);
1050     }
1051
1052     memcpy(setup, header, MIN(sizeof(header), setup_size));
1053
1054     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1055     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1056     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1057
1058     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1059     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1060     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1061
1062     option_rom[nb_option_roms].bootindex = 0;
1063     option_rom[nb_option_roms].name = "linuxboot.bin";
1064     if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1065         option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1066     }
1067     nb_option_roms++;
1068 }
1069
1070 #define NE2000_NB_MAX 6
1071
1072 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1073                                               0x280, 0x380 };
1074 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1075
1076 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1077 {
1078     static int nb_ne2k = 0;
1079
1080     if (nb_ne2k == NE2000_NB_MAX)
1081         return;
1082     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1083                     ne2000_irq[nb_ne2k], nd);
1084     nb_ne2k++;
1085 }
1086
1087 DeviceState *cpu_get_current_apic(void)
1088 {
1089     if (current_cpu) {
1090         X86CPU *cpu = X86_CPU(current_cpu);
1091         return cpu->apic_state;
1092     } else {
1093         return NULL;
1094     }
1095 }
1096
1097 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1098 {
1099     X86CPU *cpu = opaque;
1100
1101     if (level) {
1102         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1103     }
1104 }
1105
1106 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
1107 {
1108     Object *cpu = NULL;
1109     Error *local_err = NULL;
1110
1111     cpu = object_new(typename);
1112
1113     object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1114     object_property_set_bool(cpu, true, "realized", &local_err);
1115
1116     object_unref(cpu);
1117     error_propagate(errp, local_err);
1118 }
1119
1120 void pc_hot_add_cpu(const int64_t id, Error **errp)
1121 {
1122     MachineState *ms = MACHINE(qdev_get_machine());
1123     int64_t apic_id = x86_cpu_apic_id_from_index(id);
1124     Error *local_err = NULL;
1125
1126     if (id < 0) {
1127         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1128         return;
1129     }
1130
1131     if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1132         error_setg(errp, "Unable to add CPU: %" PRIi64
1133                    ", resulting APIC ID (%" PRIi64 ") is too large",
1134                    id, apic_id);
1135         return;
1136     }
1137
1138     pc_new_cpu(ms->cpu_type, apic_id, &local_err);
1139     if (local_err) {
1140         error_propagate(errp, local_err);
1141         return;
1142     }
1143 }
1144
1145 void pc_cpus_init(PCMachineState *pcms)
1146 {
1147     int i;
1148     const CPUArchIdList *possible_cpus;
1149     MachineState *ms = MACHINE(pcms);
1150     MachineClass *mc = MACHINE_GET_CLASS(pcms);
1151
1152     /* Calculates the limit to CPU APIC ID values
1153      *
1154      * Limit for the APIC ID value, so that all
1155      * CPU APIC IDs are < pcms->apic_id_limit.
1156      *
1157      * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1158      */
1159     pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1160     possible_cpus = mc->possible_cpu_arch_ids(ms);
1161     for (i = 0; i < smp_cpus; i++) {
1162         pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1163                    &error_fatal);
1164     }
1165 }
1166
1167 static void pc_build_feature_control_file(PCMachineState *pcms)
1168 {
1169     MachineState *ms = MACHINE(pcms);
1170     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1171     CPUX86State *env = &cpu->env;
1172     uint32_t unused, ecx, edx;
1173     uint64_t feature_control_bits = 0;
1174     uint64_t *val;
1175
1176     cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1177     if (ecx & CPUID_EXT_VMX) {
1178         feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1179     }
1180
1181     if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1182         (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1183         (env->mcg_cap & MCG_LMCE_P)) {
1184         feature_control_bits |= FEATURE_CONTROL_LMCE;
1185     }
1186
1187     if (!feature_control_bits) {
1188         return;
1189     }
1190
1191     val = g_malloc(sizeof(*val));
1192     *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1193     fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1194 }
1195
1196 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1197 {
1198     if (cpus_count > 0xff) {
1199         /* If the number of CPUs can't be represented in 8 bits, the
1200          * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1201          * to make old BIOSes fail more predictably.
1202          */
1203         rtc_set_memory(rtc, 0x5f, 0);
1204     } else {
1205         rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1206     }
1207 }
1208
1209 static
1210 void pc_machine_done(Notifier *notifier, void *data)
1211 {
1212     PCMachineState *pcms = container_of(notifier,
1213                                         PCMachineState, machine_done);
1214     PCIBus *bus = pcms->bus;
1215
1216     /* set the number of CPUs */
1217     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1218
1219     if (bus) {
1220         int extra_hosts = 0;
1221
1222         QLIST_FOREACH(bus, &bus->child, sibling) {
1223             /* look for expander root buses */
1224             if (pci_bus_is_root(bus)) {
1225                 extra_hosts++;
1226             }
1227         }
1228         if (extra_hosts && pcms->fw_cfg) {
1229             uint64_t *val = g_malloc(sizeof(*val));
1230             *val = cpu_to_le64(extra_hosts);
1231             fw_cfg_add_file(pcms->fw_cfg,
1232                     "etc/extra-pci-roots", val, sizeof(*val));
1233         }
1234     }
1235
1236     acpi_setup();
1237     if (pcms->fw_cfg) {
1238         pc_build_smbios(pcms);
1239         pc_build_feature_control_file(pcms);
1240         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1241         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1242     }
1243
1244     if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1245         IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1246
1247         if (!iommu || !iommu->x86_iommu.intr_supported ||
1248             iommu->intr_eim != ON_OFF_AUTO_ON) {
1249             error_report("current -smp configuration requires "
1250                          "Extended Interrupt Mode enabled. "
1251                          "You can add an IOMMU using: "
1252                          "-device intel-iommu,intremap=on,eim=on");
1253             exit(EXIT_FAILURE);
1254         }
1255     }
1256 }
1257
1258 void pc_guest_info_init(PCMachineState *pcms)
1259 {
1260     int i;
1261
1262     pcms->apic_xrupt_override = kvm_allows_irq0_override();
1263     pcms->numa_nodes = nb_numa_nodes;
1264     pcms->node_mem = g_malloc0(pcms->numa_nodes *
1265                                     sizeof *pcms->node_mem);
1266     for (i = 0; i < nb_numa_nodes; i++) {
1267         pcms->node_mem[i] = numa_info[i].node_mem;
1268     }
1269
1270     pcms->machine_done.notify = pc_machine_done;
1271     qemu_add_machine_init_done_notifier(&pcms->machine_done);
1272 }
1273
1274 /* setup pci memory address space mapping into system address space */
1275 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1276                             MemoryRegion *pci_address_space)
1277 {
1278     /* Set to lower priority than RAM */
1279     memory_region_add_subregion_overlap(system_memory, 0x0,
1280                                         pci_address_space, -1);
1281 }
1282
1283 void pc_acpi_init(const char *default_dsdt)
1284 {
1285     char *filename;
1286
1287     if (acpi_tables != NULL) {
1288         /* manually set via -acpitable, leave it alone */
1289         return;
1290     }
1291
1292     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1293     if (filename == NULL) {
1294         warn_report("failed to find %s", default_dsdt);
1295     } else {
1296         QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1297                                           &error_abort);
1298         Error *err = NULL;
1299
1300         qemu_opt_set(opts, "file", filename, &error_abort);
1301
1302         acpi_table_add_builtin(opts, &err);
1303         if (err) {
1304             warn_reportf_err(err, "failed to load %s: ", filename);
1305         }
1306         g_free(filename);
1307     }
1308 }
1309
1310 void xen_load_linux(PCMachineState *pcms)
1311 {
1312     int i;
1313     FWCfgState *fw_cfg;
1314
1315     assert(MACHINE(pcms)->kernel_filename != NULL);
1316
1317     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1318     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1319     rom_set_fw(fw_cfg);
1320
1321     load_linux(pcms, fw_cfg);
1322     for (i = 0; i < nb_option_roms; i++) {
1323         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1324                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1325                !strcmp(option_rom[i].name, "multiboot.bin"));
1326         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1327     }
1328     pcms->fw_cfg = fw_cfg;
1329 }
1330
1331 void pc_memory_init(PCMachineState *pcms,
1332                     MemoryRegion *system_memory,
1333                     MemoryRegion *rom_memory,
1334                     MemoryRegion **ram_memory)
1335 {
1336     int linux_boot, i;
1337     MemoryRegion *ram, *option_rom_mr;
1338     MemoryRegion *ram_below_4g, *ram_above_4g;
1339     FWCfgState *fw_cfg;
1340     MachineState *machine = MACHINE(pcms);
1341     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1342
1343     assert(machine->ram_size == pcms->below_4g_mem_size +
1344                                 pcms->above_4g_mem_size);
1345
1346     linux_boot = (machine->kernel_filename != NULL);
1347
1348     /* Allocate RAM.  We allocate it as a single memory region and use
1349      * aliases to address portions of it, mostly for backwards compatibility
1350      * with older qemus that used qemu_ram_alloc().
1351      */
1352     ram = g_malloc(sizeof(*ram));
1353     memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1354                                          machine->ram_size);
1355     *ram_memory = ram;
1356     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1357     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1358                              0, pcms->below_4g_mem_size);
1359     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1360     e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1361     if (pcms->above_4g_mem_size > 0) {
1362         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1363         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1364                                  pcms->below_4g_mem_size,
1365                                  pcms->above_4g_mem_size);
1366         memory_region_add_subregion(system_memory, 0x100000000ULL,
1367                                     ram_above_4g);
1368         e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1369     }
1370
1371     if (!pcmc->has_reserved_memory &&
1372         (machine->ram_slots ||
1373          (machine->maxram_size > machine->ram_size))) {
1374         MachineClass *mc = MACHINE_GET_CLASS(machine);
1375
1376         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1377                      mc->name);
1378         exit(EXIT_FAILURE);
1379     }
1380
1381     /* always allocate the device memory information */
1382     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1383
1384     /* initialize device memory address space */
1385     if (pcmc->has_reserved_memory &&
1386         (machine->ram_size < machine->maxram_size)) {
1387         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1388
1389         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1390             error_report("unsupported amount of memory slots: %"PRIu64,
1391                          machine->ram_slots);
1392             exit(EXIT_FAILURE);
1393         }
1394
1395         if (QEMU_ALIGN_UP(machine->maxram_size,
1396                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1397             error_report("maximum memory size must by aligned to multiple of "
1398                          "%d bytes", TARGET_PAGE_SIZE);
1399             exit(EXIT_FAILURE);
1400         }
1401
1402         machine->device_memory->base =
1403             ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1404
1405         if (pcmc->enforce_aligned_dimm) {
1406             /* size device region assuming 1G page max alignment per slot */
1407             device_mem_size += (1 * GiB) * machine->ram_slots;
1408         }
1409
1410         if ((machine->device_memory->base + device_mem_size) <
1411             device_mem_size) {
1412             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1413                          machine->maxram_size);
1414             exit(EXIT_FAILURE);
1415         }
1416
1417         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1418                            "device-memory", device_mem_size);
1419         memory_region_add_subregion(system_memory, machine->device_memory->base,
1420                                     &machine->device_memory->mr);
1421     }
1422
1423     /* Initialize PC system firmware */
1424     pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1425
1426     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1427     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1428                            &error_fatal);
1429     if (pcmc->pci_enabled) {
1430         memory_region_set_readonly(option_rom_mr, true);
1431     }
1432     memory_region_add_subregion_overlap(rom_memory,
1433                                         PC_ROM_MIN_VGA,
1434                                         option_rom_mr,
1435                                         1);
1436
1437     fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1438
1439     rom_set_fw(fw_cfg);
1440
1441     if (pcmc->has_reserved_memory && machine->device_memory->base) {
1442         uint64_t *val = g_malloc(sizeof(*val));
1443         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1444         uint64_t res_mem_end = machine->device_memory->base;
1445
1446         if (!pcmc->broken_reserved_end) {
1447             res_mem_end += memory_region_size(&machine->device_memory->mr);
1448         }
1449         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1450         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1451     }
1452
1453     if (linux_boot) {
1454         load_linux(pcms, fw_cfg);
1455     }
1456
1457     for (i = 0; i < nb_option_roms; i++) {
1458         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1459     }
1460     pcms->fw_cfg = fw_cfg;
1461
1462     /* Init default IOAPIC address space */
1463     pcms->ioapic_as = &address_space_memory;
1464 }
1465
1466 /*
1467  * The 64bit pci hole starts after "above 4G RAM" and
1468  * potentially the space reserved for memory hotplug.
1469  */
1470 uint64_t pc_pci_hole64_start(void)
1471 {
1472     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1473     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1474     MachineState *ms = MACHINE(pcms);
1475     uint64_t hole64_start = 0;
1476
1477     if (pcmc->has_reserved_memory && ms->device_memory->base) {
1478         hole64_start = ms->device_memory->base;
1479         if (!pcmc->broken_reserved_end) {
1480             hole64_start += memory_region_size(&ms->device_memory->mr);
1481         }
1482     } else {
1483         hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1484     }
1485
1486     return ROUND_UP(hole64_start, 1 * GiB);
1487 }
1488
1489 qemu_irq pc_allocate_cpu_irq(void)
1490 {
1491     return qemu_allocate_irq(pic_irq_request, NULL, 0);
1492 }
1493
1494 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1495 {
1496     DeviceState *dev = NULL;
1497
1498     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1499     if (pci_bus) {
1500         PCIDevice *pcidev = pci_vga_init(pci_bus);
1501         dev = pcidev ? &pcidev->qdev : NULL;
1502     } else if (isa_bus) {
1503         ISADevice *isadev = isa_vga_init(isa_bus);
1504         dev = isadev ? DEVICE(isadev) : NULL;
1505     }
1506     rom_reset_order_override();
1507     return dev;
1508 }
1509
1510 static const MemoryRegionOps ioport80_io_ops = {
1511     .write = ioport80_write,
1512     .read = ioport80_read,
1513     .endianness = DEVICE_NATIVE_ENDIAN,
1514     .impl = {
1515         .min_access_size = 1,
1516         .max_access_size = 1,
1517     },
1518 };
1519
1520 static const MemoryRegionOps ioportF0_io_ops = {
1521     .write = ioportF0_write,
1522     .read = ioportF0_read,
1523     .endianness = DEVICE_NATIVE_ENDIAN,
1524     .impl = {
1525         .min_access_size = 1,
1526         .max_access_size = 1,
1527     },
1528 };
1529
1530 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1531 {
1532     int i;
1533     DriveInfo *fd[MAX_FD];
1534     qemu_irq *a20_line;
1535     ISADevice *i8042, *port92, *vmmouse;
1536
1537     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1538     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1539
1540     for (i = 0; i < MAX_FD; i++) {
1541         fd[i] = drive_get(IF_FLOPPY, 0, i);
1542         create_fdctrl |= !!fd[i];
1543     }
1544     if (create_fdctrl) {
1545         fdctrl_init_isa(isa_bus, fd);
1546     }
1547
1548     i8042 = isa_create_simple(isa_bus, "i8042");
1549     if (!no_vmport) {
1550         vmport_init(isa_bus);
1551         vmmouse = isa_try_create(isa_bus, "vmmouse");
1552     } else {
1553         vmmouse = NULL;
1554     }
1555     if (vmmouse) {
1556         DeviceState *dev = DEVICE(vmmouse);
1557         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1558         qdev_init_nofail(dev);
1559     }
1560     port92 = isa_create_simple(isa_bus, "port92");
1561
1562     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1563     i8042_setup_a20_line(i8042, a20_line[0]);
1564     port92_init(port92, a20_line[1]);
1565     g_free(a20_line);
1566 }
1567
1568 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1569                           ISADevice **rtc_state,
1570                           bool create_fdctrl,
1571                           bool no_vmport,
1572                           bool has_pit,
1573                           uint32_t hpet_irqs)
1574 {
1575     int i;
1576     DeviceState *hpet = NULL;
1577     int pit_isa_irq = 0;
1578     qemu_irq pit_alt_irq = NULL;
1579     qemu_irq rtc_irq = NULL;
1580     ISADevice *pit = NULL;
1581     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1582     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1583
1584     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1585     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1586
1587     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1588     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1589
1590     /*
1591      * Check if an HPET shall be created.
1592      *
1593      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1594      * when the HPET wants to take over. Thus we have to disable the latter.
1595      */
1596     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1597         /* In order to set property, here not using sysbus_try_create_simple */
1598         hpet = qdev_try_create(NULL, TYPE_HPET);
1599         if (hpet) {
1600             /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1601              * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1602              * IRQ8 and IRQ2.
1603              */
1604             uint8_t compat = object_property_get_uint(OBJECT(hpet),
1605                     HPET_INTCAP, NULL);
1606             if (!compat) {
1607                 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1608             }
1609             qdev_init_nofail(hpet);
1610             sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1611
1612             for (i = 0; i < GSI_NUM_PINS; i++) {
1613                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1614             }
1615             pit_isa_irq = -1;
1616             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1617             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1618         }
1619     }
1620     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1621
1622     qemu_register_boot_set(pc_boot_set, *rtc_state);
1623
1624     if (!xen_enabled() && has_pit) {
1625         if (kvm_pit_in_kernel()) {
1626             pit = kvm_pit_init(isa_bus, 0x40);
1627         } else {
1628             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1629         }
1630         if (hpet) {
1631             /* connect PIT to output control line of the HPET */
1632             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1633         }
1634         pcspk_init(isa_bus, pit);
1635     }
1636
1637     i8257_dma_init(isa_bus, 0);
1638
1639     /* Super I/O */
1640     pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1641 }
1642
1643 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1644 {
1645     int i;
1646
1647     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1648     for (i = 0; i < nb_nics; i++) {
1649         NICInfo *nd = &nd_table[i];
1650         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1651
1652         if (g_str_equal(model, "ne2k_isa")) {
1653             pc_init_ne2k_isa(isa_bus, nd);
1654         } else {
1655             pci_nic_init_nofail(nd, pci_bus, model, NULL);
1656         }
1657     }
1658     rom_reset_order_override();
1659 }
1660
1661 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1662 {
1663     DeviceState *dev;
1664     SysBusDevice *d;
1665     unsigned int i;
1666
1667     if (kvm_ioapic_in_kernel()) {
1668         dev = qdev_create(NULL, "kvm-ioapic");
1669     } else {
1670         dev = qdev_create(NULL, "ioapic");
1671     }
1672     if (parent_name) {
1673         object_property_add_child(object_resolve_path(parent_name, NULL),
1674                                   "ioapic", OBJECT(dev), NULL);
1675     }
1676     qdev_init_nofail(dev);
1677     d = SYS_BUS_DEVICE(dev);
1678     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1679
1680     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1681         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1682     }
1683 }
1684
1685 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1686                                Error **errp)
1687 {
1688     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1689     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1690     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1691     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1692
1693     /*
1694      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1695      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1696      * addition to cover this case.
1697      */
1698     if (!pcms->acpi_dev || !acpi_enabled) {
1699         error_setg(errp,
1700                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1701         return;
1702     }
1703
1704     if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
1705         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1706         return;
1707     }
1708
1709     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1710                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1711 }
1712
1713 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1714                            DeviceState *dev, Error **errp)
1715 {
1716     HotplugHandlerClass *hhc;
1717     Error *local_err = NULL;
1718     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1719     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1720
1721     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1722     if (local_err) {
1723         goto out;
1724     }
1725
1726     if (is_nvdimm) {
1727         nvdimm_plug(&pcms->acpi_nvdimm_state);
1728     }
1729
1730     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1731     hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1732 out:
1733     error_propagate(errp, local_err);
1734 }
1735
1736 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1737                                      DeviceState *dev, Error **errp)
1738 {
1739     HotplugHandlerClass *hhc;
1740     Error *local_err = NULL;
1741     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1742
1743     /*
1744      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1745      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1746      * addition to cover this case.
1747      */
1748     if (!pcms->acpi_dev || !acpi_enabled) {
1749         error_setg(&local_err,
1750                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1751         goto out;
1752     }
1753
1754     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1755         error_setg(&local_err,
1756                    "nvdimm device hot unplug is not supported yet.");
1757         goto out;
1758     }
1759
1760     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1761     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1762
1763 out:
1764     error_propagate(errp, local_err);
1765 }
1766
1767 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1768                              DeviceState *dev, Error **errp)
1769 {
1770     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1771     HotplugHandlerClass *hhc;
1772     Error *local_err = NULL;
1773
1774     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1775     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1776
1777     if (local_err) {
1778         goto out;
1779     }
1780
1781     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1782     object_unparent(OBJECT(dev));
1783
1784  out:
1785     error_propagate(errp, local_err);
1786 }
1787
1788 static int pc_apic_cmp(const void *a, const void *b)
1789 {
1790    CPUArchId *apic_a = (CPUArchId *)a;
1791    CPUArchId *apic_b = (CPUArchId *)b;
1792
1793    return apic_a->arch_id - apic_b->arch_id;
1794 }
1795
1796 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1797  * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1798  * entry corresponding to CPU's apic_id returns NULL.
1799  */
1800 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1801 {
1802     CPUArchId apic_id, *found_cpu;
1803
1804     apic_id.arch_id = id;
1805     found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1806         ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1807         pc_apic_cmp);
1808     if (found_cpu && idx) {
1809         *idx = found_cpu - ms->possible_cpus->cpus;
1810     }
1811     return found_cpu;
1812 }
1813
1814 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1815                         DeviceState *dev, Error **errp)
1816 {
1817     CPUArchId *found_cpu;
1818     HotplugHandlerClass *hhc;
1819     Error *local_err = NULL;
1820     X86CPU *cpu = X86_CPU(dev);
1821     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1822
1823     if (pcms->acpi_dev) {
1824         hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1825         hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1826         if (local_err) {
1827             goto out;
1828         }
1829     }
1830
1831     /* increment the number of CPUs */
1832     pcms->boot_cpus++;
1833     if (pcms->rtc) {
1834         rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1835     }
1836     if (pcms->fw_cfg) {
1837         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1838     }
1839
1840     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1841     found_cpu->cpu = OBJECT(dev);
1842 out:
1843     error_propagate(errp, local_err);
1844 }
1845 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1846                                      DeviceState *dev, Error **errp)
1847 {
1848     int idx = -1;
1849     HotplugHandlerClass *hhc;
1850     Error *local_err = NULL;
1851     X86CPU *cpu = X86_CPU(dev);
1852     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1853
1854     if (!pcms->acpi_dev) {
1855         error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1856         goto out;
1857     }
1858
1859     pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1860     assert(idx != -1);
1861     if (idx == 0) {
1862         error_setg(&local_err, "Boot CPU is unpluggable");
1863         goto out;
1864     }
1865
1866     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1867     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1868
1869     if (local_err) {
1870         goto out;
1871     }
1872
1873  out:
1874     error_propagate(errp, local_err);
1875
1876 }
1877
1878 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1879                              DeviceState *dev, Error **errp)
1880 {
1881     CPUArchId *found_cpu;
1882     HotplugHandlerClass *hhc;
1883     Error *local_err = NULL;
1884     X86CPU *cpu = X86_CPU(dev);
1885     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1886
1887     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1888     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1889
1890     if (local_err) {
1891         goto out;
1892     }
1893
1894     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1895     found_cpu->cpu = NULL;
1896     object_unparent(OBJECT(dev));
1897
1898     /* decrement the number of CPUs */
1899     pcms->boot_cpus--;
1900     /* Update the number of CPUs in CMOS */
1901     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1902     fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1903  out:
1904     error_propagate(errp, local_err);
1905 }
1906
1907 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1908                             DeviceState *dev, Error **errp)
1909 {
1910     int idx;
1911     CPUState *cs;
1912     CPUArchId *cpu_slot;
1913     X86CPUTopoInfo topo;
1914     X86CPU *cpu = X86_CPU(dev);
1915     MachineState *ms = MACHINE(hotplug_dev);
1916     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1917
1918     if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1919         error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1920                    ms->cpu_type);
1921         return;
1922     }
1923
1924     /* if APIC ID is not set, set it based on socket/core/thread properties */
1925     if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1926         int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
1927
1928         if (cpu->socket_id < 0) {
1929             error_setg(errp, "CPU socket-id is not set");
1930             return;
1931         } else if (cpu->socket_id > max_socket) {
1932             error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1933                        cpu->socket_id, max_socket);
1934             return;
1935         }
1936         if (cpu->core_id < 0) {
1937             error_setg(errp, "CPU core-id is not set");
1938             return;
1939         } else if (cpu->core_id > (smp_cores - 1)) {
1940             error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1941                        cpu->core_id, smp_cores - 1);
1942             return;
1943         }
1944         if (cpu->thread_id < 0) {
1945             error_setg(errp, "CPU thread-id is not set");
1946             return;
1947         } else if (cpu->thread_id > (smp_threads - 1)) {
1948             error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1949                        cpu->thread_id, smp_threads - 1);
1950             return;
1951         }
1952
1953         topo.pkg_id = cpu->socket_id;
1954         topo.core_id = cpu->core_id;
1955         topo.smt_id = cpu->thread_id;
1956         cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
1957     }
1958
1959     cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1960     if (!cpu_slot) {
1961         MachineState *ms = MACHINE(pcms);
1962
1963         x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1964         error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1965                   " APIC ID %" PRIu32 ", valid index range 0:%d",
1966                    topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
1967                    ms->possible_cpus->len - 1);
1968         return;
1969     }
1970
1971     if (cpu_slot->cpu) {
1972         error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1973                    idx, cpu->apic_id);
1974         return;
1975     }
1976
1977     /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1978      * so that machine_query_hotpluggable_cpus would show correct values
1979      */
1980     /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1981      * once -smp refactoring is complete and there will be CPU private
1982      * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1983     x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1984     if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1985         error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1986             " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1987         return;
1988     }
1989     cpu->socket_id = topo.pkg_id;
1990
1991     if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1992         error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1993             " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1994         return;
1995     }
1996     cpu->core_id = topo.core_id;
1997
1998     if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1999         error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2000             " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2001         return;
2002     }
2003     cpu->thread_id = topo.smt_id;
2004
2005     if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2006         error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2007         return;
2008     }
2009
2010     cs = CPU(cpu);
2011     cs->cpu_index = idx;
2012
2013     numa_cpu_pre_plug(cpu_slot, dev, errp);
2014 }
2015
2016 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2017                                           DeviceState *dev, Error **errp)
2018 {
2019     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2020         pc_memory_pre_plug(hotplug_dev, dev, errp);
2021     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2022         pc_cpu_pre_plug(hotplug_dev, dev, errp);
2023     }
2024 }
2025
2026 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2027                                       DeviceState *dev, Error **errp)
2028 {
2029     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2030         pc_memory_plug(hotplug_dev, dev, errp);
2031     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2032         pc_cpu_plug(hotplug_dev, dev, errp);
2033     }
2034 }
2035
2036 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2037                                                 DeviceState *dev, Error **errp)
2038 {
2039     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2040         pc_memory_unplug_request(hotplug_dev, dev, errp);
2041     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2042         pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2043     } else {
2044         error_setg(errp, "acpi: device unplug request for not supported device"
2045                    " type: %s", object_get_typename(OBJECT(dev)));
2046     }
2047 }
2048
2049 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2050                                         DeviceState *dev, Error **errp)
2051 {
2052     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2053         pc_memory_unplug(hotplug_dev, dev, errp);
2054     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2055         pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2056     } else {
2057         error_setg(errp, "acpi: device unplug for not supported device"
2058                    " type: %s", object_get_typename(OBJECT(dev)));
2059     }
2060 }
2061
2062 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2063                                              DeviceState *dev)
2064 {
2065     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2066         object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2067         return HOTPLUG_HANDLER(machine);
2068     }
2069
2070     return NULL;
2071 }
2072
2073 static void
2074 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2075                                          const char *name, void *opaque,
2076                                          Error **errp)
2077 {
2078     MachineState *ms = MACHINE(obj);
2079     int64_t value = memory_region_size(&ms->device_memory->mr);
2080
2081     visit_type_int(v, name, &value, errp);
2082 }
2083
2084 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2085                                             const char *name, void *opaque,
2086                                             Error **errp)
2087 {
2088     PCMachineState *pcms = PC_MACHINE(obj);
2089     uint64_t value = pcms->max_ram_below_4g;
2090
2091     visit_type_size(v, name, &value, errp);
2092 }
2093
2094 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2095                                             const char *name, void *opaque,
2096                                             Error **errp)
2097 {
2098     PCMachineState *pcms = PC_MACHINE(obj);
2099     Error *error = NULL;
2100     uint64_t value;
2101
2102     visit_type_size(v, name, &value, &error);
2103     if (error) {
2104         error_propagate(errp, error);
2105         return;
2106     }
2107     if (value > 4 * GiB) {
2108         error_setg(&error,
2109                    "Machine option 'max-ram-below-4g=%"PRIu64
2110                    "' expects size less than or equal to 4G", value);
2111         error_propagate(errp, error);
2112         return;
2113     }
2114
2115     if (value < 1 * MiB) {
2116         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2117                     "BIOS may not work with less than 1MiB", value);
2118     }
2119
2120     pcms->max_ram_below_4g = value;
2121 }
2122
2123 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2124                                   void *opaque, Error **errp)
2125 {
2126     PCMachineState *pcms = PC_MACHINE(obj);
2127     OnOffAuto vmport = pcms->vmport;
2128
2129     visit_type_OnOffAuto(v, name, &vmport, errp);
2130 }
2131
2132 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2133                                   void *opaque, Error **errp)
2134 {
2135     PCMachineState *pcms = PC_MACHINE(obj);
2136
2137     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2138 }
2139
2140 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2141 {
2142     bool smm_available = false;
2143
2144     if (pcms->smm == ON_OFF_AUTO_OFF) {
2145         return false;
2146     }
2147
2148     if (tcg_enabled() || qtest_enabled()) {
2149         smm_available = true;
2150     } else if (kvm_enabled()) {
2151         smm_available = kvm_has_smm();
2152     }
2153
2154     if (smm_available) {
2155         return true;
2156     }
2157
2158     if (pcms->smm == ON_OFF_AUTO_ON) {
2159         error_report("System Management Mode not supported by this hypervisor.");
2160         exit(1);
2161     }
2162     return false;
2163 }
2164
2165 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2166                                void *opaque, Error **errp)
2167 {
2168     PCMachineState *pcms = PC_MACHINE(obj);
2169     OnOffAuto smm = pcms->smm;
2170
2171     visit_type_OnOffAuto(v, name, &smm, errp);
2172 }
2173
2174 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2175                                void *opaque, Error **errp)
2176 {
2177     PCMachineState *pcms = PC_MACHINE(obj);
2178
2179     visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2180 }
2181
2182 static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2183 {
2184     PCMachineState *pcms = PC_MACHINE(obj);
2185
2186     return pcms->acpi_nvdimm_state.is_enabled;
2187 }
2188
2189 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2190 {
2191     PCMachineState *pcms = PC_MACHINE(obj);
2192
2193     pcms->acpi_nvdimm_state.is_enabled = value;
2194 }
2195
2196 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp)
2197 {
2198     PCMachineState *pcms = PC_MACHINE(obj);
2199
2200     return g_strdup(pcms->acpi_nvdimm_state.persistence_string);
2201 }
2202
2203 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value,
2204                                                Error **errp)
2205 {
2206     PCMachineState *pcms = PC_MACHINE(obj);
2207     AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state;
2208
2209     if (strcmp(value, "cpu") == 0)
2210         nvdimm_state->persistence = 3;
2211     else if (strcmp(value, "mem-ctrl") == 0)
2212         nvdimm_state->persistence = 2;
2213     else {
2214         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
2215                    value);
2216         return;
2217     }
2218
2219     g_free(nvdimm_state->persistence_string);
2220     nvdimm_state->persistence_string = g_strdup(value);
2221 }
2222
2223 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2224 {
2225     PCMachineState *pcms = PC_MACHINE(obj);
2226
2227     return pcms->smbus_enabled;
2228 }
2229
2230 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2231 {
2232     PCMachineState *pcms = PC_MACHINE(obj);
2233
2234     pcms->smbus_enabled = value;
2235 }
2236
2237 static bool pc_machine_get_sata(Object *obj, Error **errp)
2238 {
2239     PCMachineState *pcms = PC_MACHINE(obj);
2240
2241     return pcms->sata_enabled;
2242 }
2243
2244 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2245 {
2246     PCMachineState *pcms = PC_MACHINE(obj);
2247
2248     pcms->sata_enabled = value;
2249 }
2250
2251 static bool pc_machine_get_pit(Object *obj, Error **errp)
2252 {
2253     PCMachineState *pcms = PC_MACHINE(obj);
2254
2255     return pcms->pit_enabled;
2256 }
2257
2258 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2259 {
2260     PCMachineState *pcms = PC_MACHINE(obj);
2261
2262     pcms->pit_enabled = value;
2263 }
2264
2265 static void pc_machine_initfn(Object *obj)
2266 {
2267     PCMachineState *pcms = PC_MACHINE(obj);
2268
2269     pcms->max_ram_below_4g = 0; /* use default */
2270     pcms->smm = ON_OFF_AUTO_AUTO;
2271     pcms->vmport = ON_OFF_AUTO_AUTO;
2272     /* nvdimm is disabled on default. */
2273     pcms->acpi_nvdimm_state.is_enabled = false;
2274     /* acpi build is enabled by default if machine supports it */
2275     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2276     pcms->smbus_enabled = true;
2277     pcms->sata_enabled = true;
2278     pcms->pit_enabled = true;
2279 }
2280
2281 static void pc_machine_reset(void)
2282 {
2283     CPUState *cs;
2284     X86CPU *cpu;
2285
2286     qemu_devices_reset();
2287
2288     /* Reset APIC after devices have been reset to cancel
2289      * any changes that qemu_devices_reset() might have done.
2290      */
2291     CPU_FOREACH(cs) {
2292         cpu = X86_CPU(cs);
2293
2294         if (cpu->apic_state) {
2295             device_reset(cpu->apic_state);
2296         }
2297     }
2298 }
2299
2300 static CpuInstanceProperties
2301 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2302 {
2303     MachineClass *mc = MACHINE_GET_CLASS(ms);
2304     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2305
2306     assert(cpu_index < possible_cpus->len);
2307     return possible_cpus->cpus[cpu_index].props;
2308 }
2309
2310 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2311 {
2312    X86CPUTopoInfo topo;
2313
2314    assert(idx < ms->possible_cpus->len);
2315    x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2316                             smp_cores, smp_threads, &topo);
2317    return topo.pkg_id % nb_numa_nodes;
2318 }
2319
2320 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2321 {
2322     int i;
2323
2324     if (ms->possible_cpus) {
2325         /*
2326          * make sure that max_cpus hasn't changed since the first use, i.e.
2327          * -smp hasn't been parsed after it
2328         */
2329         assert(ms->possible_cpus->len == max_cpus);
2330         return ms->possible_cpus;
2331     }
2332
2333     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2334                                   sizeof(CPUArchId) * max_cpus);
2335     ms->possible_cpus->len = max_cpus;
2336     for (i = 0; i < ms->possible_cpus->len; i++) {
2337         X86CPUTopoInfo topo;
2338
2339         ms->possible_cpus->cpus[i].type = ms->cpu_type;
2340         ms->possible_cpus->cpus[i].vcpus_count = 1;
2341         ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
2342         x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2343                                  smp_cores, smp_threads, &topo);
2344         ms->possible_cpus->cpus[i].props.has_socket_id = true;
2345         ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2346         ms->possible_cpus->cpus[i].props.has_core_id = true;
2347         ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2348         ms->possible_cpus->cpus[i].props.has_thread_id = true;
2349         ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2350     }
2351     return ms->possible_cpus;
2352 }
2353
2354 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2355 {
2356     /* cpu index isn't used */
2357     CPUState *cs;
2358
2359     CPU_FOREACH(cs) {
2360         X86CPU *cpu = X86_CPU(cs);
2361
2362         if (!cpu->apic_state) {
2363             cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2364         } else {
2365             apic_deliver_nmi(cpu->apic_state);
2366         }
2367     }
2368 }
2369
2370 static void pc_machine_class_init(ObjectClass *oc, void *data)
2371 {
2372     MachineClass *mc = MACHINE_CLASS(oc);
2373     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2374     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2375     NMIClass *nc = NMI_CLASS(oc);
2376
2377     pcmc->pci_enabled = true;
2378     pcmc->has_acpi_build = true;
2379     pcmc->rsdp_in_ram = true;
2380     pcmc->smbios_defaults = true;
2381     pcmc->smbios_uuid_encoded = true;
2382     pcmc->gigabyte_align = true;
2383     pcmc->has_reserved_memory = true;
2384     pcmc->kvmclock_enabled = true;
2385     pcmc->enforce_aligned_dimm = true;
2386     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2387      * to be used at the moment, 32K should be enough for a while.  */
2388     pcmc->acpi_data_size = 0x20000 + 0x8000;
2389     pcmc->save_tsc_khz = true;
2390     pcmc->linuxboot_dma_enabled = true;
2391     assert(!mc->get_hotplug_handler);
2392     mc->get_hotplug_handler = pc_get_hotpug_handler;
2393     mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2394     mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2395     mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2396     mc->auto_enable_numa_with_memhp = true;
2397     mc->has_hotpluggable_cpus = true;
2398     mc->default_boot_order = "cad";
2399     mc->hot_add_cpu = pc_hot_add_cpu;
2400     mc->block_default_type = IF_IDE;
2401     mc->max_cpus = 255;
2402     mc->reset = pc_machine_reset;
2403     hc->pre_plug = pc_machine_device_pre_plug_cb;
2404     hc->plug = pc_machine_device_plug_cb;
2405     hc->unplug_request = pc_machine_device_unplug_request_cb;
2406     hc->unplug = pc_machine_device_unplug_cb;
2407     nc->nmi_monitor_handler = x86_nmi;
2408     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2409
2410     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2411         pc_machine_get_device_memory_region_size, NULL,
2412         NULL, NULL, &error_abort);
2413
2414     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2415         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2416         NULL, NULL, &error_abort);
2417
2418     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2419         "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2420
2421     object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2422         pc_machine_get_smm, pc_machine_set_smm,
2423         NULL, NULL, &error_abort);
2424     object_class_property_set_description(oc, PC_MACHINE_SMM,
2425         "Enable SMM (pc & q35)", &error_abort);
2426
2427     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2428         pc_machine_get_vmport, pc_machine_set_vmport,
2429         NULL, NULL, &error_abort);
2430     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2431         "Enable vmport (pc & q35)", &error_abort);
2432
2433     object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2434         pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2435
2436     object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST,
2437         pc_machine_get_nvdimm_persistence,
2438         pc_machine_set_nvdimm_persistence, &error_abort);
2439
2440     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2441         pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2442
2443     object_class_property_add_bool(oc, PC_MACHINE_SATA,
2444         pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2445
2446     object_class_property_add_bool(oc, PC_MACHINE_PIT,
2447         pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2448 }
2449
2450 static const TypeInfo pc_machine_info = {
2451     .name = TYPE_PC_MACHINE,
2452     .parent = TYPE_MACHINE,
2453     .abstract = true,
2454     .instance_size = sizeof(PCMachineState),
2455     .instance_init = pc_machine_initfn,
2456     .class_size = sizeof(PCMachineClass),
2457     .class_init = pc_machine_class_init,
2458     .interfaces = (InterfaceInfo[]) {
2459          { TYPE_HOTPLUG_HANDLER },
2460          { TYPE_NMI },
2461          { }
2462     },
2463 };
2464
2465 static void pc_machine_register_types(void)
2466 {
2467     type_register_static(&pc_machine_info);
2468 }
2469
2470 type_init(pc_machine_register_types)