hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/units.h"
  33 #include "hw/loader.h"
  34 #include "sysemu/arch_init.h"
  35 #include "hw/i2c/smbus_eeprom.h"
  36 #include "hw/rtc/mc146818rtc.h"
  37 #include "hw/xen/xen.h"
  38 #include "sysemu/kvm.h"
  39 #include "hw/kvm/clock.h"
  40 #include "hw/pci-host/q35.h"
  41 #include "hw/qdev-properties.h"
  42 #include "exec/address-spaces.h"
  43 #include "hw/i386/x86.h"
  44 #include "hw/i386/pc.h"
  45 #include "hw/i386/ich9.h"
  46 #include "hw/i386/amd_iommu.h"
  47 #include "hw/i386/intel_iommu.h"
  48 #include "hw/display/ramfb.h"
  49 #include "hw/firmware/smbios.h"
  50 #include "hw/ide/pci.h"
  51 #include "hw/ide/ahci.h"
  52 #include "hw/usb.h"
  53 #include "qapi/error.h"
  54 #include "qemu/error-report.h"
  55 #include "sysemu/numa.h"
  56 #include "hw/mem/nvdimm.h"
  57 #include "hw/i386/acpi-build.h"
  58
  59 /* ICH9 AHCI has 6 ports */
  60 #define MAX_SATA_PORTS     6
  61
  62 struct ehci_companions {
  63     const char *name;
  64     int func;
  65     int port;
  66 };
  67
  68 static const struct ehci_companions ich9_1d[] = {
  69     { .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
  70     { .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
  71     { .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
  72 };
  73
  74 static const struct ehci_companions ich9_1a[] = {
  75     { .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
  76     { .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
  77     { .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
  78 };
  79
  80 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
  81 {
  82     const struct ehci_companions *comp;
  83     PCIDevice *ehci, *uhci;
  84     BusState *usbbus;
  85     const char *name;
  86     int i;
  87
  88     switch (slot) {
  89     case 0x1d:
  90         name = "ich9-usb-ehci1";
  91         comp = ich9_1d;
  92         break;
  93     case 0x1a:
  94         name = "ich9-usb-ehci2";
  95         comp = ich9_1a;
  96         break;
  97     default:
  98         return -1;
  99     }
 100
 101     ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name);
 102     qdev_init_nofail(&ehci->qdev);
 103     usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
 104
 105     for (i = 0; i < 3; i++) {
 106         uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func),
 107                                         true, comp[i].name);
 108         qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
 109         qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
 110         qdev_init_nofail(&uhci->qdev);
 111     }
 112     return 0;
 113 }
 114
 115 /* PC hardware initialisation */
 116 static void pc_q35_init(MachineState *machine)
 117 {
 118     PCMachineState *pcms = PC_MACHINE(machine);
 119     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 120     X86MachineState *x86ms = X86_MACHINE(machine);
 121     Q35PCIHost *q35_host;
 122     PCIHostState *phb;
 123     PCIBus *host_bus;
 124     PCIDevice *lpc;
 125     DeviceState *lpc_dev;
 126     BusState *idebus[MAX_SATA_PORTS];
 127     ISADevice *rtc_state;
 128     MemoryRegion *system_io = get_system_io();
 129     MemoryRegion *pci_memory;
 130     MemoryRegion *rom_memory;
 131     MemoryRegion *ram_memory;
 132     GSIState *gsi_state;
 133     ISABus *isa_bus;
 134     int i;
 135     ICH9LPCState *ich9_lpc;
 136     PCIDevice *ahci;
 137     ram_addr_t lowmem;
 138     DriveInfo *hd[MAX_SATA_PORTS];
 139     MachineClass *mc = MACHINE_GET_CLASS(machine);
 140
 141     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
 142      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
 143      * also known as MMCFG).
 144      * If it doesn't, we need to split it in chunks below and above 4G.
 145      * In any case, try to make sure that guest addresses aligned at
 146      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
 147      */
 148     if (machine->ram_size >= 0xb0000000) {
 149         lowmem = 0x80000000;
 150     } else {
 151         lowmem = 0xb0000000;
 152     }
 153
 154     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 155      * min(qemu limit, user limit).
 156      */
 157     if (!x86ms->max_ram_below_4g) {
 158         x86ms->max_ram_below_4g = 4 * GiB;
 159     }
 160     if (lowmem > x86ms->max_ram_below_4g) {
 161         lowmem = x86ms->max_ram_below_4g;
 162         if (machine->ram_size - lowmem > lowmem &&
 163             lowmem & (1 * GiB - 1)) {
 164             warn_report("There is possibly poor performance as the ram size "
 165                         " (0x%" PRIx64 ") is more then twice the size of"
 166                         " max-ram-below-4g (%"PRIu64") and"
 167                         " max-ram-below-4g is not a multiple of 1G.",
 168                         (uint64_t)machine->ram_size, x86ms->max_ram_below_4g);
 169         }
 170     }
 171
 172     if (machine->ram_size >= lowmem) {
 173         x86ms->above_4g_mem_size = machine->ram_size - lowmem;
 174         x86ms->below_4g_mem_size = lowmem;
 175     } else {
 176         x86ms->above_4g_mem_size = 0;
 177         x86ms->below_4g_mem_size = machine->ram_size;
 178     }
 179
 180     if (xen_enabled()) {
 181         xen_hvm_init(pcms, &ram_memory);
 182     }
 183
 184     x86_cpus_init(x86ms, pcmc->default_cpu_version);
 185
 186     kvmclock_create();
 187
 188     /* pci enabled */
 189     if (pcmc->pci_enabled) {
 190         pci_memory = g_new(MemoryRegion, 1);
 191         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 192         rom_memory = pci_memory;
 193     } else {
 194         pci_memory = NULL;
 195         rom_memory = get_system_memory();
 196     }
 197
 198     pc_guest_info_init(pcms);
 199
 200     if (pcmc->smbios_defaults) {
 201         /* These values are guest ABI, do not change */
 202         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 203                             mc->name, pcmc->smbios_legacy_mode,
 204                             pcmc->smbios_uuid_encoded,
 205                             SMBIOS_ENTRY_POINT_21);
 206     }
 207
 208     /* allocate ram and load rom/bios */
 209     if (!xen_enabled()) {
 210         pc_memory_init(pcms, get_system_memory(),
 211                        rom_memory, &ram_memory);
 212     }
 213
 214     /* create pci host bus */
 215     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 216
 217     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 218     object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
 219                              MCH_HOST_PROP_RAM_MEM, NULL);
 220     object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
 221                              MCH_HOST_PROP_PCI_MEM, NULL);
 222     object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
 223                              MCH_HOST_PROP_SYSTEM_MEM, NULL);
 224     object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
 225                              MCH_HOST_PROP_IO_MEM, NULL);
 226     object_property_set_int(OBJECT(q35_host), x86ms->below_4g_mem_size,
 227                             PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
 228     object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size,
 229                             PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
 230     /* pci */
 231     qdev_init_nofail(DEVICE(q35_host));
 232     phb = PCI_HOST_BRIDGE(q35_host);
 233     host_bus = phb->bus;
 234     /* create ISA bus */
 235     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 236                                           ICH9_LPC_FUNC), true,
 237                                           TYPE_ICH9_LPC_DEVICE);
 238
 239     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 240                              TYPE_HOTPLUG_HANDLER,
 241                              (Object **)&pcms->acpi_dev,
 242                              object_property_allow_set_link,
 243                              OBJ_PROP_LINK_STRONG, &error_abort);
 244     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 245                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 246
 247     /* irq lines */
 248     gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
 249
 250     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 251     lpc_dev = DEVICE(lpc);
 252     for (i = 0; i < GSI_NUM_PINS; i++) {
 253         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
 254     }
 255     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 256                  ICH9_LPC_NB_PIRQS);
 257     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 258     isa_bus = ich9_lpc->isa_bus;
 259
 260     pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 261
 262     if (pcmc->pci_enabled) {
 263         ioapic_init_gsi(gsi_state, "q35");
 264     }
 265
 266     if (tcg_enabled()) {
 267         x86_register_ferr_irq(x86ms->gsi[13]);
 268     }
 269
 270     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 271     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 272         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 273     }
 274
 275     /* init basic PC hardware */
 276     pc_basic_device_init(isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
 277                          (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled,
 278                          0xff0104);
 279
 280     /* connect pm stuff to lpc */
 281     ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
 282
 283     if (pcms->sata_enabled) {
 284         /* ahci and SATA device, for q35 1 ahci controller is built-in */
 285         ahci = pci_create_simple_multifunction(host_bus,
 286                                                PCI_DEVFN(ICH9_SATA1_DEV,
 287                                                          ICH9_SATA1_FUNC),
 288                                                true, "ich9-ahci");
 289         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 290         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 291         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 292         ide_drive_get(hd, ahci_get_num_ports(ahci));
 293         ahci_ide_create_devs(ahci, hd);
 294     } else {
 295         idebus[0] = idebus[1] = NULL;
 296     }
 297
 298     if (machine_usb(machine)) {
 299         /* Should we create 6 UHCI according to ich9 spec? */
 300         ehci_create_ich9_with_companions(host_bus, 0x1d);
 301     }
 302
 303     if (pcms->smbus_enabled) {
 304         /* TODO: Populate SPD eeprom data.  */
 305         pcms->smbus = ich9_smb_init(host_bus,
 306                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 307                                     0xb100);
 308         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
 309     }
 310
 311     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 312
 313     /* the rest devices to which pci devfn is automatically assigned */
 314     pc_vga_init(isa_bus, host_bus);
 315     pc_nic_init(pcmc, isa_bus, host_bus);
 316
 317     if (machine->nvdimms_state->is_enabled) {
 318         nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
 319                                x86_nvdimm_acpi_dsmio,
 320                                x86ms->fw_cfg, OBJECT(pcms));
 321     }
 322 }
 323
 324 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 325     static void pc_init_##suffix(MachineState *machine) \
 326     { \
 327         void (*compat)(MachineState *m) = (compatfn); \
 328         if (compat) { \
 329             compat(machine); \
 330         } \
 331         pc_q35_init(machine); \
 332     } \
 333     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 334
 335
 336 static void pc_q35_machine_options(MachineClass *m)
 337 {
 338     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 339     pcmc->default_nic_model = "e1000e";
 340
 341     m->family = "pc_q35";
 342     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 343     m->units_per_default_bus = 1;
 344     m->default_machine_opts = "firmware=bios-256k.bin";
 345     m->default_display = "std";
 346     m->default_kernel_irqchip_split = false;
 347     m->no_floppy = 1;
 348     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 349     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 350     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
 351     m->max_cpus = 288;
 352 }
 353
 354 static void pc_q35_5_1_machine_options(MachineClass *m)
 355 {
 356     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 357     pc_q35_machine_options(m);
 358     m->alias = "q35";
 359     pcmc->default_cpu_version = 1;
 360 }
 361
 362 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
 363                    pc_q35_5_1_machine_options);
 364
 365 static void pc_q35_5_0_machine_options(MachineClass *m)
 366 {
 367     pc_q35_5_1_machine_options(m);
 368     m->alias = NULL;
 369     compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
 370     compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
 371 }
 372
 373 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
 374                    pc_q35_5_0_machine_options);
 375
 376 static void pc_q35_4_2_machine_options(MachineClass *m)
 377 {
 378     pc_q35_5_0_machine_options(m);
 379     m->alias = NULL;
 380     compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
 381     compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
 382 }
 383
 384 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
 385                    pc_q35_4_2_machine_options);
 386
 387 static void pc_q35_4_1_machine_options(MachineClass *m)
 388 {
 389     pc_q35_4_2_machine_options(m);
 390     m->alias = NULL;
 391     compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
 392     compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
 393 }
 394
 395 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
 396                    pc_q35_4_1_machine_options);
 397
 398 static void pc_q35_4_0_1_machine_options(MachineClass *m)
 399 {
 400     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 401     pc_q35_4_1_machine_options(m);
 402     m->alias = NULL;
 403     pcmc->default_cpu_version = CPU_VERSION_LEGACY;
 404     /*
 405      * This is the default machine for the 4.0-stable branch. It is basically
 406      * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
 407      * 4.0 compat props.
 408      */
 409     compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
 410     compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
 411 }
 412
 413 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
 414                    pc_q35_4_0_1_machine_options);
 415
 416 static void pc_q35_4_0_machine_options(MachineClass *m)
 417 {
 418     pc_q35_4_0_1_machine_options(m);
 419     m->default_kernel_irqchip_split = true;
 420     m->alias = NULL;
 421     /* Compat props are applied by the 4.0.1 machine */
 422 }
 423
 424 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
 425                    pc_q35_4_0_machine_options);
 426
 427 static void pc_q35_3_1_machine_options(MachineClass *m)
 428 {
 429     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 430
 431     pc_q35_4_0_machine_options(m);
 432     m->default_kernel_irqchip_split = false;
 433     pcmc->do_not_add_smb_acpi = true;
 434     m->smbus_no_migration_support = true;
 435     m->alias = NULL;
 436     pcmc->pvh_enabled = false;
 437     compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
 438     compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
 439 }
 440
 441 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
 442                    pc_q35_3_1_machine_options);
 443
 444 static void pc_q35_3_0_machine_options(MachineClass *m)
 445 {
 446     pc_q35_3_1_machine_options(m);
 447     compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
 448     compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
 449 }
 450
 451 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
 452                     pc_q35_3_0_machine_options);
 453
 454 static void pc_q35_2_12_machine_options(MachineClass *m)
 455 {
 456     pc_q35_3_0_machine_options(m);
 457     compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
 458     compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
 459 }
 460
 461 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 462                    pc_q35_2_12_machine_options);
 463
 464 static void pc_q35_2_11_machine_options(MachineClass *m)
 465 {
 466     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 467
 468     pc_q35_2_12_machine_options(m);
 469     pcmc->default_nic_model = "e1000";
 470     compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
 471     compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
 472 }
 473
 474 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 475                    pc_q35_2_11_machine_options);
 476
 477 static void pc_q35_2_10_machine_options(MachineClass *m)
 478 {
 479     pc_q35_2_11_machine_options(m);
 480     compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
 481     compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
 482     m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
 483     m->auto_enable_numa_with_memhp = false;
 484 }
 485
 486 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 487                    pc_q35_2_10_machine_options);
 488
 489 static void pc_q35_2_9_machine_options(MachineClass *m)
 490 {
 491     pc_q35_2_10_machine_options(m);
 492     compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
 493     compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
 494 }
 495
 496 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 497                    pc_q35_2_9_machine_options);
 498
 499 static void pc_q35_2_8_machine_options(MachineClass *m)
 500 {
 501     pc_q35_2_9_machine_options(m);
 502     compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
 503     compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
 504 }
 505
 506 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 507                    pc_q35_2_8_machine_options);
 508
 509 static void pc_q35_2_7_machine_options(MachineClass *m)
 510 {
 511     pc_q35_2_8_machine_options(m);
 512     m->max_cpus = 255;
 513     compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
 514     compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
 515 }
 516
 517 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 518                    pc_q35_2_7_machine_options);
 519
 520 static void pc_q35_2_6_machine_options(MachineClass *m)
 521 {
 522     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 523
 524     pc_q35_2_7_machine_options(m);
 525     pcmc->legacy_cpu_hotplug = true;
 526     pcmc->linuxboot_dma_enabled = false;
 527     compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
 528     compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
 529 }
 530
 531 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 532                    pc_q35_2_6_machine_options);
 533
 534 static void pc_q35_2_5_machine_options(MachineClass *m)
 535 {
 536     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
 537
 538     pc_q35_2_6_machine_options(m);
 539     x86mc->save_tsc_khz = false;
 540     m->legacy_fw_cfg_order = 1;
 541     compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
 542     compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
 543 }
 544
 545 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 546                    pc_q35_2_5_machine_options);
 547
 548 static void pc_q35_2_4_machine_options(MachineClass *m)
 549 {
 550     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 551
 552     pc_q35_2_5_machine_options(m);
 553     m->hw_version = "2.4.0";
 554     pcmc->broken_reserved_end = true;
 555     compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
 556     compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
 557 }
 558
 559 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 560                    pc_q35_2_4_machine_options);