hw/isa/piix4.c

   1 /*
   2  * QEMU PIIX4 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qapi/error.h"
  28 #include "hw/irq.h"
  29 #include "hw/southbridge/piix.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/sysbus.h"
  33 #include "hw/intc/i8259.h"
  34 #include "hw/dma/i8257.h"
  35 #include "hw/timer/i8254.h"
  36 #include "hw/rtc/mc146818rtc.h"
  37 #include "hw/ide.h"
  38 #include "migration/vmstate.h"
  39 #include "sysemu/reset.h"
  40 #include "sysemu/runstate.h"
  41
  42 PCIDevice *piix4_dev;
  43
  44 typedef struct PIIX4State {
  45     PCIDevice dev;
  46     qemu_irq cpu_intr;
  47     qemu_irq *isa;
  48
  49     RTCState rtc;
  50     /* Reset Control Register */
  51     MemoryRegion rcr_mem;
  52     uint8_t rcr;
  53 } PIIX4State;
  54
  55 #define PIIX4_PCI_DEVICE(obj) \
  56     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
  57
  58 static void piix4_isa_reset(DeviceState *dev)
  59 {
  60     PIIX4State *d = PIIX4_PCI_DEVICE(dev);
  61     uint8_t *pci_conf = d->dev.config;
  62
  63     pci_conf[0x04] = 0x07; // master, memory and I/O
  64     pci_conf[0x05] = 0x00;
  65     pci_conf[0x06] = 0x00;
  66     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
  67     pci_conf[0x4c] = 0x4d;
  68     pci_conf[0x4e] = 0x03;
  69     pci_conf[0x4f] = 0x00;
  70     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
  71     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
  72     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
  73     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
  74     pci_conf[0x69] = 0x02;
  75     pci_conf[0x70] = 0x80;
  76     pci_conf[0x76] = 0x0c;
  77     pci_conf[0x77] = 0x0c;
  78     pci_conf[0x78] = 0x02;
  79     pci_conf[0x79] = 0x00;
  80     pci_conf[0x80] = 0x00;
  81     pci_conf[0x82] = 0x00;
  82     pci_conf[0xa0] = 0x08;
  83     pci_conf[0xa2] = 0x00;
  84     pci_conf[0xa3] = 0x00;
  85     pci_conf[0xa4] = 0x00;
  86     pci_conf[0xa5] = 0x00;
  87     pci_conf[0xa6] = 0x00;
  88     pci_conf[0xa7] = 0x00;
  89     pci_conf[0xa8] = 0x0f;
  90     pci_conf[0xaa] = 0x00;
  91     pci_conf[0xab] = 0x00;
  92     pci_conf[0xac] = 0x00;
  93     pci_conf[0xae] = 0x00;
  94 }
  95
  96 static const VMStateDescription vmstate_piix4 = {
  97     .name = "PIIX4",
  98     .version_id = 2,
  99     .minimum_version_id = 2,
 100     .fields = (VMStateField[]) {
 101         VMSTATE_PCI_DEVICE(dev, PIIX4State),
 102         VMSTATE_END_OF_LIST()
 103     }
 104 };
 105
 106 static void piix4_request_i8259_irq(void *opaque, int irq, int level)
 107 {
 108     PIIX4State *s = opaque;
 109     qemu_set_irq(s->cpu_intr, level);
 110 }
 111
 112 static void piix4_set_i8259_irq(void *opaque, int irq, int level)
 113 {
 114     PIIX4State *s = opaque;
 115     qemu_set_irq(s->isa[irq], level);
 116 }
 117
 118 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
 119                             unsigned int len)
 120 {
 121     PIIX4State *s = opaque;
 122
 123     if (val & 4) {
 124         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 125         return;
 126     }
 127
 128     s->rcr = val & 2; /* keep System Reset type only */
 129 }
 130
 131 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
 132 {
 133     PIIX4State *s = opaque;
 134
 135     return s->rcr;
 136 }
 137
 138 static const MemoryRegionOps piix4_rcr_ops = {
 139     .read = piix4_rcr_read,
 140     .write = piix4_rcr_write,
 141     .endianness = DEVICE_LITTLE_ENDIAN,
 142     .impl = {
 143         .min_access_size = 1,
 144         .max_access_size = 1,
 145     },
 146 };
 147
 148 static void piix4_realize(PCIDevice *dev, Error **errp)
 149 {
 150     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
 151     ISABus *isa_bus;
 152     qemu_irq *i8259_out_irq;
 153     Error *err = NULL;
 154
 155     isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
 156                           pci_address_space_io(dev), errp);
 157     if (!isa_bus) {
 158         return;
 159     }
 160
 161     qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
 162                             "isa", ISA_NUM_IRQS);
 163     qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
 164                              "intr", 1);
 165
 166     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
 167                           "reset-control", 1);
 168     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 169                                         PIIX_RCR_IOPORT, &s->rcr_mem, 1);
 170
 171     /* initialize i8259 pic */
 172     i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
 173     s->isa = i8259_init(isa_bus, *i8259_out_irq);
 174
 175     /* initialize ISA irqs */
 176     isa_bus_irqs(isa_bus, s->isa);
 177
 178     /* initialize pit */
 179     i8254_pit_init(isa_bus, 0x40, 0, NULL);
 180
 181     /* DMA */
 182     i8257_dma_init(isa_bus, 0);
 183
 184     /* RTC */
 185     qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
 186     qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
 187     object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
 188     if (err) {
 189         error_propagate(errp, err);
 190         return;
 191     }
 192     isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
 193
 194     piix4_dev = dev;
 195 }
 196
 197 static void piix4_init(Object *obj)
 198 {
 199     PIIX4State *s = PIIX4_PCI_DEVICE(obj);
 200
 201     object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
 202 }
 203
 204 static void piix4_class_init(ObjectClass *klass, void *data)
 205 {
 206     DeviceClass *dc = DEVICE_CLASS(klass);
 207     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 208
 209     k->realize = piix4_realize;
 210     k->vendor_id = PCI_VENDOR_ID_INTEL;
 211     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
 212     k->class_id = PCI_CLASS_BRIDGE_ISA;
 213     dc->reset = piix4_isa_reset;
 214     dc->desc = "ISA bridge";
 215     dc->vmsd = &vmstate_piix4;
 216     /*
 217      * Reason: part of PIIX4 southbridge, needs to be wired up,
 218      * e.g. by mips_malta_init()
 219      */
 220     dc->user_creatable = false;
 221     dc->hotpluggable = false;
 222 }
 223
 224 static const TypeInfo piix4_info = {
 225     .name          = TYPE_PIIX4_PCI_DEVICE,
 226     .parent        = TYPE_PCI_DEVICE,
 227     .instance_size = sizeof(PIIX4State),
 228     .instance_init = piix4_init,
 229     .class_init    = piix4_class_init,
 230     .interfaces = (InterfaceInfo[]) {
 231         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 232         { },
 233     },
 234 };
 235
 236 static void piix4_register_types(void)
 237 {
 238     type_register_static(&piix4_info);
 239 }
 240
 241 type_init(piix4_register_types)
 242
 243 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
 244                           I2CBus **smbus, size_t ide_buses)
 245 {
 246     size_t ide_drives = ide_buses * MAX_IDE_DEVS;
 247     DriveInfo **hd;
 248     PCIDevice *pci;
 249     DeviceState *dev;
 250
 251     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
 252                                           true, TYPE_PIIX4_PCI_DEVICE);
 253     dev = DEVICE(pci);
 254     if (isa_bus) {
 255         *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
 256     }
 257
 258     hd = g_new(DriveInfo *, ide_drives);
 259     ide_drive_get(hd, ide_drives);
 260     pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
 261     g_free(hd);
 262     pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
 263     if (smbus) {
 264         *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
 265                                isa_get_irq(NULL, 9), NULL, 0, NULL);
 266    }
 267
 268     return dev;
 269 }