hw/misc/zynq-xadc.c

   1 /*
   2  * ADC registers for Xilinx Zynq Platform
   3  *
   4  * Copyright (c) 2015 Guenter Roeck
   5  * Based on hw/misc/zynq_slcr.c, written by Michal Simek
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  *
  12  * You should have received a copy of the GNU General Public License along
  13  * with this program; if not, see <http://www.gnu.org/licenses/>.
  14  */
  15
  16 #include "qemu/osdep.h"
  17 #include "hw/irq.h"
  18 #include "hw/misc/zynq-xadc.h"
  19 #include "migration/vmstate.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24
  25 enum {
  26     CFG                = 0x000 / 4,
  27     INT_STS,
  28     INT_MASK,
  29     MSTS,
  30     CMDFIFO,
  31     RDFIFO,
  32     MCTL,
  33 };
  34
  35 #define CFG_ENABLE              BIT(31)
  36 #define CFG_CFIFOTH_SHIFT       20
  37 #define CFG_CFIFOTH_LENGTH      4
  38 #define CFG_DFIFOTH_SHIFT       16
  39 #define CFG_DFIFOTH_LENGTH      4
  40 #define CFG_WEDGE               BIT(13)
  41 #define CFG_REDGE               BIT(12)
  42 #define CFG_TCKRATE_SHIFT       8
  43 #define CFG_TCKRATE_LENGTH      2
  44
  45 #define CFG_TCKRATE_DIV(x)      (0x1 << (x - 1))
  46
  47 #define CFG_IGAP_SHIFT          0
  48 #define CFG_IGAP_LENGTH         5
  49
  50 #define INT_CFIFO_LTH           BIT(9)
  51 #define INT_DFIFO_GTH           BIT(8)
  52 #define INT_OT                  BIT(7)
  53 #define INT_ALM_SHIFT           0
  54 #define INT_ALM_LENGTH          7
  55 #define INT_ALM_MASK            (((1 << INT_ALM_LENGTH) - 1) << INT_ALM_SHIFT)
  56
  57 #define INT_ALL (INT_CFIFO_LTH | INT_DFIFO_GTH | INT_OT | INT_ALM_MASK)
  58
  59 #define MSTS_CFIFO_LVL_SHIFT    16
  60 #define MSTS_CFIFO_LVL_LENGTH   4
  61 #define MSTS_DFIFO_LVL_SHIFT    12
  62 #define MSTS_DFIFO_LVL_LENGTH   4
  63 #define MSTS_CFIFOF             BIT(11)
  64 #define MSTS_CFIFOE             BIT(10)
  65 #define MSTS_DFIFOF             BIT(9)
  66 #define MSTS_DFIFOE             BIT(8)
  67 #define MSTS_OT                 BIT(7)
  68 #define MSTS_ALM_SHIFT          0
  69 #define MSTS_ALM_LENGTH         7
  70
  71 #define MCTL_RESET              BIT(4)
  72
  73 #define CMD_NOP                 0x00
  74 #define CMD_READ                0x01
  75 #define CMD_WRITE               0x02
  76
  77 static void zynq_xadc_update_ints(ZynqXADCState *s)
  78 {
  79
  80     /* We are fast, commands are actioned instantly so the CFIFO is always
  81      * empty (and below threshold).
  82      */
  83     s->regs[INT_STS] |= INT_CFIFO_LTH;
  84
  85     if (s->xadc_dfifo_entries >
  86         extract32(s->regs[CFG], CFG_DFIFOTH_SHIFT, CFG_DFIFOTH_LENGTH)) {
  87         s->regs[INT_STS] |= INT_DFIFO_GTH;
  88     }
  89
  90     qemu_set_irq(s->qemu_irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK]));
  91 }
  92
  93 static void zynq_xadc_reset(DeviceState *d)
  94 {
  95     ZynqXADCState *s = ZYNQ_XADC(d);
  96
  97     s->regs[CFG] = 0x14 << CFG_IGAP_SHIFT |
  98                    CFG_TCKRATE_DIV(4) << CFG_TCKRATE_SHIFT | CFG_REDGE;
  99     s->regs[INT_STS] = INT_CFIFO_LTH;
 100     s->regs[INT_MASK] = 0xffffffff;
 101     s->regs[CMDFIFO] = 0;
 102     s->regs[RDFIFO] = 0;
 103     s->regs[MCTL] = MCTL_RESET;
 104
 105     memset(s->xadc_regs, 0, sizeof(s->xadc_regs));
 106     memset(s->xadc_dfifo, 0, sizeof(s->xadc_dfifo));
 107     s->xadc_dfifo_entries = 0;
 108
 109     zynq_xadc_update_ints(s);
 110 }
 111
 112 static uint16_t xadc_pop_dfifo(ZynqXADCState *s)
 113 {
 114     uint16_t rv = s->xadc_dfifo[0];
 115     int i;
 116
 117     if (s->xadc_dfifo_entries > 0) {
 118         s->xadc_dfifo_entries--;
 119     }
 120     for (i = 0; i < s->xadc_dfifo_entries; i++) {
 121         s->xadc_dfifo[i] = s->xadc_dfifo[i + 1];
 122     }
 123     s->xadc_dfifo[s->xadc_dfifo_entries] = 0;
 124     zynq_xadc_update_ints(s);
 125     return rv;
 126 }
 127
 128 static void xadc_push_dfifo(ZynqXADCState *s, uint16_t regval)
 129 {
 130     if (s->xadc_dfifo_entries < ZYNQ_XADC_FIFO_DEPTH) {
 131         s->xadc_dfifo[s->xadc_dfifo_entries++] = s->xadc_read_reg_previous;
 132     }
 133     s->xadc_read_reg_previous = regval;
 134     zynq_xadc_update_ints(s);
 135 }
 136
 137 static bool zynq_xadc_check_offset(hwaddr offset, bool rnw)
 138 {
 139     switch (offset) {
 140     case CFG:
 141     case INT_MASK:
 142     case INT_STS:
 143     case MCTL:
 144         return true;
 145     case RDFIFO:
 146     case MSTS:
 147         return rnw;     /* read only */
 148     case CMDFIFO:
 149         return !rnw;    /* write only */
 150     default:
 151         return false;
 152     }
 153 }
 154
 155 static uint64_t zynq_xadc_read(void *opaque, hwaddr offset, unsigned size)
 156 {
 157     ZynqXADCState *s = opaque;
 158     int reg = offset / 4;
 159     uint32_t rv = 0;
 160
 161     if (!zynq_xadc_check_offset(reg, true)) {
 162         qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid read access to "
 163                       "addr %" HWADDR_PRIx "\n", offset);
 164         return 0;
 165     }
 166
 167     switch (reg) {
 168     case CFG:
 169     case INT_MASK:
 170     case INT_STS:
 171     case MCTL:
 172         rv = s->regs[reg];
 173         break;
 174     case MSTS:
 175         rv = MSTS_CFIFOE;
 176         rv |= s->xadc_dfifo_entries << MSTS_DFIFO_LVL_SHIFT;
 177         if (!s->xadc_dfifo_entries) {
 178             rv |= MSTS_DFIFOE;
 179         } else if (s->xadc_dfifo_entries == ZYNQ_XADC_FIFO_DEPTH) {
 180             rv |= MSTS_DFIFOF;
 181         }
 182         break;
 183     case RDFIFO:
 184         rv = xadc_pop_dfifo(s);
 185         break;
 186     }
 187     return rv;
 188 }
 189
 190 static void zynq_xadc_write(void *opaque, hwaddr offset, uint64_t val,
 191                             unsigned size)
 192 {
 193     ZynqXADCState *s = (ZynqXADCState *)opaque;
 194     int reg = offset / 4;
 195     int xadc_reg;
 196     int xadc_cmd;
 197     int xadc_data;
 198
 199     if (!zynq_xadc_check_offset(reg, false)) {
 200         qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "
 201                       "to addr %" HWADDR_PRIx "\n", offset);
 202         return;
 203     }
 204
 205     switch (reg) {
 206     case CFG:
 207         s->regs[CFG] = val;
 208         break;
 209     case INT_STS:
 210         s->regs[INT_STS] &= ~val;
 211         break;
 212     case INT_MASK:
 213         s->regs[INT_MASK] = val & INT_ALL;
 214         break;
 215     case CMDFIFO:
 216         xadc_cmd  = extract32(val, 26,  4);
 217         xadc_reg  = extract32(val, 16, 10);
 218         xadc_data = extract32(val,  0, 16);
 219
 220         if (s->regs[MCTL] & MCTL_RESET) {
 221             qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "
 222                           "while comm channel held in reset: %" PRIx32 "\n",
 223                           (uint32_t) val);
 224             break;
 225         }
 226
 227         if (xadc_reg >= ZYNQ_XADC_NUM_ADC_REGS && xadc_cmd != CMD_NOP) {
 228             qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "
 229                           "reg 0x%x\n", xadc_reg);
 230             break;
 231         }
 232
 233         switch (xadc_cmd) {
 234         case CMD_READ:
 235             xadc_push_dfifo(s, s->xadc_regs[xadc_reg]);
 236             break;
 237         case CMD_WRITE:
 238             s->xadc_regs[xadc_reg] = xadc_data;
 239             /* fallthrough */
 240         case CMD_NOP:
 241             xadc_push_dfifo(s, 0);
 242             break;
 243         }
 244         break;
 245     case MCTL:
 246         s->regs[MCTL] = val & 0x00fffeff;
 247         break;
 248     }
 249     zynq_xadc_update_ints(s);
 250 }
 251
 252 static const MemoryRegionOps xadc_ops = {
 253     .read = zynq_xadc_read,
 254     .write = zynq_xadc_write,
 255     .endianness = DEVICE_NATIVE_ENDIAN,
 256 };
 257
 258 static void zynq_xadc_init(Object *obj)
 259 {
 260     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 261     ZynqXADCState *s = ZYNQ_XADC(obj);
 262
 263     memory_region_init_io(&s->iomem, obj, &xadc_ops, s, "zynq-xadc",
 264                           ZYNQ_XADC_MMIO_SIZE);
 265     sysbus_init_mmio(sbd, &s->iomem);
 266     sysbus_init_irq(sbd, &s->qemu_irq);
 267 }
 268
 269 static const VMStateDescription vmstate_zynq_xadc = {
 270     .name = "zynq-xadc",
 271     .version_id = 1,
 272     .minimum_version_id = 1,
 273     .fields = (VMStateField[]) {
 274         VMSTATE_UINT32_ARRAY(regs, ZynqXADCState, ZYNQ_XADC_NUM_IO_REGS),
 275         VMSTATE_UINT16_ARRAY(xadc_regs, ZynqXADCState,
 276                              ZYNQ_XADC_NUM_ADC_REGS),
 277         VMSTATE_UINT16_ARRAY(xadc_dfifo, ZynqXADCState,
 278                              ZYNQ_XADC_FIFO_DEPTH),
 279         VMSTATE_UINT16(xadc_read_reg_previous, ZynqXADCState),
 280         VMSTATE_UINT16(xadc_dfifo_entries, ZynqXADCState),
 281         VMSTATE_END_OF_LIST()
 282     }
 283 };
 284
 285 static void zynq_xadc_class_init(ObjectClass *klass, void *data)
 286 {
 287     DeviceClass *dc = DEVICE_CLASS(klass);
 288
 289     dc->vmsd = &vmstate_zynq_xadc;
 290     dc->reset = zynq_xadc_reset;
 291 }
 292
 293 static const TypeInfo zynq_xadc_info = {
 294     .class_init = zynq_xadc_class_init,
 295     .name  = TYPE_ZYNQ_XADC,
 296     .parent = TYPE_SYS_BUS_DEVICE,
 297     .instance_size  = sizeof(ZynqXADCState),
 298     .instance_init = zynq_xadc_init,
 299 };
 300
 301 static void zynq_xadc_register_types(void)
 302 {
 303     type_register_static(&zynq_xadc_info);
 304 }
 305
 306 type_init(zynq_xadc_register_types)