hw/net/dp8393x.c

   1 /*
   2  * QEMU NS SONIC DP8393x netcard
   3  *
   4  * Copyright (c) 2008-2009 Herve Poussineau
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/sysbus.h"
  22 #include "hw/devices.h"
  23 #include "net/net.h"
  24 #include "qapi/error.h"
  25 #include "qemu/timer.h"
  26 #include <zlib.h>
  27
  28 //#define DEBUG_SONIC
  29
  30 #define SONIC_PROM_SIZE 0x1000
  31
  32 #ifdef DEBUG_SONIC
  33 #define DPRINTF(fmt, ...) \
  34 do { printf("sonic: " fmt , ##  __VA_ARGS__); } while (0)
  35 static const char* reg_names[] = {
  36     "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
  37     "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
  38     "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
  39     "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
  40     "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
  41     "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
  42     "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
  43     "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
  44 #else
  45 #define DPRINTF(fmt, ...) do {} while (0)
  46 #endif
  47
  48 #define SONIC_ERROR(fmt, ...) \
  49 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  50
  51 #define SONIC_CR     0x00
  52 #define SONIC_DCR    0x01
  53 #define SONIC_RCR    0x02
  54 #define SONIC_TCR    0x03
  55 #define SONIC_IMR    0x04
  56 #define SONIC_ISR    0x05
  57 #define SONIC_UTDA   0x06
  58 #define SONIC_CTDA   0x07
  59 #define SONIC_TPS    0x08
  60 #define SONIC_TFC    0x09
  61 #define SONIC_TSA0   0x0a
  62 #define SONIC_TSA1   0x0b
  63 #define SONIC_TFS    0x0c
  64 #define SONIC_URDA   0x0d
  65 #define SONIC_CRDA   0x0e
  66 #define SONIC_CRBA0  0x0f
  67 #define SONIC_CRBA1  0x10
  68 #define SONIC_RBWC0  0x11
  69 #define SONIC_RBWC1  0x12
  70 #define SONIC_EOBC   0x13
  71 #define SONIC_URRA   0x14
  72 #define SONIC_RSA    0x15
  73 #define SONIC_REA    0x16
  74 #define SONIC_RRP    0x17
  75 #define SONIC_RWP    0x18
  76 #define SONIC_TRBA0  0x19
  77 #define SONIC_TRBA1  0x1a
  78 #define SONIC_LLFA   0x1f
  79 #define SONIC_TTDA   0x20
  80 #define SONIC_CEP    0x21
  81 #define SONIC_CAP2   0x22
  82 #define SONIC_CAP1   0x23
  83 #define SONIC_CAP0   0x24
  84 #define SONIC_CE     0x25
  85 #define SONIC_CDP    0x26
  86 #define SONIC_CDC    0x27
  87 #define SONIC_SR     0x28
  88 #define SONIC_WT0    0x29
  89 #define SONIC_WT1    0x2a
  90 #define SONIC_RSC    0x2b
  91 #define SONIC_CRCT   0x2c
  92 #define SONIC_FAET   0x2d
  93 #define SONIC_MPT    0x2e
  94 #define SONIC_MDT    0x2f
  95 #define SONIC_DCR2   0x3f
  96
  97 #define SONIC_CR_HTX     0x0001
  98 #define SONIC_CR_TXP     0x0002
  99 #define SONIC_CR_RXDIS   0x0004
 100 #define SONIC_CR_RXEN    0x0008
 101 #define SONIC_CR_STP     0x0010
 102 #define SONIC_CR_ST      0x0020
 103 #define SONIC_CR_RST     0x0080
 104 #define SONIC_CR_RRRA    0x0100
 105 #define SONIC_CR_LCAM    0x0200
 106 #define SONIC_CR_MASK    0x03bf
 107
 108 #define SONIC_DCR_DW     0x0020
 109 #define SONIC_DCR_LBR    0x2000
 110 #define SONIC_DCR_EXBUS  0x8000
 111
 112 #define SONIC_RCR_PRX    0x0001
 113 #define SONIC_RCR_LBK    0x0002
 114 #define SONIC_RCR_FAER   0x0004
 115 #define SONIC_RCR_CRCR   0x0008
 116 #define SONIC_RCR_CRS    0x0020
 117 #define SONIC_RCR_LPKT   0x0040
 118 #define SONIC_RCR_BC     0x0080
 119 #define SONIC_RCR_MC     0x0100
 120 #define SONIC_RCR_LB0    0x0200
 121 #define SONIC_RCR_LB1    0x0400
 122 #define SONIC_RCR_AMC    0x0800
 123 #define SONIC_RCR_PRO    0x1000
 124 #define SONIC_RCR_BRD    0x2000
 125 #define SONIC_RCR_RNT    0x4000
 126
 127 #define SONIC_TCR_PTX    0x0001
 128 #define SONIC_TCR_BCM    0x0002
 129 #define SONIC_TCR_FU     0x0004
 130 #define SONIC_TCR_EXC    0x0040
 131 #define SONIC_TCR_CRSL   0x0080
 132 #define SONIC_TCR_NCRS   0x0100
 133 #define SONIC_TCR_EXD    0x0400
 134 #define SONIC_TCR_CRCI   0x2000
 135 #define SONIC_TCR_PINT   0x8000
 136
 137 #define SONIC_ISR_RBE    0x0020
 138 #define SONIC_ISR_RDE    0x0040
 139 #define SONIC_ISR_TC     0x0080
 140 #define SONIC_ISR_TXDN   0x0200
 141 #define SONIC_ISR_PKTRX  0x0400
 142 #define SONIC_ISR_PINT   0x0800
 143 #define SONIC_ISR_LCD    0x1000
 144
 145 #define TYPE_DP8393X "dp8393x"
 146 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X)
 147
 148 typedef struct dp8393xState {
 149     SysBusDevice parent_obj;
 150
 151     /* Hardware */
 152     uint8_t it_shift;
 153     qemu_irq irq;
 154 #ifdef DEBUG_SONIC
 155     int irq_level;
 156 #endif
 157     QEMUTimer *watchdog;
 158     int64_t wt_last_update;
 159     NICConf conf;
 160     NICState *nic;
 161     MemoryRegion mmio;
 162     MemoryRegion prom;
 163
 164     /* Registers */
 165     uint8_t cam[16][6];
 166     uint16_t regs[0x40];
 167
 168     /* Temporaries */
 169     uint8_t tx_buffer[0x10000];
 170     int loopback_packet;
 171
 172     /* Memory access */
 173     void *dma_mr;
 174     AddressSpace as;
 175 } dp8393xState;
 176
 177 /* Accessor functions for values which are formed by
 178  * concatenating two 16 bit device registers. By putting these
 179  * in their own functions with a uint32_t return type we avoid the
 180  * pitfall of implicit sign extension where ((x << 16) | y) is a
 181  * signed 32 bit integer that might get sign-extended to a 64 bit integer.
 182  */
 183 static uint32_t dp8393x_cdp(dp8393xState *s)
 184 {
 185     return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
 186 }
 187
 188 static uint32_t dp8393x_crba(dp8393xState *s)
 189 {
 190     return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
 191 }
 192
 193 static uint32_t dp8393x_crda(dp8393xState *s)
 194 {
 195     return (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA];
 196 }
 197
 198 static uint32_t dp8393x_rbwc(dp8393xState *s)
 199 {
 200     return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
 201 }
 202
 203 static uint32_t dp8393x_rrp(dp8393xState *s)
 204 {
 205     return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
 206 }
 207
 208 static uint32_t dp8393x_tsa(dp8393xState *s)
 209 {
 210     return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
 211 }
 212
 213 static uint32_t dp8393x_ttda(dp8393xState *s)
 214 {
 215     return (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA];
 216 }
 217
 218 static uint32_t dp8393x_wt(dp8393xState *s)
 219 {
 220     return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
 221 }
 222
 223 static void dp8393x_update_irq(dp8393xState *s)
 224 {
 225     int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
 226
 227 #ifdef DEBUG_SONIC
 228     if (level != s->irq_level) {
 229         s->irq_level = level;
 230         if (level) {
 231             DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
 232         } else {
 233             DPRINTF("lower irq\n");
 234         }
 235     }
 236 #endif
 237
 238     qemu_set_irq(s->irq, level);
 239 }
 240
 241 static void dp8393x_do_load_cam(dp8393xState *s)
 242 {
 243     uint16_t data[8];
 244     int width, size;
 245     uint16_t index = 0;
 246
 247     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 248     size = sizeof(uint16_t) * 4 * width;
 249
 250     while (s->regs[SONIC_CDC] & 0x1f) {
 251         /* Fill current entry */
 252         address_space_rw(&s->as, dp8393x_cdp(s),
 253             MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 254         s->cam[index][0] = data[1 * width] & 0xff;
 255         s->cam[index][1] = data[1 * width] >> 8;
 256         s->cam[index][2] = data[2 * width] & 0xff;
 257         s->cam[index][3] = data[2 * width] >> 8;
 258         s->cam[index][4] = data[3 * width] & 0xff;
 259         s->cam[index][5] = data[3 * width] >> 8;
 260         DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
 261             s->cam[index][0], s->cam[index][1], s->cam[index][2],
 262             s->cam[index][3], s->cam[index][4], s->cam[index][5]);
 263         /* Move to next entry */
 264         s->regs[SONIC_CDC]--;
 265         s->regs[SONIC_CDP] += size;
 266         index++;
 267     }
 268
 269     /* Read CAM enable */
 270     address_space_rw(&s->as, dp8393x_cdp(s),
 271         MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 272     s->regs[SONIC_CE] = data[0 * width];
 273     DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
 274
 275     /* Done */
 276     s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
 277     s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
 278     dp8393x_update_irq(s);
 279 }
 280
 281 static void dp8393x_do_read_rra(dp8393xState *s)
 282 {
 283     uint16_t data[8];
 284     int width, size;
 285
 286     /* Read memory */
 287     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 288     size = sizeof(uint16_t) * 4 * width;
 289     address_space_rw(&s->as, dp8393x_rrp(s),
 290         MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 291
 292     /* Update SONIC registers */
 293     s->regs[SONIC_CRBA0] = data[0 * width];
 294     s->regs[SONIC_CRBA1] = data[1 * width];
 295     s->regs[SONIC_RBWC0] = data[2 * width];
 296     s->regs[SONIC_RBWC1] = data[3 * width];
 297     DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
 298         s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
 299         s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
 300
 301     /* Go to next entry */
 302     s->regs[SONIC_RRP] += size;
 303
 304     /* Handle wrap */
 305     if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
 306         s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
 307     }
 308
 309     /* Check resource exhaustion */
 310     if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
 311     {
 312         s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
 313         dp8393x_update_irq(s);
 314     }
 315
 316     /* Done */
 317     s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
 318 }
 319
 320 static void dp8393x_do_software_reset(dp8393xState *s)
 321 {
 322     timer_del(s->watchdog);
 323
 324     s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
 325     s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
 326 }
 327
 328 static void dp8393x_set_next_tick(dp8393xState *s)
 329 {
 330     uint32_t ticks;
 331     int64_t delay;
 332
 333     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 334         timer_del(s->watchdog);
 335         return;
 336     }
 337
 338     ticks = dp8393x_wt(s);
 339     s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 340     delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
 341     timer_mod(s->watchdog, s->wt_last_update + delay);
 342 }
 343
 344 static void dp8393x_update_wt_regs(dp8393xState *s)
 345 {
 346     int64_t elapsed;
 347     uint32_t val;
 348
 349     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 350         timer_del(s->watchdog);
 351         return;
 352     }
 353
 354     elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 355     val = dp8393x_wt(s);
 356     val -= elapsed / 5000000;
 357     s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
 358     s->regs[SONIC_WT0] = (val >> 0)  & 0xffff;
 359     dp8393x_set_next_tick(s);
 360
 361 }
 362
 363 static void dp8393x_do_start_timer(dp8393xState *s)
 364 {
 365     s->regs[SONIC_CR] &= ~SONIC_CR_STP;
 366     dp8393x_set_next_tick(s);
 367 }
 368
 369 static void dp8393x_do_stop_timer(dp8393xState *s)
 370 {
 371     s->regs[SONIC_CR] &= ~SONIC_CR_ST;
 372     dp8393x_update_wt_regs(s);
 373 }
 374
 375 static int dp8393x_can_receive(NetClientState *nc);
 376
 377 static void dp8393x_do_receiver_enable(dp8393xState *s)
 378 {
 379     s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
 380     if (dp8393x_can_receive(s->nic->ncs)) {
 381         qemu_flush_queued_packets(qemu_get_queue(s->nic));
 382     }
 383 }
 384
 385 static void dp8393x_do_receiver_disable(dp8393xState *s)
 386 {
 387     s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
 388 }
 389
 390 static void dp8393x_do_transmit_packets(dp8393xState *s)
 391 {
 392     NetClientState *nc = qemu_get_queue(s->nic);
 393     uint16_t data[12];
 394     int width, size;
 395     int tx_len, len;
 396     uint16_t i;
 397
 398     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 399
 400     while (1) {
 401         /* Read memory */
 402         size = sizeof(uint16_t) * 6 * width;
 403         s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
 404         DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
 405         address_space_rw(&s->as,
 406             dp8393x_ttda(s) + sizeof(uint16_t) * width,
 407             MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 408         tx_len = 0;
 409
 410         /* Update registers */
 411         s->regs[SONIC_TCR] = data[0 * width] & 0xf000;
 412         s->regs[SONIC_TPS] = data[1 * width];
 413         s->regs[SONIC_TFC] = data[2 * width];
 414         s->regs[SONIC_TSA0] = data[3 * width];
 415         s->regs[SONIC_TSA1] = data[4 * width];
 416         s->regs[SONIC_TFS] = data[5 * width];
 417
 418         /* Handle programmable interrupt */
 419         if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
 420             s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
 421         } else {
 422             s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
 423         }
 424
 425         for (i = 0; i < s->regs[SONIC_TFC]; ) {
 426             /* Append fragment */
 427             len = s->regs[SONIC_TFS];
 428             if (tx_len + len > sizeof(s->tx_buffer)) {
 429                 len = sizeof(s->tx_buffer) - tx_len;
 430             }
 431             address_space_rw(&s->as, dp8393x_tsa(s),
 432                 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
 433             tx_len += len;
 434
 435             i++;
 436             if (i != s->regs[SONIC_TFC]) {
 437                 /* Read next fragment details */
 438                 size = sizeof(uint16_t) * 3 * width;
 439                 address_space_rw(&s->as,
 440                     dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
 441                     MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 442                 s->regs[SONIC_TSA0] = data[0 * width];
 443                 s->regs[SONIC_TSA1] = data[1 * width];
 444                 s->regs[SONIC_TFS] = data[2 * width];
 445             }
 446         }
 447
 448         /* Handle Ethernet checksum */
 449         if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
 450             /* Don't append FCS there, to look like slirp packets
 451              * which don't have one */
 452         } else {
 453             /* Remove existing FCS */
 454             tx_len -= 4;
 455         }
 456
 457         if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
 458             /* Loopback */
 459             s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
 460             if (nc->info->can_receive(nc)) {
 461                 s->loopback_packet = 1;
 462                 nc->info->receive(nc, s->tx_buffer, tx_len);
 463             }
 464         } else {
 465             /* Transmit packet */
 466             qemu_send_packet(nc, s->tx_buffer, tx_len);
 467         }
 468         s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
 469
 470         /* Write status */
 471         data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */
 472         size = sizeof(uint16_t) * width;
 473         address_space_rw(&s->as,
 474             dp8393x_ttda(s),
 475             MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
 476
 477         if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
 478             /* Read footer of packet */
 479             size = sizeof(uint16_t) * width;
 480             address_space_rw(&s->as,
 481                 dp8393x_ttda(s) +
 482                              sizeof(uint16_t) *
 483                              (4 + 3 * s->regs[SONIC_TFC]) * width,
 484                 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 485             s->regs[SONIC_CTDA] = data[0 * width] & ~0x1;
 486             if (data[0 * width] & 0x1) {
 487                 /* EOL detected */
 488                 break;
 489             }
 490         }
 491     }
 492
 493     /* Done */
 494     s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
 495     s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
 496     dp8393x_update_irq(s);
 497 }
 498
 499 static void dp8393x_do_halt_transmission(dp8393xState *s)
 500 {
 501     /* Nothing to do */
 502 }
 503
 504 static void dp8393x_do_command(dp8393xState *s, uint16_t command)
 505 {
 506     if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
 507         s->regs[SONIC_CR] &= ~SONIC_CR_RST;
 508         return;
 509     }
 510
 511     s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
 512
 513     if (command & SONIC_CR_HTX)
 514         dp8393x_do_halt_transmission(s);
 515     if (command & SONIC_CR_TXP)
 516         dp8393x_do_transmit_packets(s);
 517     if (command & SONIC_CR_RXDIS)
 518         dp8393x_do_receiver_disable(s);
 519     if (command & SONIC_CR_RXEN)
 520         dp8393x_do_receiver_enable(s);
 521     if (command & SONIC_CR_STP)
 522         dp8393x_do_stop_timer(s);
 523     if (command & SONIC_CR_ST)
 524         dp8393x_do_start_timer(s);
 525     if (command & SONIC_CR_RST)
 526         dp8393x_do_software_reset(s);
 527     if (command & SONIC_CR_RRRA)
 528         dp8393x_do_read_rra(s);
 529     if (command & SONIC_CR_LCAM)
 530         dp8393x_do_load_cam(s);
 531 }
 532
 533 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
 534 {
 535     dp8393xState *s = opaque;
 536     int reg = addr >> s->it_shift;
 537     uint16_t val = 0;
 538
 539     switch (reg) {
 540         /* Update data before reading it */
 541         case SONIC_WT0:
 542         case SONIC_WT1:
 543             dp8393x_update_wt_regs(s);
 544             val = s->regs[reg];
 545             break;
 546         /* Accept read to some registers only when in reset mode */
 547         case SONIC_CAP2:
 548         case SONIC_CAP1:
 549         case SONIC_CAP0:
 550             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 551                 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
 552                 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
 553             }
 554             break;
 555         /* All other registers have no special contrainst */
 556         default:
 557             val = s->regs[reg];
 558     }
 559
 560     DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
 561
 562     return val;
 563 }
 564
 565 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
 566                           unsigned int size)
 567 {
 568     dp8393xState *s = opaque;
 569     int reg = addr >> s->it_shift;
 570
 571     DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]);
 572
 573     switch (reg) {
 574         /* Command register */
 575         case SONIC_CR:
 576             dp8393x_do_command(s, data);
 577             break;
 578         /* Prevent write to read-only registers */
 579         case SONIC_CAP2:
 580         case SONIC_CAP1:
 581         case SONIC_CAP0:
 582         case SONIC_SR:
 583         case SONIC_MDT:
 584             DPRINTF("writing to reg %d invalid\n", reg);
 585             break;
 586         /* Accept write to some registers only when in reset mode */
 587         case SONIC_DCR:
 588             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 589                 s->regs[reg] = data & 0xbfff;
 590             } else {
 591                 DPRINTF("writing to DCR invalid\n");
 592             }
 593             break;
 594         case SONIC_DCR2:
 595             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 596                 s->regs[reg] = data & 0xf017;
 597             } else {
 598                 DPRINTF("writing to DCR2 invalid\n");
 599             }
 600             break;
 601         /* 12 lower bytes are Read Only */
 602         case SONIC_TCR:
 603             s->regs[reg] = data & 0xf000;
 604             break;
 605         /* 9 lower bytes are Read Only */
 606         case SONIC_RCR:
 607             s->regs[reg] = data & 0xffe0;
 608             break;
 609         /* Ignore most significant bit */
 610         case SONIC_IMR:
 611             s->regs[reg] = data & 0x7fff;
 612             dp8393x_update_irq(s);
 613             break;
 614         /* Clear bits by writing 1 to them */
 615         case SONIC_ISR:
 616             data &= s->regs[reg];
 617             s->regs[reg] &= ~data;
 618             if (data & SONIC_ISR_RBE) {
 619                 dp8393x_do_read_rra(s);
 620             }
 621             dp8393x_update_irq(s);
 622             if (dp8393x_can_receive(s->nic->ncs)) {
 623                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 624             }
 625             break;
 626         /* Ignore least significant bit */
 627         case SONIC_RSA:
 628         case SONIC_REA:
 629         case SONIC_RRP:
 630         case SONIC_RWP:
 631             s->regs[reg] = data & 0xfffe;
 632             break;
 633         /* Invert written value for some registers */
 634         case SONIC_CRCT:
 635         case SONIC_FAET:
 636         case SONIC_MPT:
 637             s->regs[reg] = data ^ 0xffff;
 638             break;
 639         /* All other registers have no special contrainst */
 640         default:
 641             s->regs[reg] = data;
 642     }
 643
 644     if (reg == SONIC_WT0 || reg == SONIC_WT1) {
 645         dp8393x_set_next_tick(s);
 646     }
 647 }
 648
 649 static const MemoryRegionOps dp8393x_ops = {
 650     .read = dp8393x_read,
 651     .write = dp8393x_write,
 652     .impl.min_access_size = 2,
 653     .impl.max_access_size = 2,
 654     .endianness = DEVICE_NATIVE_ENDIAN,
 655 };
 656
 657 static void dp8393x_watchdog(void *opaque)
 658 {
 659     dp8393xState *s = opaque;
 660
 661     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 662         return;
 663     }
 664
 665     s->regs[SONIC_WT1] = 0xffff;
 666     s->regs[SONIC_WT0] = 0xffff;
 667     dp8393x_set_next_tick(s);
 668
 669     /* Signal underflow */
 670     s->regs[SONIC_ISR] |= SONIC_ISR_TC;
 671     dp8393x_update_irq(s);
 672 }
 673
 674 static int dp8393x_can_receive(NetClientState *nc)
 675 {
 676     dp8393xState *s = qemu_get_nic_opaque(nc);
 677
 678     if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
 679         return 0;
 680     if (s->regs[SONIC_ISR] & SONIC_ISR_RBE)
 681         return 0;
 682     return 1;
 683 }
 684
 685 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
 686                                   int size)
 687 {
 688     static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 689     int i;
 690
 691     /* Check promiscuous mode */
 692     if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
 693         return 0;
 694     }
 695
 696     /* Check multicast packets */
 697     if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
 698         return SONIC_RCR_MC;
 699     }
 700
 701     /* Check broadcast */
 702     if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
 703         return SONIC_RCR_BC;
 704     }
 705
 706     /* Check CAM */
 707     for (i = 0; i < 16; i++) {
 708         if (s->regs[SONIC_CE] & (1 << i)) {
 709              /* Entry enabled */
 710              if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
 711                  return 0;
 712              }
 713         }
 714     }
 715
 716     return -1;
 717 }
 718
 719 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
 720                                size_t size)
 721 {
 722     dp8393xState *s = qemu_get_nic_opaque(nc);
 723     uint16_t data[10];
 724     int packet_type;
 725     uint32_t available, address;
 726     int width, rx_len = size;
 727     uint32_t checksum;
 728
 729     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 730
 731     s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
 732         SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
 733
 734     packet_type = dp8393x_receive_filter(s, buf, size);
 735     if (packet_type < 0) {
 736         DPRINTF("packet not for netcard\n");
 737         return -1;
 738     }
 739
 740     /* XXX: Check byte ordering */
 741
 742     /* Check for EOL */
 743     if (s->regs[SONIC_LLFA] & 0x1) {
 744         /* Are we still in resource exhaustion? */
 745         size = sizeof(uint16_t) * 1 * width;
 746         address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
 747         address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 748                          (uint8_t *)data, size, 0);
 749         if (data[0 * width] & 0x1) {
 750             /* Still EOL ; stop reception */
 751             return -1;
 752         } else {
 753             s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
 754         }
 755     }
 756
 757     /* Save current position */
 758     s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
 759     s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
 760
 761     /* Calculate the ethernet checksum */
 762     checksum = cpu_to_le32(crc32(0, buf, rx_len));
 763
 764     /* Put packet into RBA */
 765     DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
 766     address = dp8393x_crba(s);
 767     address_space_rw(&s->as, address,
 768         MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1);
 769     address += rx_len;
 770     address_space_rw(&s->as, address,
 771         MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1);
 772     rx_len += 4;
 773     s->regs[SONIC_CRBA1] = address >> 16;
 774     s->regs[SONIC_CRBA0] = address & 0xffff;
 775     available = dp8393x_rbwc(s);
 776     available -= rx_len / 2;
 777     s->regs[SONIC_RBWC1] = available >> 16;
 778     s->regs[SONIC_RBWC0] = available & 0xffff;
 779
 780     /* Update status */
 781     if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
 782         s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
 783     }
 784     s->regs[SONIC_RCR] |= packet_type;
 785     s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
 786     if (s->loopback_packet) {
 787         s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
 788         s->loopback_packet = 0;
 789     }
 790
 791     /* Write status to memory */
 792     DPRINTF("Write status at %08x\n", dp8393x_crda(s));
 793     data[0 * width] = s->regs[SONIC_RCR]; /* status */
 794     data[1 * width] = rx_len; /* byte count */
 795     data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */
 796     data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */
 797     data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */
 798     size = sizeof(uint16_t) * 5 * width;
 799     address_space_rw(&s->as, dp8393x_crda(s),
 800         MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
 801
 802     /* Move to next descriptor */
 803     size = sizeof(uint16_t) * width;
 804     address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
 805         MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 806     s->regs[SONIC_LLFA] = data[0 * width];
 807     if (s->regs[SONIC_LLFA] & 0x1) {
 808         /* EOL detected */
 809         s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
 810     } else {
 811         data[0 * width] = 0; /* in_use */
 812         address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width,
 813             MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
 814         s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
 815         s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
 816         s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
 817
 818         if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
 819             /* Read next RRA */
 820             dp8393x_do_read_rra(s);
 821         }
 822     }
 823
 824     /* Done */
 825     dp8393x_update_irq(s);
 826
 827     return size;
 828 }
 829
 830 static void dp8393x_reset(DeviceState *dev)
 831 {
 832     dp8393xState *s = DP8393X(dev);
 833     timer_del(s->watchdog);
 834
 835     memset(s->regs, 0, sizeof(s->regs));
 836     s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
 837     s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
 838     s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
 839     s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
 840     s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
 841     s->regs[SONIC_IMR] = 0;
 842     s->regs[SONIC_ISR] = 0;
 843     s->regs[SONIC_DCR2] = 0;
 844     s->regs[SONIC_EOBC] = 0x02F8;
 845     s->regs[SONIC_RSC] = 0;
 846     s->regs[SONIC_CE] = 0;
 847     s->regs[SONIC_RSC] = 0;
 848
 849     /* Network cable is connected */
 850     s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
 851
 852     dp8393x_update_irq(s);
 853 }
 854
 855 static NetClientInfo net_dp83932_info = {
 856     .type = NET_CLIENT_DRIVER_NIC,
 857     .size = sizeof(NICState),
 858     .can_receive = dp8393x_can_receive,
 859     .receive = dp8393x_receive,
 860 };
 861
 862 static void dp8393x_instance_init(Object *obj)
 863 {
 864     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 865     dp8393xState *s = DP8393X(obj);
 866
 867     sysbus_init_mmio(sbd, &s->mmio);
 868     sysbus_init_mmio(sbd, &s->prom);
 869     sysbus_init_irq(sbd, &s->irq);
 870 }
 871
 872 static void dp8393x_realize(DeviceState *dev, Error **errp)
 873 {
 874     dp8393xState *s = DP8393X(dev);
 875     int i, checksum;
 876     uint8_t *prom;
 877     Error *local_err = NULL;
 878
 879     address_space_init(&s->as, s->dma_mr, "dp8393x");
 880     memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
 881                           "dp8393x-regs", 0x40 << s->it_shift);
 882
 883     s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
 884                           object_get_typename(OBJECT(dev)), dev->id, s);
 885     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 886
 887     s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
 888     s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
 889
 890     memory_region_init_ram(&s->prom, OBJECT(dev),
 891                            "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
 892     if (local_err) {
 893         error_propagate(errp, local_err);
 894         return;
 895     }
 896     memory_region_set_readonly(&s->prom, true);
 897     prom = memory_region_get_ram_ptr(&s->prom);
 898     checksum = 0;
 899     for (i = 0; i < 6; i++) {
 900         prom[i] = s->conf.macaddr.a[i];
 901         checksum += prom[i];
 902         if (checksum > 0xff) {
 903             checksum = (checksum + 1) & 0xff;
 904         }
 905     }
 906     prom[7] = 0xff - checksum;
 907 }
 908
 909 static const VMStateDescription vmstate_dp8393x = {
 910     .name = "dp8393x",
 911     .version_id = 0,
 912     .minimum_version_id = 0,
 913     .fields = (VMStateField []) {
 914         VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
 915         VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
 916         VMSTATE_END_OF_LIST()
 917     }
 918 };
 919
 920 static Property dp8393x_properties[] = {
 921     DEFINE_NIC_PROPERTIES(dp8393xState, conf),
 922     DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
 923     DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
 924     DEFINE_PROP_END_OF_LIST(),
 925 };
 926
 927 static void dp8393x_class_init(ObjectClass *klass, void *data)
 928 {
 929     DeviceClass *dc = DEVICE_CLASS(klass);
 930
 931     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 932     dc->realize = dp8393x_realize;
 933     dc->reset = dp8393x_reset;
 934     dc->vmsd = &vmstate_dp8393x;
 935     dc->props = dp8393x_properties;
 936     /* Reason: dma_mr property can't be set */
 937     dc->user_creatable = false;
 938 }
 939
 940 static const TypeInfo dp8393x_info = {
 941     .name          = TYPE_DP8393X,
 942     .parent        = TYPE_SYS_BUS_DEVICE,
 943     .instance_size = sizeof(dp8393xState),
 944     .instance_init = dp8393x_instance_init,
 945     .class_init    = dp8393x_class_init,
 946 };
 947
 948 static void dp8393x_register_types(void)
 949 {
 950     type_register_static(&dp8393x_info);
 951 }
 952
 953 type_init(dp8393x_register_types)