hw/net/xilinx_ethlite.c

   1 /*
   2  * QEMU model of the Xilinx Ethernet Lite MAC.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/module.h"
  27 #include "cpu.h" /* FIXME should not use tswap* */
  28 #include "hw/sysbus.h"
  29 #include "hw/irq.h"
  30 #include "hw/qdev-properties.h"
  31 #include "net/net.h"
  32
  33 #define D(x)
  34 #define R_TX_BUF0     0
  35 #define R_TX_LEN0     (0x07f4 / 4)
  36 #define R_TX_GIE0     (0x07f8 / 4)
  37 #define R_TX_CTRL0    (0x07fc / 4)
  38 #define R_TX_BUF1     (0x0800 / 4)
  39 #define R_TX_LEN1     (0x0ff4 / 4)
  40 #define R_TX_CTRL1    (0x0ffc / 4)
  41
  42 #define R_RX_BUF0     (0x1000 / 4)
  43 #define R_RX_CTRL0    (0x17fc / 4)
  44 #define R_RX_BUF1     (0x1800 / 4)
  45 #define R_RX_CTRL1    (0x1ffc / 4)
  46 #define R_MAX         (0x2000 / 4)
  47
  48 #define GIE_GIE    0x80000000
  49
  50 #define CTRL_I     0x8
  51 #define CTRL_P     0x2
  52 #define CTRL_S     0x1
  53
  54 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
  55 #define XILINX_ETHLITE(obj) \
  56     OBJECT_CHECK(struct xlx_ethlite, (obj), TYPE_XILINX_ETHLITE)
  57
  58 struct xlx_ethlite
  59 {
  60     SysBusDevice parent_obj;
  61
  62     MemoryRegion mmio;
  63     qemu_irq irq;
  64     NICState *nic;
  65     NICConf conf;
  66
  67     uint32_t c_tx_pingpong;
  68     uint32_t c_rx_pingpong;
  69     unsigned int txbuf;
  70     unsigned int rxbuf;
  71
  72     uint32_t regs[R_MAX];
  73 };
  74
  75 static inline void eth_pulse_irq(struct xlx_ethlite *s)
  76 {
  77     /* Only the first gie reg is active.  */
  78     if (s->regs[R_TX_GIE0] & GIE_GIE) {
  79         qemu_irq_pulse(s->irq);
  80     }
  81 }
  82
  83 static uint64_t
  84 eth_read(void *opaque, hwaddr addr, unsigned int size)
  85 {
  86     struct xlx_ethlite *s = opaque;
  87     uint32_t r = 0;
  88
  89     addr >>= 2;
  90
  91     switch (addr)
  92     {
  93         case R_TX_GIE0:
  94         case R_TX_LEN0:
  95         case R_TX_LEN1:
  96         case R_TX_CTRL1:
  97         case R_TX_CTRL0:
  98         case R_RX_CTRL1:
  99         case R_RX_CTRL0:
 100             r = s->regs[addr];
 101             D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
 102             break;
 103
 104         default:
 105             r = tswap32(s->regs[addr]);
 106             break;
 107     }
 108     return r;
 109 }
 110
 111 static void
 112 eth_write(void *opaque, hwaddr addr,
 113           uint64_t val64, unsigned int size)
 114 {
 115     struct xlx_ethlite *s = opaque;
 116     unsigned int base = 0;
 117     uint32_t value = val64;
 118
 119     addr >>= 2;
 120     switch (addr)
 121     {
 122         case R_TX_CTRL0:
 123         case R_TX_CTRL1:
 124             if (addr == R_TX_CTRL1)
 125                 base = 0x800 / 4;
 126
 127             D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
 128                        __func__, addr * 4, value));
 129             if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
 130                 qemu_send_packet(qemu_get_queue(s->nic),
 131                                  (void *) &s->regs[base],
 132                                  s->regs[base + R_TX_LEN0]);
 133                 D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
 134                 if (s->regs[base + R_TX_CTRL0] & CTRL_I)
 135                     eth_pulse_irq(s);
 136             } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
 137                 memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
 138                 if (s->regs[base + R_TX_CTRL0] & CTRL_I)
 139                     eth_pulse_irq(s);
 140             }
 141
 142             /* We are fast and get ready pretty much immediately so
 143                we actually never flip the S nor P bits to one.  */
 144             s->regs[addr] = value & ~(CTRL_P | CTRL_S);
 145             break;
 146
 147         /* Keep these native.  */
 148         case R_RX_CTRL0:
 149         case R_RX_CTRL1:
 150             if (!(value & CTRL_S)) {
 151                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 152             }
 153             /* fall through */
 154         case R_TX_LEN0:
 155         case R_TX_LEN1:
 156         case R_TX_GIE0:
 157             D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
 158                        __func__, addr * 4, value));
 159             s->regs[addr] = value;
 160             break;
 161
 162         default:
 163             s->regs[addr] = tswap32(value);
 164             break;
 165     }
 166 }
 167
 168 static const MemoryRegionOps eth_ops = {
 169     .read = eth_read,
 170     .write = eth_write,
 171     .endianness = DEVICE_NATIVE_ENDIAN,
 172     .valid = {
 173         .min_access_size = 4,
 174         .max_access_size = 4
 175     }
 176 };
 177
 178 static int eth_can_rx(NetClientState *nc)
 179 {
 180     struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
 181     unsigned int rxbase = s->rxbuf * (0x800 / 4);
 182
 183     return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
 184 }
 185
 186 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 187 {
 188     struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
 189     unsigned int rxbase = s->rxbuf * (0x800 / 4);
 190
 191     /* DA filter.  */
 192     if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
 193         return size;
 194
 195     if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
 196         D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
 197         return -1;
 198     }
 199
 200     D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase));
 201     if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) {
 202         D(qemu_log("ethlite packet is too big, size=%x\n", size));
 203         return -1;
 204     }
 205     memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
 206
 207     s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
 208     if (s->regs[R_RX_CTRL0] & CTRL_I) {
 209         eth_pulse_irq(s);
 210     }
 211
 212     /* If c_rx_pingpong was set flip buffers.  */
 213     s->rxbuf ^= s->c_rx_pingpong;
 214     return size;
 215 }
 216
 217 static void xilinx_ethlite_reset(DeviceState *dev)
 218 {
 219     struct xlx_ethlite *s = XILINX_ETHLITE(dev);
 220
 221     s->rxbuf = 0;
 222 }
 223
 224 static NetClientInfo net_xilinx_ethlite_info = {
 225     .type = NET_CLIENT_DRIVER_NIC,
 226     .size = sizeof(NICState),
 227     .can_receive = eth_can_rx,
 228     .receive = eth_rx,
 229 };
 230
 231 static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
 232 {
 233     struct xlx_ethlite *s = XILINX_ETHLITE(dev);
 234
 235     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 236     s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
 237                           object_get_typename(OBJECT(dev)), dev->id, s);
 238     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 239 }
 240
 241 static void xilinx_ethlite_init(Object *obj)
 242 {
 243     struct xlx_ethlite *s = XILINX_ETHLITE(obj);
 244
 245     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 246
 247     memory_region_init_io(&s->mmio, obj, &eth_ops, s,
 248                           "xlnx.xps-ethernetlite", R_MAX * 4);
 249     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 250 }
 251
 252 static Property xilinx_ethlite_properties[] = {
 253     DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
 254     DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
 255     DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
 256     DEFINE_PROP_END_OF_LIST(),
 257 };
 258
 259 static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
 260 {
 261     DeviceClass *dc = DEVICE_CLASS(klass);
 262
 263     dc->realize = xilinx_ethlite_realize;
 264     dc->reset = xilinx_ethlite_reset;
 265     dc->props = xilinx_ethlite_properties;
 266 }
 267
 268 static const TypeInfo xilinx_ethlite_info = {
 269     .name          = TYPE_XILINX_ETHLITE,
 270     .parent        = TYPE_SYS_BUS_DEVICE,
 271     .instance_size = sizeof(struct xlx_ethlite),
 272     .instance_init = xilinx_ethlite_init,
 273     .class_init    = xilinx_ethlite_class_init,
 274 };
 275
 276 static void xilinx_ethlite_register_types(void)
 277 {
 278     type_register_static(&xilinx_ethlite_info);
 279 }
 280
 281 type_init(xilinx_ethlite_register_types)