hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pci_bridge.h"
  27 #include "pci_internals.h"
  28 #include "monitor.h"
  29 #include "net.h"
  30 #include "sysemu.h"
  31 #include "loader.h"
  32 #include "qemu-objects.h"
  33
  34 //#define DEBUG_PCI
  35 #ifdef DEBUG_PCI
  36 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  37 #else
  38 # define PCI_DPRINTF(format, ...)       do { } while (0)
  39 #endif
  40
  41 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  42 static char *pcibus_get_dev_path(DeviceState *dev);
  43
  44 struct BusInfo pci_bus_info = {
  45     .name       = "PCI",
  46     .size       = sizeof(PCIBus),
  47     .print_dev  = pcibus_dev_print,
  48     .get_dev_path = pcibus_get_dev_path,
  49     .props      = (Property[]) {
  50         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  51         DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
  52         DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
  53         DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
  54                         QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
  55         DEFINE_PROP_END_OF_LIST()
  56     }
  57 };
  58
  59 static void pci_update_mappings(PCIDevice *d);
  60 static void pci_set_irq(void *opaque, int irq_num, int level);
  61 static int pci_add_option_rom(PCIDevice *pdev);
  62 static void pci_del_option_rom(PCIDevice *pdev);
  63
  64 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  65 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  66
  67 struct PCIHostBus {
  68     int domain;
  69     struct PCIBus *bus;
  70     QLIST_ENTRY(PCIHostBus) next;
  71 };
  72 static QLIST_HEAD(, PCIHostBus) host_buses;
  73
  74 static const VMStateDescription vmstate_pcibus = {
  75     .name = "PCIBUS",
  76     .version_id = 1,
  77     .minimum_version_id = 1,
  78     .minimum_version_id_old = 1,
  79     .fields      = (VMStateField []) {
  80         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  81         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  82         VMSTATE_END_OF_LIST()
  83     }
  84 };
  85
  86 static int pci_bar(PCIDevice *d, int reg)
  87 {
  88     uint8_t type;
  89
  90     if (reg != PCI_ROM_SLOT)
  91         return PCI_BASE_ADDRESS_0 + reg * 4;
  92
  93     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
  94     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
  95 }
  96
  97 static inline int pci_irq_state(PCIDevice *d, int irq_num)
  98 {
  99         return (d->irq_state >> irq_num) & 0x1;
 100 }
 101
 102 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
 103 {
 104         d->irq_state &= ~(0x1 << irq_num);
 105         d->irq_state |= level << irq_num;
 106 }
 107
 108 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
 109 {
 110     PCIBus *bus;
 111     for (;;) {
 112         bus = pci_dev->bus;
 113         irq_num = bus->map_irq(pci_dev, irq_num);
 114         if (bus->set_irq)
 115             break;
 116         pci_dev = bus->parent_dev;
 117     }
 118     bus->irq_count[irq_num] += change;
 119     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 120 }
 121
 122 /* Update interrupt status bit in config space on interrupt
 123  * state change. */
 124 static void pci_update_irq_status(PCIDevice *dev)
 125 {
 126     if (dev->irq_state) {
 127         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
 128     } else {
 129         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 130     }
 131 }
 132
 133 static void pci_device_reset(PCIDevice *dev)
 134 {
 135     int r;
 136
 137     dev->irq_state = 0;
 138     pci_update_irq_status(dev);
 139     /* Clear all writeable bits */
 140     pci_set_word(dev->config + PCI_COMMAND,
 141                  pci_get_word(dev->config + PCI_COMMAND) &
 142                  ~pci_get_word(dev->wmask + PCI_COMMAND));
 143     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 144     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 145     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 146         PCIIORegion *region = &dev->io_regions[r];
 147         if (!region->size) {
 148             continue;
 149         }
 150
 151         if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 152             region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 153             pci_set_quad(dev->config + pci_bar(dev, r), region->type);
 154         } else {
 155             pci_set_long(dev->config + pci_bar(dev, r), region->type);
 156         }
 157     }
 158     pci_update_mappings(dev);
 159 }
 160
 161 static void pci_bus_reset(void *opaque)
 162 {
 163     PCIBus *bus = opaque;
 164     int i;
 165
 166     for (i = 0; i < bus->nirq; i++) {
 167         bus->irq_count[i] = 0;
 168     }
 169     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 170         if (bus->devices[i]) {
 171             pci_device_reset(bus->devices[i]);
 172         }
 173     }
 174 }
 175
 176 static void pci_host_bus_register(int domain, PCIBus *bus)
 177 {
 178     struct PCIHostBus *host;
 179     host = qemu_mallocz(sizeof(*host));
 180     host->domain = domain;
 181     host->bus = bus;
 182     QLIST_INSERT_HEAD(&host_buses, host, next);
 183 }
 184
 185 PCIBus *pci_find_root_bus(int domain)
 186 {
 187     struct PCIHostBus *host;
 188
 189     QLIST_FOREACH(host, &host_buses, next) {
 190         if (host->domain == domain) {
 191             return host->bus;
 192         }
 193     }
 194
 195     return NULL;
 196 }
 197
 198 int pci_find_domain(const PCIBus *bus)
 199 {
 200     PCIDevice *d;
 201     struct PCIHostBus *host;
 202
 203     /* obtain root bus */
 204     while ((d = bus->parent_dev) != NULL) {
 205         bus = d->bus;
 206     }
 207
 208     QLIST_FOREACH(host, &host_buses, next) {
 209         if (host->bus == bus) {
 210             return host->domain;
 211         }
 212     }
 213
 214     abort();    /* should not be reached */
 215     return -1;
 216 }
 217
 218 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 219                          const char *name, int devfn_min)
 220 {
 221     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 222     assert(PCI_FUNC(devfn_min) == 0);
 223     bus->devfn_min = devfn_min;
 224
 225     /* host bridge */
 226     QLIST_INIT(&bus->child);
 227     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 228
 229     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
 230     qemu_register_reset(pci_bus_reset, bus);
 231 }
 232
 233 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 234 {
 235     PCIBus *bus;
 236
 237     bus = qemu_mallocz(sizeof(*bus));
 238     bus->qbus.qdev_allocated = 1;
 239     pci_bus_new_inplace(bus, parent, name, devfn_min);
 240     return bus;
 241 }
 242
 243 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 244                   void *irq_opaque, int nirq)
 245 {
 246     bus->set_irq = set_irq;
 247     bus->map_irq = map_irq;
 248     bus->irq_opaque = irq_opaque;
 249     bus->nirq = nirq;
 250     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 251 }
 252
 253 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
 254 {
 255     bus->qbus.allow_hotplug = 1;
 256     bus->hotplug = hotplug;
 257     bus->hotplug_qdev = qdev;
 258 }
 259
 260 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
 261 {
 262     bus->mem_base = base;
 263 }
 264
 265 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 266                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 267                          void *irq_opaque, int devfn_min, int nirq)
 268 {
 269     PCIBus *bus;
 270
 271     bus = pci_bus_new(parent, name, devfn_min);
 272     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 273     return bus;
 274 }
 275
 276 int pci_bus_num(PCIBus *s)
 277 {
 278     if (!s->parent_dev)
 279         return 0;       /* pci host bridge */
 280     return s->parent_dev->config[PCI_SECONDARY_BUS];
 281 }
 282
 283 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 284 {
 285     PCIDevice *s = container_of(pv, PCIDevice, config);
 286     uint8_t *config;
 287     int i;
 288
 289     assert(size == pci_config_size(s));
 290     config = qemu_malloc(size);
 291
 292     qemu_get_buffer(f, config, size);
 293     for (i = 0; i < size; ++i) {
 294         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
 295             qemu_free(config);
 296             return -EINVAL;
 297         }
 298     }
 299     memcpy(s->config, config, size);
 300
 301     pci_update_mappings(s);
 302
 303     qemu_free(config);
 304     return 0;
 305 }
 306
 307 /* just put buffer */
 308 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 309 {
 310     const uint8_t **v = pv;
 311     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 312     qemu_put_buffer(f, *v, size);
 313 }
 314
 315 static VMStateInfo vmstate_info_pci_config = {
 316     .name = "pci config",
 317     .get  = get_pci_config_device,
 318     .put  = put_pci_config_device,
 319 };
 320
 321 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 322 {
 323     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 324     uint32_t irq_state[PCI_NUM_PINS];
 325     int i;
 326     for (i = 0; i < PCI_NUM_PINS; ++i) {
 327         irq_state[i] = qemu_get_be32(f);
 328         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
 329             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
 330                     irq_state[i]);
 331             return -EINVAL;
 332         }
 333     }
 334
 335     for (i = 0; i < PCI_NUM_PINS; ++i) {
 336         pci_set_irq_state(s, i, irq_state[i]);
 337     }
 338
 339     return 0;
 340 }
 341
 342 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 343 {
 344     int i;
 345     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 346
 347     for (i = 0; i < PCI_NUM_PINS; ++i) {
 348         qemu_put_be32(f, pci_irq_state(s, i));
 349     }
 350 }
 351
 352 static VMStateInfo vmstate_info_pci_irq_state = {
 353     .name = "pci irq state",
 354     .get  = get_pci_irq_state,
 355     .put  = put_pci_irq_state,
 356 };
 357
 358 const VMStateDescription vmstate_pci_device = {
 359     .name = "PCIDevice",
 360     .version_id = 2,
 361     .minimum_version_id = 1,
 362     .minimum_version_id_old = 1,
 363     .fields      = (VMStateField []) {
 364         VMSTATE_INT32_LE(version_id, PCIDevice),
 365         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 366                                    vmstate_info_pci_config,
 367                                    PCI_CONFIG_SPACE_SIZE),
 368         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 369                                    vmstate_info_pci_irq_state,
 370                                    PCI_NUM_PINS * sizeof(int32_t)),
 371         VMSTATE_END_OF_LIST()
 372     }
 373 };
 374
 375 const VMStateDescription vmstate_pcie_device = {
 376     .name = "PCIDevice",
 377     .version_id = 2,
 378     .minimum_version_id = 1,
 379     .minimum_version_id_old = 1,
 380     .fields      = (VMStateField []) {
 381         VMSTATE_INT32_LE(version_id, PCIDevice),
 382         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 383                                    vmstate_info_pci_config,
 384                                    PCIE_CONFIG_SPACE_SIZE),
 385         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 386                                    vmstate_info_pci_irq_state,
 387                                    PCI_NUM_PINS * sizeof(int32_t)),
 388         VMSTATE_END_OF_LIST()
 389     }
 390 };
 391
 392 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 393 {
 394     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 395 }
 396
 397 void pci_device_save(PCIDevice *s, QEMUFile *f)
 398 {
 399     /* Clear interrupt status bit: it is implicit
 400      * in irq_state which we are saving.
 401      * This makes us compatible with old devices
 402      * which never set or clear this bit. */
 403     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 404     vmstate_save_state(f, pci_get_vmstate(s), s);
 405     /* Restore the interrupt status bit. */
 406     pci_update_irq_status(s);
 407 }
 408
 409 int pci_device_load(PCIDevice *s, QEMUFile *f)
 410 {
 411     int ret;
 412     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 413     /* Restore the interrupt status bit. */
 414     pci_update_irq_status(s);
 415     return ret;
 416 }
 417
 418 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
 419 {
 420     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
 421                  pci_default_sub_vendor_id);
 422     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
 423                  pci_default_sub_device_id);
 424 }
 425
 426 /*
 427  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
 428  *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
 429  */
 430 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 431                       unsigned int *slotp, unsigned int *funcp)
 432 {
 433     const char *p;
 434     char *e;
 435     unsigned long val;
 436     unsigned long dom = 0, bus = 0;
 437     unsigned int slot = 0;
 438     unsigned int func = 0;
 439
 440     p = addr;
 441     val = strtoul(p, &e, 16);
 442     if (e == p)
 443         return -1;
 444     if (*e == ':') {
 445         bus = val;
 446         p = e + 1;
 447         val = strtoul(p, &e, 16);
 448         if (e == p)
 449             return -1;
 450         if (*e == ':') {
 451             dom = bus;
 452             bus = val;
 453             p = e + 1;
 454             val = strtoul(p, &e, 16);
 455             if (e == p)
 456                 return -1;
 457         }
 458     }
 459
 460     slot = val;
 461
 462     if (funcp != NULL) {
 463         if (*e != '.')
 464             return -1;
 465
 466         p = e + 1;
 467         val = strtoul(p, &e, 16);
 468         if (e == p)
 469             return -1;
 470
 471         func = val;
 472     }
 473
 474     /* if funcp == NULL func is 0 */
 475     if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
 476         return -1;
 477
 478     if (*e)
 479         return -1;
 480
 481     /* Note: QEMU doesn't implement domains other than 0 */
 482     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 483         return -1;
 484
 485     *domp = dom;
 486     *busp = bus;
 487     *slotp = slot;
 488     if (funcp != NULL)
 489         *funcp = func;
 490     return 0;
 491 }
 492
 493 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 494                      unsigned *slotp)
 495 {
 496     /* strip legacy tag */
 497     if (!strncmp(addr, "pci_addr=", 9)) {
 498         addr += 9;
 499     }
 500     if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
 501         monitor_printf(mon, "Invalid pci address\n");
 502         return -1;
 503     }
 504     return 0;
 505 }
 506
 507 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 508 {
 509     int dom, bus;
 510     unsigned slot;
 511
 512     if (!devaddr) {
 513         *devfnp = -1;
 514         return pci_find_bus(pci_find_root_bus(0), 0);
 515     }
 516
 517     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
 518         return NULL;
 519     }
 520
 521     *devfnp = slot << 3;
 522     return pci_find_bus(pci_find_root_bus(dom), bus);
 523 }
 524
 525 static void pci_init_cmask(PCIDevice *dev)
 526 {
 527     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 528     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 529     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 530     dev->cmask[PCI_REVISION_ID] = 0xff;
 531     dev->cmask[PCI_CLASS_PROG] = 0xff;
 532     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 533     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 534     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 535 }
 536
 537 static void pci_init_wmask(PCIDevice *dev)
 538 {
 539     int config_size = pci_config_size(dev);
 540
 541     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 542     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 543     pci_set_word(dev->wmask + PCI_COMMAND,
 544                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 545                  PCI_COMMAND_INTX_DISABLE);
 546
 547     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 548            config_size - PCI_CONFIG_HEADER_SIZE);
 549 }
 550
 551 static void pci_init_wmask_bridge(PCIDevice *d)
 552 {
 553     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 554        PCI_SEC_LETENCY_TIMER */
 555     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 556
 557     /* base and limit */
 558     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 559     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 560     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 561                  PCI_MEMORY_RANGE_MASK & 0xffff);
 562     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 563                  PCI_MEMORY_RANGE_MASK & 0xffff);
 564     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 565                  PCI_PREF_RANGE_MASK & 0xffff);
 566     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 567                  PCI_PREF_RANGE_MASK & 0xffff);
 568
 569     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 570     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 571
 572     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 573 }
 574
 575 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
 576 {
 577     uint8_t slot = PCI_SLOT(dev->devfn);
 578     uint8_t func;
 579
 580     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 581         dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
 582     }
 583
 584     /*
 585      * multifuction bit is interpreted in two ways as follows.
 586      *   - all functions must set the bit to 1.
 587      *     Example: Intel X53
 588      *   - function 0 must set the bit, but the rest function (> 0)
 589      *     is allowed to leave the bit to 0.
 590      *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
 591      *
 592      * So OS (at least Linux) checks the bit of only function 0,
 593      * and doesn't see the bit of function > 0.
 594      *
 595      * The below check allows both interpretation.
 596      */
 597     if (PCI_FUNC(dev->devfn)) {
 598         PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
 599         if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
 600             /* function 0 should set multifunction bit */
 601             error_report("PCI: single function device can't be populated "
 602                          "in function %x.%x", slot, PCI_FUNC(dev->devfn));
 603             return -1;
 604         }
 605         return 0;
 606     }
 607
 608     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 609         return 0;
 610     }
 611     /* function 0 indicates single function, so function > 0 must be NULL */
 612     for (func = 1; func < PCI_FUNC_MAX; ++func) {
 613         if (bus->devices[PCI_DEVFN(slot, func)]) {
 614             error_report("PCI: %x.0 indicates single function, "
 615                          "but %x.%x is already populated.",
 616                          slot, slot, func);
 617             return -1;
 618         }
 619     }
 620     return 0;
 621 }
 622
 623 static void pci_config_alloc(PCIDevice *pci_dev)
 624 {
 625     int config_size = pci_config_size(pci_dev);
 626
 627     pci_dev->config = qemu_mallocz(config_size);
 628     pci_dev->cmask = qemu_mallocz(config_size);
 629     pci_dev->wmask = qemu_mallocz(config_size);
 630     pci_dev->used = qemu_mallocz(config_size);
 631 }
 632
 633 static void pci_config_free(PCIDevice *pci_dev)
 634 {
 635     qemu_free(pci_dev->config);
 636     qemu_free(pci_dev->cmask);
 637     qemu_free(pci_dev->wmask);
 638     qemu_free(pci_dev->used);
 639 }
 640
 641 /* -1 for devfn means auto assign */
 642 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 643                                          const char *name, int devfn,
 644                                          PCIConfigReadFunc *config_read,
 645                                          PCIConfigWriteFunc *config_write,
 646                                          bool is_bridge)
 647 {
 648     if (devfn < 0) {
 649         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
 650             devfn += PCI_FUNC_MAX) {
 651             if (!bus->devices[devfn])
 652                 goto found;
 653         }
 654         error_report("PCI: no slot/function available for %s, all in use", name);
 655         return NULL;
 656     found: ;
 657     } else if (bus->devices[devfn]) {
 658         error_report("PCI: slot %d function %d not available for %s, in use by %s",
 659                      PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
 660         return NULL;
 661     }
 662     pci_dev->bus = bus;
 663     pci_dev->devfn = devfn;
 664     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 665     pci_dev->irq_state = 0;
 666     pci_config_alloc(pci_dev);
 667
 668     if (!is_bridge) {
 669         pci_set_default_subsystem_id(pci_dev);
 670     }
 671     pci_init_cmask(pci_dev);
 672     pci_init_wmask(pci_dev);
 673     if (is_bridge) {
 674         pci_init_wmask_bridge(pci_dev);
 675     }
 676     if (pci_init_multifunction(bus, pci_dev)) {
 677         pci_config_free(pci_dev);
 678         return NULL;
 679     }
 680
 681     if (!config_read)
 682         config_read = pci_default_read_config;
 683     if (!config_write)
 684         config_write = pci_default_write_config;
 685     pci_dev->config_read = config_read;
 686     pci_dev->config_write = config_write;
 687     bus->devices[devfn] = pci_dev;
 688     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 689     pci_dev->version_id = 2; /* Current pci device vmstate version */
 690     return pci_dev;
 691 }
 692
 693 static void do_pci_unregister_device(PCIDevice *pci_dev)
 694 {
 695     qemu_free_irqs(pci_dev->irq);
 696     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 697     pci_config_free(pci_dev);
 698 }
 699
 700 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 701                                int instance_size, int devfn,
 702                                PCIConfigReadFunc *config_read,
 703                                PCIConfigWriteFunc *config_write)
 704 {
 705     PCIDevice *pci_dev;
 706
 707     pci_dev = qemu_mallocz(instance_size);
 708     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 709                                      config_read, config_write,
 710                                      PCI_HEADER_TYPE_NORMAL);
 711     if (pci_dev == NULL) {
 712         hw_error("PCI: can't register device\n");
 713     }
 714     return pci_dev;
 715 }
 716
 717 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
 718                                           target_phys_addr_t addr)
 719 {
 720     return addr + bus->mem_base;
 721 }
 722
 723 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 724 {
 725     PCIIORegion *r;
 726     int i;
 727
 728     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 729         r = &pci_dev->io_regions[i];
 730         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 731             continue;
 732         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 733             isa_unassign_ioport(r->addr, r->filtered_size);
 734         } else {
 735             cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
 736                                                          r->addr),
 737                                          r->filtered_size,
 738                                          IO_MEM_UNASSIGNED);
 739         }
 740     }
 741 }
 742
 743 static int pci_unregister_device(DeviceState *dev)
 744 {
 745     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 746     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 747     int ret = 0;
 748
 749     if (info->exit)
 750         ret = info->exit(pci_dev);
 751     if (ret)
 752         return ret;
 753
 754     pci_unregister_io_regions(pci_dev);
 755     pci_del_option_rom(pci_dev);
 756     do_pci_unregister_device(pci_dev);
 757     return 0;
 758 }
 759
 760 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 761                             pcibus_t size, int type,
 762                             PCIMapIORegionFunc *map_func)
 763 {
 764     PCIIORegion *r;
 765     uint32_t addr;
 766     uint64_t wmask;
 767
 768     assert(region_num >= 0);
 769     assert(region_num < PCI_NUM_REGIONS);
 770     if (size & (size-1)) {
 771         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 772                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 773         exit(1);
 774     }
 775
 776     r = &pci_dev->io_regions[region_num];
 777     r->addr = PCI_BAR_UNMAPPED;
 778     r->size = size;
 779     r->filtered_size = size;
 780     r->type = type;
 781     r->map_func = map_func;
 782
 783     wmask = ~(size - 1);
 784     addr = pci_bar(pci_dev, region_num);
 785     if (region_num == PCI_ROM_SLOT) {
 786         /* ROM enable bit is writeable */
 787         wmask |= PCI_ROM_ADDRESS_ENABLE;
 788     }
 789     pci_set_long(pci_dev->config + addr, type);
 790     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 791         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 792         pci_set_quad(pci_dev->wmask + addr, wmask);
 793         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 794     } else {
 795         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 796         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 797     }
 798 }
 799
 800 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 801                               uint8_t type)
 802 {
 803     pcibus_t base = *addr;
 804     pcibus_t limit = *addr + *size - 1;
 805     PCIDevice *br;
 806
 807     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 808         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 809
 810         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 811             if (!(cmd & PCI_COMMAND_IO)) {
 812                 goto no_map;
 813             }
 814         } else {
 815             if (!(cmd & PCI_COMMAND_MEMORY)) {
 816                 goto no_map;
 817             }
 818         }
 819
 820         base = MAX(base, pci_bridge_get_base(br, type));
 821         limit = MIN(limit, pci_bridge_get_limit(br, type));
 822     }
 823
 824     if (base > limit) {
 825         goto no_map;
 826     }
 827     *addr = base;
 828     *size = limit - base + 1;
 829     return;
 830 no_map:
 831     *addr = PCI_BAR_UNMAPPED;
 832     *size = 0;
 833 }
 834
 835 static pcibus_t pci_bar_address(PCIDevice *d,
 836                                 int reg, uint8_t type, pcibus_t size)
 837 {
 838     pcibus_t new_addr, last_addr;
 839     int bar = pci_bar(d, reg);
 840     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 841
 842     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 843         if (!(cmd & PCI_COMMAND_IO)) {
 844             return PCI_BAR_UNMAPPED;
 845         }
 846         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
 847         last_addr = new_addr + size - 1;
 848         /* NOTE: we have only 64K ioports on PC */
 849         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
 850             return PCI_BAR_UNMAPPED;
 851         }
 852         return new_addr;
 853     }
 854
 855     if (!(cmd & PCI_COMMAND_MEMORY)) {
 856         return PCI_BAR_UNMAPPED;
 857     }
 858     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 859         new_addr = pci_get_quad(d->config + bar);
 860     } else {
 861         new_addr = pci_get_long(d->config + bar);
 862     }
 863     /* the ROM slot has a specific enable bit */
 864     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
 865         return PCI_BAR_UNMAPPED;
 866     }
 867     new_addr &= ~(size - 1);
 868     last_addr = new_addr + size - 1;
 869     /* NOTE: we do not support wrapping */
 870     /* XXX: as we cannot support really dynamic
 871        mappings, we handle specific values as invalid
 872        mappings. */
 873     if (last_addr <= new_addr || new_addr == 0 ||
 874         last_addr == PCI_BAR_UNMAPPED) {
 875         return PCI_BAR_UNMAPPED;
 876     }
 877
 878     /* Now pcibus_t is 64bit.
 879      * Check if 32 bit BAR wraps around explicitly.
 880      * Without this, PC ide doesn't work well.
 881      * TODO: remove this work around.
 882      */
 883     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
 884         return PCI_BAR_UNMAPPED;
 885     }
 886
 887     /*
 888      * OS is allowed to set BAR beyond its addressable
 889      * bits. For example, 32 bit OS can set 64bit bar
 890      * to >4G. Check it. TODO: we might need to support
 891      * it in the future for e.g. PAE.
 892      */
 893     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
 894         return PCI_BAR_UNMAPPED;
 895     }
 896
 897     return new_addr;
 898 }
 899
 900 static void pci_update_mappings(PCIDevice *d)
 901 {
 902     PCIIORegion *r;
 903     int i;
 904     pcibus_t new_addr, filtered_size;
 905
 906     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 907         r = &d->io_regions[i];
 908
 909         /* this region isn't registered */
 910         if (!r->size)
 911             continue;
 912
 913         new_addr = pci_bar_address(d, i, r->type, r->size);
 914
 915         /* bridge filtering */
 916         filtered_size = r->size;
 917         if (new_addr != PCI_BAR_UNMAPPED) {
 918             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 919         }
 920
 921         /* This bar isn't changed */
 922         if (new_addr == r->addr && filtered_size == r->filtered_size)
 923             continue;
 924
 925         /* now do the real mapping */
 926         if (r->addr != PCI_BAR_UNMAPPED) {
 927             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 928                 int class;
 929                 /* NOTE: specific hack for IDE in PC case:
 930                    only one byte must be mapped. */
 931                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 932                 if (class == 0x0101 && r->size == 4) {
 933                     isa_unassign_ioport(r->addr + 2, 1);
 934                 } else {
 935                     isa_unassign_ioport(r->addr, r->filtered_size);
 936                 }
 937             } else {
 938                 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
 939                                              r->filtered_size,
 940                                              IO_MEM_UNASSIGNED);
 941                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 942             }
 943         }
 944         r->addr = new_addr;
 945         r->filtered_size = filtered_size;
 946         if (r->addr != PCI_BAR_UNMAPPED) {
 947             /*
 948              * TODO: currently almost all the map funcions assumes
 949              * filtered_size == size and addr & ~(size - 1) == addr.
 950              * However with bridge filtering, they aren't always true.
 951              * Teach them such cases, such that filtered_size < size and
 952              * addr & (size - 1) != 0.
 953              */
 954             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 955                 r->map_func(d, i, r->addr, r->filtered_size, r->type);
 956             } else {
 957                 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
 958                             r->filtered_size, r->type);
 959             }
 960         }
 961     }
 962 }
 963
 964 static inline int pci_irq_disabled(PCIDevice *d)
 965 {
 966     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
 967 }
 968
 969 /* Called after interrupt disabled field update in config space,
 970  * assert/deassert interrupts if necessary.
 971  * Gets original interrupt disable bit value (before update). */
 972 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
 973 {
 974     int i, disabled = pci_irq_disabled(d);
 975     if (disabled == was_irq_disabled)
 976         return;
 977     for (i = 0; i < PCI_NUM_PINS; ++i) {
 978         int state = pci_irq_state(d, i);
 979         pci_change_irq_level(d, i, disabled ? -state : state);
 980     }
 981 }
 982
 983 uint32_t pci_default_read_config(PCIDevice *d,
 984                                  uint32_t address, int len)
 985 {
 986     uint32_t val = 0;
 987     assert(len == 1 || len == 2 || len == 4);
 988     len = MIN(len, pci_config_size(d) - address);
 989     memcpy(&val, d->config + address, len);
 990     return le32_to_cpu(val);
 991 }
 992
 993 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 994 {
 995     int i, was_irq_disabled = pci_irq_disabled(d);
 996     uint32_t config_size = pci_config_size(d);
 997
 998     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
 999         uint8_t wmask = d->wmask[addr + i];
1000         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1001     }
1002     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1003         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1004         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1005         range_covers_byte(addr, l, PCI_COMMAND))
1006         pci_update_mappings(d);
1007
1008     if (range_covers_byte(addr, l, PCI_COMMAND))
1009         pci_update_irq_disabled(d, was_irq_disabled);
1010 }
1011
1012 /***********************************************************/
1013 /* generic PCI irq support */
1014
1015 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1016 static void pci_set_irq(void *opaque, int irq_num, int level)
1017 {
1018     PCIDevice *pci_dev = opaque;
1019     int change;
1020
1021     change = level - pci_irq_state(pci_dev, irq_num);
1022     if (!change)
1023         return;
1024
1025     pci_set_irq_state(pci_dev, irq_num, level);
1026     pci_update_irq_status(pci_dev);
1027     if (pci_irq_disabled(pci_dev))
1028         return;
1029     pci_change_irq_level(pci_dev, irq_num, change);
1030 }
1031
1032 /***********************************************************/
1033 /* monitor info on PCI */
1034
1035 typedef struct {
1036     uint16_t class;
1037     const char *desc;
1038 } pci_class_desc;
1039
1040 static const pci_class_desc pci_class_descriptions[] =
1041 {
1042     { 0x0100, "SCSI controller"},
1043     { 0x0101, "IDE controller"},
1044     { 0x0102, "Floppy controller"},
1045     { 0x0103, "IPI controller"},
1046     { 0x0104, "RAID controller"},
1047     { 0x0106, "SATA controller"},
1048     { 0x0107, "SAS controller"},
1049     { 0x0180, "Storage controller"},
1050     { 0x0200, "Ethernet controller"},
1051     { 0x0201, "Token Ring controller"},
1052     { 0x0202, "FDDI controller"},
1053     { 0x0203, "ATM controller"},
1054     { 0x0280, "Network controller"},
1055     { 0x0300, "VGA controller"},
1056     { 0x0301, "XGA controller"},
1057     { 0x0302, "3D controller"},
1058     { 0x0380, "Display controller"},
1059     { 0x0400, "Video controller"},
1060     { 0x0401, "Audio controller"},
1061     { 0x0402, "Phone"},
1062     { 0x0480, "Multimedia controller"},
1063     { 0x0500, "RAM controller"},
1064     { 0x0501, "Flash controller"},
1065     { 0x0580, "Memory controller"},
1066     { 0x0600, "Host bridge"},
1067     { 0x0601, "ISA bridge"},
1068     { 0x0602, "EISA bridge"},
1069     { 0x0603, "MC bridge"},
1070     { 0x0604, "PCI bridge"},
1071     { 0x0605, "PCMCIA bridge"},
1072     { 0x0606, "NUBUS bridge"},
1073     { 0x0607, "CARDBUS bridge"},
1074     { 0x0608, "RACEWAY bridge"},
1075     { 0x0680, "Bridge"},
1076     { 0x0c03, "USB controller"},
1077     { 0, NULL}
1078 };
1079
1080 static void pci_for_each_device_under_bus(PCIBus *bus,
1081                                           void (*fn)(PCIBus *b, PCIDevice *d))
1082 {
1083     PCIDevice *d;
1084     int devfn;
1085
1086     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1087         d = bus->devices[devfn];
1088         if (d) {
1089             fn(bus, d);
1090         }
1091     }
1092 }
1093
1094 void pci_for_each_device(PCIBus *bus, int bus_num,
1095                          void (*fn)(PCIBus *b, PCIDevice *d))
1096 {
1097     bus = pci_find_bus(bus, bus_num);
1098
1099     if (bus) {
1100         pci_for_each_device_under_bus(bus, fn);
1101     }
1102 }
1103
1104 static void pci_device_print(Monitor *mon, QDict *device)
1105 {
1106     QDict *qdict;
1107     QListEntry *entry;
1108     uint64_t addr, size;
1109
1110     monitor_printf(mon, "  Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1111     monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1112                         qdict_get_int(device, "slot"),
1113                         qdict_get_int(device, "function"));
1114     monitor_printf(mon, "    ");
1115
1116     qdict = qdict_get_qdict(device, "class_info");
1117     if (qdict_haskey(qdict, "desc")) {
1118         monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1119     } else {
1120         monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1121     }
1122
1123     qdict = qdict_get_qdict(device, "id");
1124     monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1125                         qdict_get_int(qdict, "device"),
1126                         qdict_get_int(qdict, "vendor"));
1127
1128     if (qdict_haskey(device, "irq")) {
1129         monitor_printf(mon, "      IRQ %" PRId64 ".\n",
1130                             qdict_get_int(device, "irq"));
1131     }
1132
1133     if (qdict_haskey(device, "pci_bridge")) {
1134         QDict *info;
1135
1136         qdict = qdict_get_qdict(device, "pci_bridge");
1137
1138         info = qdict_get_qdict(qdict, "bus");
1139         monitor_printf(mon, "      BUS %" PRId64 ".\n",
1140                             qdict_get_int(info, "number"));
1141         monitor_printf(mon, "      secondary bus %" PRId64 ".\n",
1142                             qdict_get_int(info, "secondary"));
1143         monitor_printf(mon, "      subordinate bus %" PRId64 ".\n",
1144                             qdict_get_int(info, "subordinate"));
1145
1146         info = qdict_get_qdict(qdict, "io_range");
1147         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1148                        qdict_get_int(info, "base"),
1149                        qdict_get_int(info, "limit"));
1150
1151         info = qdict_get_qdict(qdict, "memory_range");
1152         monitor_printf(mon,
1153                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1154                        qdict_get_int(info, "base"),
1155                        qdict_get_int(info, "limit"));
1156
1157         info = qdict_get_qdict(qdict, "prefetchable_range");
1158         monitor_printf(mon, "      prefetchable memory range "
1159                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1160                        qdict_get_int(info, "base"),
1161         qdict_get_int(info, "limit"));
1162     }
1163
1164     QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1165         qdict = qobject_to_qdict(qlist_entry_obj(entry));
1166         monitor_printf(mon, "      BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1167
1168         addr = qdict_get_int(qdict, "address");
1169         size = qdict_get_int(qdict, "size");
1170
1171         if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1172             monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1173                                 " [0x%04"FMT_PCIBUS"].\n",
1174                                 addr, addr + size - 1);
1175         } else {
1176             monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1177                                " [0x%08"FMT_PCIBUS"].\n",
1178                                 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1179                                 qdict_get_bool(qdict, "prefetch") ?
1180                                 " prefetchable" : "", addr, addr + size - 1);
1181         }
1182     }
1183
1184     monitor_printf(mon, "      id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1185
1186     if (qdict_haskey(device, "pci_bridge")) {
1187         qdict = qdict_get_qdict(device, "pci_bridge");
1188         if (qdict_haskey(qdict, "devices")) {
1189             QListEntry *dev;
1190             QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1191                 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1192             }
1193         }
1194     }
1195 }
1196
1197 void do_pci_info_print(Monitor *mon, const QObject *data)
1198 {
1199     QListEntry *bus, *dev;
1200
1201     QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1202         QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1203         QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1204             pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1205         }
1206     }
1207 }
1208
1209 static QObject *pci_get_dev_class(const PCIDevice *dev)
1210 {
1211     int class;
1212     const pci_class_desc *desc;
1213
1214     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1215     desc = pci_class_descriptions;
1216     while (desc->desc && class != desc->class)
1217         desc++;
1218
1219     if (desc->desc) {
1220         return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1221                                   desc->desc, class);
1222     } else {
1223         return qobject_from_jsonf("{ 'class': %d }", class);
1224     }
1225 }
1226
1227 static QObject *pci_get_dev_id(const PCIDevice *dev)
1228 {
1229     return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1230                               pci_get_word(dev->config + PCI_VENDOR_ID),
1231                               pci_get_word(dev->config + PCI_DEVICE_ID));
1232 }
1233
1234 static QObject *pci_get_regions_list(const PCIDevice *dev)
1235 {
1236     int i;
1237     QList *regions_list;
1238
1239     regions_list = qlist_new();
1240
1241     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1242         QObject *obj;
1243         const PCIIORegion *r = &dev->io_regions[i];
1244
1245         if (!r->size) {
1246             continue;
1247         }
1248
1249         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1250             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1251                                      "'address': %" PRId64 ", "
1252                                      "'size': %" PRId64 " }",
1253                                      i, r->addr, r->size);
1254         } else {
1255             int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1256
1257             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1258                                      "'mem_type_64': %i, 'prefetch': %i, "
1259                                      "'address': %" PRId64 ", "
1260                                      "'size': %" PRId64 " }",
1261                                      i, mem_type_64,
1262                                      r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1263                                      r->addr, r->size);
1264         }
1265
1266         qlist_append_obj(regions_list, obj);
1267     }
1268
1269     return QOBJECT(regions_list);
1270 }
1271
1272 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1273
1274 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1275 {
1276     uint8_t type;
1277     QObject *obj;
1278
1279     obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d,"                                       "'class_info': %p, 'id': %p, 'regions': %p,"
1280                               " 'qdev_id': %s }",
1281                               bus_num,
1282                               PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1283                               pci_get_dev_class(dev), pci_get_dev_id(dev),
1284                               pci_get_regions_list(dev),
1285                               dev->qdev.id ? dev->qdev.id : "");
1286
1287     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1288         QDict *qdict = qobject_to_qdict(obj);
1289         qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1290     }
1291
1292     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1293     if (type == PCI_HEADER_TYPE_BRIDGE) {
1294         QDict *qdict;
1295         QObject *pci_bridge;
1296
1297         pci_bridge = qobject_from_jsonf("{ 'bus': "
1298         "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1299         "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1300         "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1301         "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1302         dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1303         dev->config[PCI_SUBORDINATE_BUS],
1304         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1305         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1306         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1307         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1308         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1309                                PCI_BASE_ADDRESS_MEM_PREFETCH),
1310         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1311                                 PCI_BASE_ADDRESS_MEM_PREFETCH));
1312
1313         if (dev->config[PCI_SECONDARY_BUS] != 0) {
1314             PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1315
1316             if (child_bus) {
1317                 qdict = qobject_to_qdict(pci_bridge);
1318                 qdict_put_obj(qdict, "devices",
1319                               pci_get_devices_list(child_bus,
1320                                                    dev->config[PCI_SECONDARY_BUS]));
1321             }
1322         }
1323         qdict = qobject_to_qdict(obj);
1324         qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1325     }
1326
1327     return obj;
1328 }
1329
1330 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1331 {
1332     int devfn;
1333     PCIDevice *dev;
1334     QList *dev_list;
1335
1336     dev_list = qlist_new();
1337
1338     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1339         dev = bus->devices[devfn];
1340         if (dev) {
1341             qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1342         }
1343     }
1344
1345     return QOBJECT(dev_list);
1346 }
1347
1348 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1349 {
1350     bus = pci_find_bus(bus, bus_num);
1351     if (bus) {
1352         return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1353                                   bus_num, pci_get_devices_list(bus, bus_num));
1354     }
1355
1356     return NULL;
1357 }
1358
1359 void do_pci_info(Monitor *mon, QObject **ret_data)
1360 {
1361     QList *bus_list;
1362     struct PCIHostBus *host;
1363
1364     bus_list = qlist_new();
1365
1366     QLIST_FOREACH(host, &host_buses, next) {
1367         QObject *obj = pci_get_bus_dict(host->bus, 0);
1368         if (obj) {
1369             qlist_append_obj(bus_list, obj);
1370         }
1371     }
1372
1373     *ret_data = QOBJECT(bus_list);
1374 }
1375
1376 static const char * const pci_nic_models[] = {
1377     "ne2k_pci",
1378     "i82551",
1379     "i82557b",
1380     "i82559er",
1381     "rtl8139",
1382     "e1000",
1383     "pcnet",
1384     "virtio",
1385     NULL
1386 };
1387
1388 static const char * const pci_nic_names[] = {
1389     "ne2k_pci",
1390     "i82551",
1391     "i82557b",
1392     "i82559er",
1393     "rtl8139",
1394     "e1000",
1395     "pcnet",
1396     "virtio-net-pci",
1397     NULL
1398 };
1399
1400 /* Initialize a PCI NIC.  */
1401 /* FIXME callers should check for failure, but don't */
1402 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1403                         const char *default_devaddr)
1404 {
1405     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1406     PCIBus *bus;
1407     int devfn;
1408     PCIDevice *pci_dev;
1409     DeviceState *dev;
1410     int i;
1411
1412     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1413     if (i < 0)
1414         return NULL;
1415
1416     bus = pci_get_bus_devfn(&devfn, devaddr);
1417     if (!bus) {
1418         error_report("Invalid PCI device address %s for device %s",
1419                      devaddr, pci_nic_names[i]);
1420         return NULL;
1421     }
1422
1423     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1424     dev = &pci_dev->qdev;
1425     qdev_set_nic_properties(dev, nd);
1426     if (qdev_init(dev) < 0)
1427         return NULL;
1428     return pci_dev;
1429 }
1430
1431 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1432                                const char *default_devaddr)
1433 {
1434     PCIDevice *res;
1435
1436     if (qemu_show_nic_models(nd->model, pci_nic_models))
1437         exit(0);
1438
1439     res = pci_nic_init(nd, default_model, default_devaddr);
1440     if (!res)
1441         exit(1);
1442     return res;
1443 }
1444
1445 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1446 {
1447     pci_update_mappings(d);
1448 }
1449
1450 void pci_bridge_update_mappings(PCIBus *b)
1451 {
1452     PCIBus *child;
1453
1454     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1455
1456     QLIST_FOREACH(child, &b->child, sibling) {
1457         pci_bridge_update_mappings(child);
1458     }
1459 }
1460
1461 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1462 {
1463     PCIBus *sec;
1464
1465     if (!bus) {
1466         return NULL;
1467     }
1468
1469     if (pci_bus_num(bus) == bus_num) {
1470         return bus;
1471     }
1472
1473     /* try child bus */
1474     if (!bus->parent_dev /* host pci bridge */ ||
1475         (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1476          bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1477         for (; bus; bus = sec) {
1478             QLIST_FOREACH(sec, &bus->child, sibling) {
1479                 assert(sec->parent_dev);
1480                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1481                     return sec;
1482                 }
1483                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1484                     bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1485                     break;
1486                 }
1487             }
1488         }
1489     }
1490
1491     return NULL;
1492 }
1493
1494 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1495 {
1496     bus = pci_find_bus(bus, bus_num);
1497
1498     if (!bus)
1499         return NULL;
1500
1501     return bus->devices[PCI_DEVFN(slot, function)];
1502 }
1503
1504 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1505 {
1506     PCIDevice *pci_dev = (PCIDevice *)qdev;
1507     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1508     PCIBus *bus;
1509     int devfn, rc;
1510
1511     /* initialize cap_present for pci_is_express() and pci_config_size() */
1512     if (info->is_express) {
1513         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1514     }
1515
1516     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1517     devfn = pci_dev->devfn;
1518     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1519                                      info->config_read, info->config_write,
1520                                      info->is_bridge);
1521     if (pci_dev == NULL)
1522         return -1;
1523     rc = info->init(pci_dev);
1524     if (rc != 0) {
1525         do_pci_unregister_device(pci_dev);
1526         return rc;
1527     }
1528
1529     /* rom loading */
1530     if (pci_dev->romfile == NULL && info->romfile != NULL)
1531         pci_dev->romfile = qemu_strdup(info->romfile);
1532     pci_add_option_rom(pci_dev);
1533
1534     if (bus->hotplug) {
1535         /* lower layer must check qdev->hotplugged */
1536         rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1537         if (rc != 0) {
1538             int r = pci_unregister_device(&pci_dev->qdev);
1539             assert(!r);
1540             return rc;
1541         }
1542     }
1543     return 0;
1544 }
1545
1546 static int pci_unplug_device(DeviceState *qdev)
1547 {
1548     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1549
1550     return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1551 }
1552
1553 void pci_qdev_register(PCIDeviceInfo *info)
1554 {
1555     info->qdev.init = pci_qdev_init;
1556     info->qdev.unplug = pci_unplug_device;
1557     info->qdev.exit = pci_unregister_device;
1558     info->qdev.bus_info = &pci_bus_info;
1559     qdev_register(&info->qdev);
1560 }
1561
1562 void pci_qdev_register_many(PCIDeviceInfo *info)
1563 {
1564     while (info->qdev.name) {
1565         pci_qdev_register(info);
1566         info++;
1567     }
1568 }
1569
1570 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1571                                     const char *name)
1572 {
1573     DeviceState *dev;
1574
1575     dev = qdev_create(&bus->qbus, name);
1576     qdev_prop_set_uint32(dev, "addr", devfn);
1577     qdev_prop_set_bit(dev, "multifunction", multifunction);
1578     return DO_UPCAST(PCIDevice, qdev, dev);
1579 }
1580
1581 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1582                                            bool multifunction,
1583                                            const char *name)
1584 {
1585     PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1586     qdev_init_nofail(&dev->qdev);
1587     return dev;
1588 }
1589
1590 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1591 {
1592     return pci_create_multifunction(bus, devfn, false, name);
1593 }
1594
1595 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1596 {
1597     return pci_create_simple_multifunction(bus, devfn, false, name);
1598 }
1599
1600 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1601 {
1602     int config_size = pci_config_size(pdev);
1603     int offset = PCI_CONFIG_HEADER_SIZE;
1604     int i;
1605     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1606         if (pdev->used[i])
1607             offset = i + 1;
1608         else if (i - offset + 1 == size)
1609             return offset;
1610     return 0;
1611 }
1612
1613 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1614                                         uint8_t *prev_p)
1615 {
1616     uint8_t next, prev;
1617
1618     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1619         return 0;
1620
1621     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1622          prev = next + PCI_CAP_LIST_NEXT)
1623         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1624             break;
1625
1626     if (prev_p)
1627         *prev_p = prev;
1628     return next;
1629 }
1630
1631 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1632 {
1633     cpu_register_physical_memory(addr, size, pdev->rom_offset);
1634 }
1635
1636 /* Add an option rom for the device */
1637 static int pci_add_option_rom(PCIDevice *pdev)
1638 {
1639     int size;
1640     char *path;
1641     void *ptr;
1642     char name[32];
1643
1644     if (!pdev->romfile)
1645         return 0;
1646     if (strlen(pdev->romfile) == 0)
1647         return 0;
1648
1649     if (!pdev->rom_bar) {
1650         /*
1651          * Load rom via fw_cfg instead of creating a rom bar,
1652          * for 0.11 compatibility.
1653          */
1654         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1655         if (class == 0x0300) {
1656             rom_add_vga(pdev->romfile);
1657         } else {
1658             rom_add_option(pdev->romfile);
1659         }
1660         return 0;
1661     }
1662
1663     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1664     if (path == NULL) {
1665         path = qemu_strdup(pdev->romfile);
1666     }
1667
1668     size = get_image_size(path);
1669     if (size < 0) {
1670         error_report("%s: failed to find romfile \"%s\"",
1671                      __FUNCTION__, pdev->romfile);
1672         return -1;
1673     }
1674     if (size & (size - 1)) {
1675         size = 1 << qemu_fls(size);
1676     }
1677
1678     if (pdev->qdev.info->vmsd)
1679         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1680     else
1681         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1682     pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1683
1684     ptr = qemu_get_ram_ptr(pdev->rom_offset);
1685     load_image(path, ptr);
1686     qemu_free(path);
1687
1688     pci_register_bar(pdev, PCI_ROM_SLOT, size,
1689                      0, pci_map_option_rom);
1690
1691     return 0;
1692 }
1693
1694 static void pci_del_option_rom(PCIDevice *pdev)
1695 {
1696     if (!pdev->rom_offset)
1697         return;
1698
1699     qemu_ram_free(pdev->rom_offset);
1700     pdev->rom_offset = 0;
1701 }
1702
1703 /*
1704  * if !offset
1705  * Reserve space and add capability to the linked list in pci config space
1706  *
1707  * if offset = 0,
1708  * Find and reserve space and add capability to the linked list
1709  * in pci config space */
1710 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1711                        uint8_t offset, uint8_t size)
1712 {
1713     uint8_t *config;
1714     if (!offset) {
1715         offset = pci_find_space(pdev, size);
1716         if (!offset) {
1717             return -ENOSPC;
1718         }
1719     }
1720
1721     config = pdev->config + offset;
1722     config[PCI_CAP_LIST_ID] = cap_id;
1723     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1724     pdev->config[PCI_CAPABILITY_LIST] = offset;
1725     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1726     memset(pdev->used + offset, 0xFF, size);
1727     /* Make capability read-only by default */
1728     memset(pdev->wmask + offset, 0, size);
1729     /* Check capability by default */
1730     memset(pdev->cmask + offset, 0xFF, size);
1731     return offset;
1732 }
1733
1734 /* Unlink capability from the pci config space. */
1735 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1736 {
1737     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1738     if (!offset)
1739         return;
1740     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1741     /* Make capability writeable again */
1742     memset(pdev->wmask + offset, 0xff, size);
1743     /* Clear cmask as device-specific registers can't be checked */
1744     memset(pdev->cmask + offset, 0, size);
1745     memset(pdev->used + offset, 0, size);
1746
1747     if (!pdev->config[PCI_CAPABILITY_LIST])
1748         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1749 }
1750
1751 /* Reserve space for capability at a known offset (to call after load). */
1752 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1753 {
1754     memset(pdev->used + offset, 0xff, size);
1755 }
1756
1757 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1758 {
1759     return pci_find_capability_list(pdev, cap_id, NULL);
1760 }
1761
1762 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1763 {
1764     PCIDevice *d = (PCIDevice *)dev;
1765     const pci_class_desc *desc;
1766     char ctxt[64];
1767     PCIIORegion *r;
1768     int i, class;
1769
1770     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1771     desc = pci_class_descriptions;
1772     while (desc->desc && class != desc->class)
1773         desc++;
1774     if (desc->desc) {
1775         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1776     } else {
1777         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1778     }
1779
1780     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1781                    "pci id %04x:%04x (sub %04x:%04x)\n",
1782                    indent, "", ctxt,
1783                    d->config[PCI_SECONDARY_BUS],
1784                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1785                    pci_get_word(d->config + PCI_VENDOR_ID),
1786                    pci_get_word(d->config + PCI_DEVICE_ID),
1787                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1788                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1789     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1790         r = &d->io_regions[i];
1791         if (!r->size)
1792             continue;
1793         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1794                        " [0x%"FMT_PCIBUS"]\n",
1795                        indent, "",
1796                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1797                        r->addr, r->addr + r->size - 1);
1798     }
1799 }
1800
1801 static char *pcibus_get_dev_path(DeviceState *dev)
1802 {
1803     PCIDevice *d = (PCIDevice *)dev;
1804     char path[16];
1805
1806     snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1807              pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1808              PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1809
1810     return strdup(path);
1811 }
1812